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PHYSC 3322
Experiment 1.5
14 May, 2017
Digital Devices
Purpose
This experiment will introduce you to the basic operating principles of digital electronic
devices.
Background
These circuits are called digital devices because the signals they receive and transmit
carry discrete information. That is, the input and output voltages are interpreted by the
circuits as representing discrete numerical quantities, like 0 and 1.
The integrated circuits you will be using in this experiment are transistor-transistor
logic (TTL) devices. TTL devices are designed to operate from a 5 V power supply. If
the power supply voltage is below 4.75 V, the devices will work erratically, and if the
voltage is above 5.25 V, the devices may be damaged. At an input of a TTL device, if
the voltage is 0.0–0.8 V, the signal is interpreted as a 0. If the voltage is 2.0–5.0 V, the
signal is interpreted as a 1. At an output of a TTL device, the voltage is guaranteed to
be less than 0.5 V if the signal is to be interpreted as a 0, and greater than 2.4 V if the
signal is to be interpreted as a 1. As you can see, there is a built-in error margin of
about 0.4 V; this is intended to avoid problems if a small amount of noise is induced on
the signal lines by nearby circuitry.
By using these very simple logical interpretations of the voltages on the various
conductors in a circuit, it is possible to build devices as complex as a computer, which
contains the equivalent of many tens of thousands of simple TTL circuits.
Procedure
Clock oscillator: Most digital circuits require a clock signal. This is simply a periodic
digital waveform, which alternates between 0 and 1 states at some chosen frequency.
(When a personal computer is advertised as having a 66 MHz CPU, for example, the 66
MHz refers to the clock frequency used in the computer. As you might imagine, the
higher the clock frequency, the more operations can be performed in a given amount of
time.)
For this experiment, you will build a clock oscillator using a common integrated circuit
known as a 555 timer. (The 555 is actually not a TTL device, but if you operate it from a
5 V power supply, it produces a signal which is compatible with TTL devices.) Figure 1
shows the names of the connections to the 555. For now, you don't need to worry what
all of the names mean, but do note that two of the pins have a horizontal bar over their
names. This means that the signal is active low, rather than active high, which is the
standard for TTL devices. So, for example, the reset pin on the 555 chip is active low,
meaning that you need to place a 0 signal on that pin in order to reset the timer.
Construct the oscillator circuit shown in Figure 2 on your breadboard. Place the circuit
near one end of the breadboard, so that you have room for the other circuits which will
be added later. Connect a 5 V power supply to your circuit, and observe the signal at
the out pin of the 555 on an oscilloscope. Using the second channel of the oscilloscope,
observe the signal at the threshold pin as well. Note the relationship between this
signal and the output signal, and also note that the output transitions between the 0
and 1 states occur when the voltage at the threshold pin is at 1/3 and 2/3 of the power
supply voltage. Sketch the waveforms, including the voltage scale. Measure the output
frequency and record it.
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PHYSC 3322
Experiment 1.5
Figure 1. Pin diagram of the 555 timer
integrated circuit.
14 May, 2017
Figure 2. Clock oscillator circuit.
Binary-coded decimal counter: Next, you will use your clock oscillator to drive a
counter. The counter device is a 74LS160, which counts in the sequence 0, 1, 2, ..., 9, 0, 1,
2, ..., 9, etc., repeating every ten counts. This is why it is called a decimal counter. Since
TTL logic is only capable of representing 0 and 1, it is necessary to use a binary
encoding to represent the numbers from 0 to 9, and this is done according to the
following table:
decimal
binary
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
Since a minimum of four binary digits (bits) are required to represent the numbers from
0 to 9, the circuit must use four signal lines, one for each bit. Figure 3 shows the
connection diagram for the 74LS160 device. The input clock signal is applied to the
CLK input, and the four output signals are QA through QD. (There are a number of
other signal inputs and outputs, which will not be used in this experiment.) QA is the
least-significant bit (LSB), the rightmost bit in the table above. QD is the most-significant
bit (MSB), the leftmost bit in the table above. Every time the signal at the CLK input
changes from 0 to 1, the counter increments its count and the output signals change
accordingly.
Construct the circuit shown in Figure 4 (place it next to the clock oscillator circuit).
Connect the output of the clock oscillator to the CLK input of the counter. With channel
1 of the oscilloscope still connected to the output of the oscillator, connect channel 2 to
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PHYSC 3322
Experiment 1.5
14 May, 2017
the QA output of the counter. According to the table, the QA output should alternate
between 0 and 1, changing for each count. Verify that this is the case, and also note that
the change does indeed occur when the clock input changes from 0 to 1. Sketch the
waveforms.
Next, connect channel 2 of the oscilloscope to the QD output. According to the table,
this output should make a single 0 to 1 transition for every count cycle (i.e., for every
ten input transitions). Verify that this is the case, and sketch the waveforms.
Figure 3. Pin diagram of the 74LS160 binary-coded
decimal counter integrated circuit.
Figure 4. Binary-coded decimal counter circuit.
Digital display: You now have a decimal counter, which is a useful building block and
can be used in a variety of devices. However, the count is emitted in binary notation,
while humans are used to seeing numbers in decimal notation. To display the numbers,
you will use a 7-segment light-emitting diode array. And to convert the binary numbers
so that they can be shown on this display, you will use a 74LS47 BCD to 7-segment
converter. The connection diagram for the 74LS47 is shown in Figure 5, and the
connection diagram for the 7-segment display is shown in Figure 6. Because of the way
the 7-segment display is designed, a current-limiting resistor must be inserted between
each output from the 74LS47 and the corresponding input of the display. Since
handling so many individual resistors is unwieldy, you will use a 4116R resistor
network device. This device consists simply of eight resistors in a single package, as
shown in Figure 7.
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PHYSC 3322
Experiment 1.5
14 May, 2017
Figure 5. Pin diagram of the 74LS47 BCD to 7-segment
decoder integrated circuit.
Figure 6. Pin diagram of the 7-segment display.
Figure 7. Pin diagram of the 4116R resistor network.
Construct the circuit shown in Figure 8. Place the 74LS47 nearest the 74LS160 counter,
the resistor network adjacent to the 74LS47, and the display adjacent to the resistor
network.
Apply power to the circuit and observe the display. Since the counter is counting at a
very high rate, the numbers on the display will be a blur, and will just look like an 8. To
slow the counter down, replace the 100 nF capacitor in the clock oscillator with a 22 µF
capacitor. Now observe the count and verify that it increments as expected.
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PHYSC 3322
Experiment 1.5
14 May, 2017
Figure 8. Decoder and display circuit.
Questions
According to the manufacturer, the output frequency of a 555 timer connected as
shown in Figure 2 should have an output frequency given by
f 
1
ln 2R1  2R2 C 1
.
(1)
Verify that this is the case in your circuit. Remember that 1 F  1   1 s .
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