Download 2-6 A 7nm CMOS Platform Technology Using EUV Lithography

A 7nm CMOS Platform Technology Using EUV Lithography: The 7nm FinFET technology to be disclosed by the IBM/Globalfoundries/Samsung technology
development alliance is the first integrated platform technology to use extreme ultraviolet (EUV) light to pattern transistors. A long-anticipated development, EUV
lithography may become a requirement for ultra-small devices because the wavelength of EUV light is much shorter than that of the light currently used (13.5nm
vs. 193nm) and it simplifies patterning. Here, EUV lithography and other advanced patterning approaches have led to the tightest contacted polysilicon pitch
(44/48nm) and metallization pitch (36nm) ever reported for FinFETs. The technology also features dual-strained channels on a thick strain-relaxed buffer (SRB)
virtual substrate to combine tensile-strained NMOS and compressively strained SiGE PMOS for enhancement of drive current by 11% and 20%, respectively,
versus a common planar HKMG process. It also features novel trench epitaxy to minimize the resistance of the highly scaled contact regions.
At top left is a schematic description of dual-stressed channel materials on the SRB with a super-steep retrograde well (SSRW), along with TEM images of (a) the
tensile strained silicon fin and (b) the compressively strained SiGe fin on a common SRB. At top right is a TEM image of a 48nm contacted polysilicon pitch
device with an optimized self-aligned contact with a contact opening of ~10nm and Lmetal of ~15nm.
The bottom illustration and graph show that the trench epitaxial process simultaneously meets ground rules and contact resistivity reduction following implant and
anneal optimizations.
(Paper #2.6, “A 7nm FinFET Technology Featuring EUV Patterning and Dual-Strained High-Mobility Channels,” R. Xie et al, IBM/Globalfoundries/Samsung)