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UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on Feb 26, 2006 by Bill Tsang (ctsang@eecs)
Borivoje Nikolic Homework #6: CMOS Scaling, CMOS logic and logical effort
EECS 141
Problem #1: Process Scaling
A state-of-the-art microprocessor from a company in the valley consumes 10mW/MHz
when fabricated using a 0.13 m CMOS process. The area of the processor is 100 mm2.
Assume a 2GHz clock frequency, and 1.2V power supply for the 0.13m process.
Assume that the manufacturing cost of a chip is $0.5/mm2. Assume short channel
devices, but ignore second order effects like mobility degradation, series resistance, etc.
Also, ignore the leakage power (although it might be significant in real life).
a) If the supply voltage in the scaled 0.13m processor is then reduced to 1.0V, what
will be the power consumption and power density?
b) Using full scaling, what will be the area, power consumption, and power density of
the original processor if it is scaled to a 90nm technology? Assume that the clock
frequency stays at 2GHz.
c) Compare the manufacturing cost of the chip in the 0.13m process and the 90nm
process if the cost per area is the same in both processes?
d) Now, if the company adds 10% more circuits when the microprocessor scales from
the 0.13m to a 90nm process. Find the manufacturing cost of the new chip in the
90nm process.
e) Assuming the same power consumption, how fast can the new processor in 90nm
process powered at 1.0V be clocked without exceeding the power consumption of the
original processor(Assume that the speed is not limited by technology)?
Problem #2 – CMOS Logic
VDD
PUN
Y
A
E
B
C
D
Consider the CMOS logic gate given above.
a) Determine the logic function of the gate.
b) Draw the pull-up network (ensure that you use a minimum number of transistors).
c) Size it such that it has the same worst case pull-up/pull-down strength as a minimum
sized 2/1 inverter.
Problem #3 Fanout and NAND Chain Delay - SPICE
(It might help if you study HW5 solution first)
From eq. (6.6) in the book, we have that:
Tp=tp0(p+g*f/γ)
In this problem, we will look into the parameters γ, p, g for a NAND and how to find
them using SPICE. Let Vdd=2.5v, and use the following for your simulations:
.lib '/home/ff/ee141/MODELS/g25.mod' TT
.subckt NAND2 Vdd Gnd VinA VinB Vout
Mp1 Vout VinA Vdd Vdd pmos l=0.24u w=0.6u
Mp2 Vout VinB Vdd Vdd pmos l=0.24u w=0.6u
Mn1 Vout VinA vmid Gnd nmos l=0.24u w=0.72u
Mn2 vmid VinB Gnd Gnd nmos l=0.24u w=0.72u
.ends
a) Connect one terminal of the NAND gate to Vdd. Run a transient simulation for a
single unloaded NAND with a 1uA current charging the input from 0 to 2.5v (you
may have done this already in your HW5. Please refer to HW 5 solution).
Estimate the input capacitance from the waveform at the input. Also, what is the
worst case instantaneous input capacitance?
Hint: You can use Measure->Point in Awaves to see the slope of the input voltage
when it’s moving the most slowly
b) Measure the propagation delay for a sharp rising edge going through a single
NAND driving loads of 0 through 100fF(Remember to connect one input to Vdd).
Extrapolate an estimate of the intrinsic output capacitance. Assume
p=Cint(NAND)/Cint(INV). What is the value of the parameter p. (You need to
use the result of HW5).
c) So far, we’ve run the NAND with fictitious inputs and loads. To better capture
how it would behave in a real environment, simulate a geometrically tapered
chain of 8 NANDs with fanout factor f. Give a sharp rising edge at the input of
the first inverter and a large capacitor loading the last. Use your estimate of input
capacitance from part a) to scale this load to emulate a continuation of the NAND
chain. Measure the propagation delay of a NAND in the middle of the chain, for
fanouts of 1 through 5, and estimate γ/g from the results. Then find g as we
already know γ from HW5 solution
Tip: Rather than measuring the delay through a single NAND, measure across a
consecutive pair of NANDs, and take half of that delay. This will average out the
differences between rising and falling edges, and also make the measurement
independent of the switch level you use to trigger the delay measurement.
Tip: You can use a multiplier factor when instantiating an NAND in the chain, e.g.
XNAND1 vdd 0 vdd v1 v2 NAND2
XNAND2 vdd 0 vdd v2 v3 NAND2 M='fanout'
d) How does p, g of a NAND gate compare to what you expect in theory. How do
your results compare? Speculate on which values can be trusted and why the
others may be questionable. Suggest other approaches for extracting the suspected
parameters.