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UNIVERSITY OF CALIFORNIA
College of Engineering
Department of Electrical Engineering and Computer Sciences
Last modified on October 13, 2001 by Henry Lam ([email protected])
Borivoje Nikolic
Homework #6 Solutions
EECS 141
PROBLEM 1
1. F = ! ((a * b) + (c * (d + e))) Draw the complementary CMOS circuit that
implements this function. Size it such that it has the same pull-up/pull-down
strength as a minimum sized 2/1 inverter.
2. Draw (or fire up MAX and draw it there) the layout that would share the most
diffusions (do not worry about the correct transistor widths). Show the Euler Path
used to arrive at your solution.
3. For the sizing used in part 1, find the logical efforts (g) of the gate for all 5 of the
inputs. Are they the same or different?
A
B
C
D
E
g = (4 + 2)/3 = 2
g = (4 + 2)/3 = 2
g = (4 + 2)/3 = 2
g = (8 + 2)/3 = 10/3
g = (8 + 2)/3 = 10/3
The Logical Effort for each input is different.
4. Resize the circuit such that it has the same strength as a 4/1 (skewed-HI) inverter.
What are the logical efforts of the gate for each of the 5 inputs now?
A
B
C
D
E
g = (8 + 2)/6 = 5/3
g = (8 + 2)/6 = 5/3
g = (8 + 2)/6 = 5/3
g = (16 + 2)/6 = 3
g = (16 + 2)/6 = 3
Remember that since we are skewing the circuit high such that it has a pull-up of 4, we
need to compare it to a 4/2 (6) instead of a 2/1 (3) inverter.
PROBLEM 2
Find the delay of each of the four circuits using logical effort (use a spreadsheet or
anything to keep track of the numbers. This problem isn’t hard—just bookkeeping).
Which one is the fastest? Draw out the fastest implementation of the 8-input-AND gate
and size them such that the optimal performance is achieved. Why (or why not) does a
four-stage AND make sense given the load constraint of this problem?
The logical efforts of these gates are:
INV
2-input-NAND
4-input NAND
2-input-NOR
4-input-NOR
1
4/3
6/3 = 2
5/3
9/3 = 3
H = 50, B = 1, F = BGH. Stage effort (f) = F ^ (1/4) since there are 4 stages. The delay t
through each circuit element = p + g * h. The following table finds the delay through
each circuit
circuit a
delay:
circuit b
delay:
circuit c
delay:
circuit d
delay:
G = 4/3 * 1 * 2 * 1 = 8/3
2NAND
INV
4NAND
2 + 3.40
1 + 3.40
4 + 3.40
F = 8/3 * 50 = 400/3 = 133.3
INV
1 + 3.40
Total Delay: 21.6
f = 3.40
G = 1 * 3 * 4/3 * 1 = 4
INV
4NOR
1 + 3.76
4 + 3.76
F = 4 * 50 = 200
INV
1 + 3.76
Total Delay: 23.04
f = 3.76
G = 4/3 * 5/3 * 1 * 5/3 = 100/27
2NAND
2NOR
INV
2 + 3.69
2 + 3.69
1 + 3.69
F = 100/27 * 50 = 185.16
2NOR
2 + 3.69
Total Delay: 21.8
f = 3.69
G = 1 * 5/3 * 2 * 1 = 10/3
INV
2NOR
4NAND
1 + 3.59
2 + 3.59
4 + 3.59
F = 10/3 * 50 = 500/3 = 166.67
INV
1 + 3.59
Total Delay: 22.4
f = 3.59
2NAND
2 + 3.76
Thus, circuit (a) is the fastest of the four circuit topologies.
h = f/g (3.40 / g). Thus, the electrical effort (h) of each stage is:
Gate
2NAND (g = 4/3)
INV (g = 1)
4NAND (g = 2)
INV (g = 1)
Electrical Effort
2.55
3.40
1.7
3.40
The sizing of the circuit looks like:
The unit widths represent the total width it can present to the preceding input. So, for
example, the 2NAND can present a total of 6 unit widths and we know for a 2-input
NAND, the ratio between the pmos and nmos sizes is 1. Thus, each pmos and nmos
should have a unit width of 3 (3 + 3 = 6). For the 4NAND, the nmos needs to be twice the
width of pmos to get equivalent pull-up/down as a min sized inverter. Thus, the pmos
width of the 4NAND is 17.3 units and the nmos has a width of 34.6 units (34.6 + 17.3 =
51.9 and it preserves the correct ratio between pmos and nmos).
Using 4 stages makes a lot of sense in the case of the loads. Since H = 50, we can
estimate G to turn out to be ~ 3 or so and we know B = 1. Thus, we can say that F = 150.
For a stage effort of 4, 150 ^ (1/N) = 4 => N = 3.6. If the G was higher (a worst case),
then N would also be higher bumping that value to be up around 4. Thus, using a 4 stage
AND gate should provide close to optimal performance.
PROBLEM 3
Figure 1. XNORT path.
1. A three-input XNORT gate (see insert above) works like a two-input NOR as long
as input A is high; otherwise, the output is stuck high. Implement the XNORT gate
in complementary CMOS, and size all transistors such that the worst-case delay
is equal to that of a minimum sized 2/1 inverter. Find the logical effort associated
with each input.
.
The complementary CMOS implementation is to the left.
Logical effort is defined as the ratio of input capacitance
of a gate (considering only one input) to the input
capacitance of an inverter with the same output current.
This gives us:



gA=(2+2)/(2+1)=4/3
gB=(4+2)/(2+1)=2
gC=(4+2)/(2+1)=2
2. Assuming all input combinations are equally likely, what is the transition activity
(probability) of a XNORT gate? Averaged over many cycles, will a XNORT gate
typically consume more or less power than a two-input NOR gate, if they both
drive equally large output loads? What about a two-input XOR?
The transition probability of the gate is
P(F:01) = P(F=0)P(F=1) = 3/8  5/8 = 15/64  0.23
The transition probability of a two-input NOR (again with all inputs
assumed equally likely) is 3/16  0.19, lower than the XNORT. With the
simplifying assumption that the output load is large (which lets us forget
about differences in intrinsic capacitance), we can confidently assert that
the XNORT will on average consume more dynamic power.
The transition probability of a two-input XOR is 0.25, which is slightly more than the
XNORT. Therefore, we would expect the XNORT to consume less power, on average.
3. For the logic path from node (1) to node (2) shown in Figure 1, find the path
branching effort, path electrical effort, path logical effort, and total path effort.
What is the optimum effort per stage for minimizing delay?
A missing piece of information in this problem is the size of the gates that are off-path.
For simplicity, these can be assumed to be sized equal to the on-path gate of the same
type, whatever that is chosen to be.
The path branching effort (product of stage branching efforts, which are the ratios of total
driven capacitance to capacitance driven on the path) is:
B = 1  3  1  2 1=6
The path electrical effort (ratio of output capacitance to input capacitance) is:
H = CL/Cin = 18fF/3fF = 6
The path logical effort (product of stage logical efforts), using results from both the
lectures and earlier in this problem, is:
G = ginv  gxnort,a  gnand  gxnort,b  gnor = 1  4/3  4/3  2  5/3 = 160/27
The total path effort is then F= GBH = 160/27  6  6 = 160  4/3.
The optimum effort per stage for this five stage path is F1/5  2.92.
4. Find the input capacitances {w, x, y, z} necessary for each of the gates in the path
in order to achieve the optimum effort per stage.
The electrical effort for the nor (last gate in the path) is:
h = CL/z
The effort for the stage is f = gh => z = gnorCL/f  (5/3)/(2.9) 18fF  10.3fF
The electrical effort for the second xnort is:
h  2  10.3fF/y
Here, y  20.6fF gxnort,b/f  20.6fF 2/2.92  14.1fF.
The electrical effort for the nand is:
h  14.1fF/x
x  14.1fF gnand/f  14.1fF (4/3)/ 2.92  6.4fF
The electrical effort for the first xnort is:
h  3  6.4fF/w
w  19.2fF gxnort,a/f  19.2fF (4/3)/2.92  8.8fF
As a check, we see that the first stage effort is
f = ginvh = 1  8.8fF/3fF  2.93, which closely matches our calculated optimum effort per
stage.