Download EE 586 VLSI System Design

EE 586 VLSI System Design
Homework Assignment # 4
Due December 3, 2008
Problem 1: CMOS Logic
a) Do the following two circuits (Figure below) implement the same logic function? If
yes, what is that logic function? If no, give Boolean expressions for both circuits.
Answer: Circuit A: F  ABCD  E , Circuit B: F  ABCD  E , Yes as shown by
Boolean functions.
b) Will these two circuits’ output resistances always be equal to each other?
Answer: Rpull_down is the same for both circuits. Since the transistors in each circuit are
sized for symmetric switching we have the Rpull_down =Rpull_up, thus the output resistances
for the circuits are the same.
c) Will these two circuits’ rise and fall times always be equal to each other? Why or why
not?
Answer: The rise and fall times of these circuits will not always be equal because C L_A =
29C while CL_B = 11C. This difference in intrinsic capacitance at the output node results
in differing rise and fall times for the two circuits.
Problem 2: Differential Buffer
Design and simulate a circuit that generates an optimal differential signal as shown in the
Figure below. Make sure the rise and fall times are equal.
Answer:
A
A=Y
Size the inverter for symmetric
switching and then size the pass gate to
have the same resistance as either Rp or
Rn of the inverter. NB that Rn//Rp for the
pass gate. The configuration ensures
that the inverter delay is the same as the
pass gate delay.
A=Y
The traces showing A, A=Y and A_bar=Y_bar are shown below. A little fine tuning in
transistor sizing can provide the exact 50 % switching point for both rising and falling
edges.
Problem 3: Pass Transistor Logic
The Figure below shows a pass-gate logic network.
a) Determine the truth table for the circuit. What logic function does it implement?
Answer:
A
B
OUT (XNOR)
0
0
1
0
1
0
1
0
0
1
1
1
b) If the PMOS were removed, would the circuit still function correctly? Does the
PMOS transistor serve any useful purpose?
Answer: Removing the PMOS puts the gate in high Z (high impedance) for A=B=0,
therefore the gate no longer finctions properly without the PMOS.
A
OUT
B
Problem 4: Logic Family
Design a 4:1 multiplexer using
a) static CMOS
S1S0 S1S0 S1S0 S1S0
D0
S0
D0
0
D1
1
S1
D1
0
Y
Y
D2
0
D3
1
1
D2
D3
I should have provided a gate level 4:1 mux that requires 40 transistors to implement,
but this is simple even though it requires that the select signals be encoded, suggest a
way of doing so.
b) pass transistor logic
Answer:
A
B
Vout
C
D
S1
S1 S2 S2
c) pass gates
Answer: For each transistor in the circuit of the pass transistor circuit of (b) add a
PMOS device and drive its gate terminal with the inverse of the signal driving the
corresponding NMOS.
d) Comment on the three designs i.e. under what circumstances would you use one
over another?
Answer: Pass transistor circuit requires very few transistors good for area. The static
CMOS implementation would be good for full rail to rail swing, but this can be
provided by the pass gate implementation.
e) You will have to provide the equation that describes the multiplexing function.
Answer: Vout  AS1 S 2  BS1 S 2  CS1 S 2  DS1 S 2
The expression is based on my pass transistor logic circuit, just replace A, B, C and D
with D0, D1, D2 and D3 for the static CMOS representation.