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Journal of the Korean Physical Society, Vol. 40, No. 1, January 2002, pp. 56∼59
Abnormal ID –VD Curves Due to Contact Structures in ULSI Devices
Yong Hae Kim∗
Advanced Micro-Electronics Research Lab., Electronics and Telecommunications Research Institute, Taejon 305-350
Jong Oh Kim, Kuk Seung Yang, Sang Hee Lee and Young Hoon Kim
TG–1/P1, Memory Research and Development Division, Hynix Semiconductor, Ichon 467-701
(Received 11 February 2001)
We have analyzed the transistor characteristics for various contact structures in ULSI devices.
Abnormal ID –VD curves are observed with contact structure variations even though the contact
resistance is ohmic. The saturation current, the contact resistance, and the number of drain contacts
have a major effect on the abnormal behavior. We derive the variable, IDSAT RD /ND , over which
the abnormal ID –VD curves are observed.
PACS numbers: 85.30.De
reported layout-dependent device characteristics. The
driving-current reduction, which depends on the diffusion overlap of the gate, was explained by the mobility
degradation induced by the trench stress. In this paper we analyze the transistor characteristics for various
contact structures.
I. INTRODUCTION
As DRAM technology enters into the deep submicron
era, the effects of the contact resistance and the contact layout on the transistor characteristics are becoming more important [1,2]. Models have been developed
for the uniform sheet resistance or the uniform contact
resistance, which decreases as the transistor width is increased [3–6]. Moon et al.
[3] derived an analytical model for pMOS based on the unified charge control model. The parasitic resistance is included by using
VDS = Vds −IDS (RS +RD ). Chen et al. [4] reported the
semi-empirical saturation drain current model for lightly
doped drain (LDD) nMOS including velocity saturation,
the mobility degradation due to increased vertical effective field, and the source/drain series resistance of LDD
structure. Chyau and Jang [5] presented a physics-based
and analytic I–V model for submicron buried-channel
pMOS including the short channel effects such as drain
induced barrier lowering, channel length modulation, velocity saturation, mobility degradation due to the transverse electric field, and uniform parasitic source/drain
resistance.
Recently, the effects of nonuniform parasitic resistance, such as the contact resistance and the contact
layout details, have been a topic of considerable interest
[7, 8]. Lee et al.
[7] analyzed the contact structuredependent hot-carrier effect. Hot-carrier degradaton increases rapidly as the number of contact holes is increased while the current-driving capability improves
moderately. They developed a HSPICE circuit model
to simulate various contact structures. Scott et al. [8]
∗ E-mail:
II. EXPERIMENTAL
The devices were fabricated using 0.13µm DRAM
technology with a 65 Å gate oxide, a polymetal
(W/WNx/Poly) gate, and a W direct bitline contact
both at the nMOS and the pMOS. We designed the following bitline contact structures shown in Fig. 1: N/N
contact (N = 12 for W = 10 µm, N = 5 for W = 4 µm,
and N = 2 for W = 2 µm), N/1 contact, 3/1 contact, and
1/1 conact. Also, the bitline contact to wordline spacing
was varied. The contact size was 0.2 µm × 0.2 µm.
Fig. 1. Schemetic diagram of various contact sturctures:
(a) N/N contact (N = 12 for W = 10 µm, N = 5 for W = 4
µm, N = 2 for W = 2 µm), (b) N/1 contact, (c) 3/1 contact,
and (d) 1/1 contact.
[email protected]
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Abnormal ID –VD Curves Due to Contact Structures in ULSI Devices – Yong Hae Kim et al.
III. RESULTS AND DISCUSSTION
Figure 2 shows the ID –VD characteristics of the (a)
source/drain (S/D) = N/N contact and the (b) S/D =
1/1 contact. Abnormal ID –VD curves (a current damping in the linear region), which are more exaggerated as
the gate voltage (VG ) is increased, are observed in the
S/D = 1/1 contact structures for both the nMOS and
the pMOS. To extract the relationship between the contact structures and the abnormal curves, we measure the
ID –VD curves of the (a) nMOS and the (b) pMOS for
VDSAT
various contact structures [Fig. 3].
As the number of source contact (NS ) is decreased
from N to 1, the saturation current (IDSAT ) is decreased
by 40% independently of the number of drain contact
(ND = N, 3, 1). However, when the ND is decreased
from N to 1, the saturation voltage (VT SAT ) is increased
about 0.5 V independently of the number of source contact. That behavior can be explained with Hu’s model by
separating the source and the drain contact resistances
[4]:
2
1
−
RS + · · ·
VGS − VT
VGS − VT + ESAT L
2
1
= VDSAT 0 + IDSAT 0 · RD + IDSAT 0 2
−
(R∗ − RD )RS + · · ·
VGS − VT
VGS − VT + ESAT L
IDSAT = IDSAT 0 − IDSAT 0 2
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(1)
(2)
From the above equation, the saturation current mainly
depends on the source contact resistance (RS ) while the
saturation voltage is affected by the drain contact resistance (RD ).
However, the abnormal ID –VD curves which occur at
S/D = N/1, 3/1, 1/1 contact structures in the nMOS
and at S/D = N/1, 3/1, 1/1, 1/3 contact structures in
the pMOS with VG = 2.5 V cannot be explained. The
fact that when the number of drain contacts is reduced
the abnormal ID –VD curves are more easily observed implies that the drain contact resistance has an important
role. To confirm the contact resistance effects, we split
the contact resistance, 2kΩ/240Ω(pMOS/nMOS) of base
Fig. 2. ID –VD curves with VG = 1 V∼4 V of nMOS (Lg =
0.24 µm) and pMOS (Lg = 0.29 µm) in the (a) source/drain
(S/D) = N/N contact and (b) S/D = 1/1 contact structures.
Fig. 3. ID –VD curves at VG = 2.5 V with various source
and drain contact structures of (a) nMOS (Lg = 0.24 µm)
and (b) pMOS (Lg = 0.29 µm).
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Journal of the Korean Physical Society, Vol. 40, No. 1, January 2002
Fig. 6. Useful variable, IDSAT RD /ND , as a function of the
saturation current. The abnormal behavior is observed when
IDSAT RD /ND is above 500 mV in pMOS and above 1000mV
in nMOS.
Fig. 4. Changes of (a) contact resistance in the contact
chain pattern and (b) ID –VD characteristics of nMOS and
pMOS between the base process and the process A.
Fig. 5. ID –VD curves at VG = 2 V for various transistor
widths and contact numbers in nMOS (Lg = 0.24 µm) and
pMOS (Lg = 0.29 µm).
process versus 10.5kΩ/330Ω(pMOS/nMOS) of process A
in which the contact resistance is also ohmic as shown in
Fig. 4(a). When the contact resistance is increased, the
ID –VD curves change from normal to abnormal curves in
the pMOS, but there is little change in the nMOS [Fig.
4(b)].
We also varied the transistor width [Fig. 5]. While the
ID –VD curves did not change with the transistor width in
the S/D = N/N contact structure, the ID –VD curves in
the S/D = 1/1 contact structure changed from abnormal
behavior to normal behavior when the transistor width
was decreased. The variation of ID –VD curves with the
transistor width variation implies there is a limitation
on the current per unit contact. We additionally measured the ID –VD curves for various contact-to-wordline
spacings, but we could not observe any change in the
transistor characteristics.
To extract the experimental variable that signals the
abnormal the ID –VD curves, we combined the saturation
current, the contact resistance, and the number of drain
contact. We found that IDSAT RD /ND is parameter
for determing where the ID –VD curves show abnormal
behavior. Abnormal ID –VD curves are seen when the
value of IDSAT RD /ND is about 1000 mV in the nMOS
and 500 mV in the pMOS [Fig. 6].
This empirical variable tells us that the abnormal ID –
VD curves occur when the number of drain contacts is
too small or the contact resistance is too high, as well as
when the contact is non-ohmic. The above case can occur
in the core region of a DRAM cell. Although we have
tried a DAVINCI simulation for various contact structures, we failed to obtain abnormal transistor behavior.
IV. CONCLUSION
Abnormal ID –VD curves are observed when the contact structure is varied, even though the contact resistance is ohmic. The saturation current, the contact resistance, and the number of drain contacts have a major
effect on the abnormal behavior. We derive the variable
IDSAT RD /ND , above which abnormal ID –VD curves are
observed.
Abnormal ID –VD Curves Due to Contact Structures in ULSI Devices – Yong Hae Kim et al.
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