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COLORADO STATE UNIVERSITY
ECE 332: ELECTRONIC PRINCIPLES II
HOMEWORK 2
1. Consider the classical biasing scheme shown in the figure below, using a 9-V supply. For the
MOSFET, 𝑉𝑡 = 1𝑉, 𝜆 = 0, and 𝑘 ′ 𝑛 = 2 𝑚𝐴/𝑉 2. W/L = 1. Arrange that the drain current is
1 𝑚𝐴, with about one-third of the supply voltage across each of 𝑅𝑠 and 𝑅𝑑 . Use 22𝑀Ω for the
larger one between 𝑅𝐺1 and 𝑅𝐺2 . What are the values of 𝑅𝑠 , 𝑅𝑑 , 𝑅𝐺1 , and 𝑅𝐺2 that you have
chosen? Specify them to two significant digits. For your design, how far is the drain voltage
from the edge of saturation?
2. Using the circuit topology shown in the figure below, arrange to bias the NMOS transistor at
𝐼𝐷 = 1 𝑚𝐴 with 𝑉𝐷 midway between cutoff and the beginning of triode operation. (Hint: When
the transistor is in cutoff region, the current flowing through the transistor should be zero.
When the transistor enters the triode region from the saturation region, the beginning point is
when Vgd=Vt.) The available supplies are ±5V. For the NMOS transistor, 𝑉𝑡 = 1𝑉, 𝜆 = 0, and
𝑘 ′ 𝑛 = 2 𝑚𝐴/𝑉 2 . W/L = 1. Use a gate-bias resistor of 10𝑀Ω. Specify 𝑅𝑆 and 𝑅𝐷 to two
significant digits.
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3. Using the feedback bias arrangement shown in the figure below with a 5-V supply with an
NMOS device for which 𝑉𝑡 = 1𝑉, and 𝑘 ′ 𝑛 = 0.6 𝑚𝐴/𝑉 2 , W/L = 1. find 𝑅𝐷 to establish a drain
current of 0.2 mA. If resistor values are limited to those on the 5% resistor scale, what value
would you choose? What values of current and 𝑉𝐷 result?
4. A variation feedback bias circuit from previous problem shown in the figure below using a 5-V
supply with an NMOS device for which 𝑉𝑡 = 1𝑉, 𝑘 ′ 𝑛 = 6.25 𝑚𝐴/𝑉 2, W/L = 1, and 𝜆 = 0,
provide a design that biases the transistor at 𝐼𝐷 = 2 𝑚𝐴, with 𝑉𝐷𝑆 large enough to allow
saturation operation for a 2-V negative signal swing at the drain. Use 22𝑀Ω as the largest
resistor in the feedback-bias network. What values of 𝑅𝐷 , 𝑅𝐺1 , and 𝑅𝐺2 have you chosen?
Specify all resistors to two significant digits.
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