Download A Comparative Study of 6T, 8T and 9T SRAM Cell

International Journal of Advanced Engineering Research and Technology (IJAERT) 206
Volume 3 Issue 6, June 2015, ISSN No.: 2348 – 8190
A Comparative Study of 6T, 8T and 9T SRAM Cell
Kirti Bushan Bawa*, Dr. Sukhwinder Singh**
*( ME VLSI Department, PEC , Chandigarh
** (Supervisor/Assistant Professor ECE Department, PEC, Chandigarh
ABSTRACT
From the last few decades, the scaling down of CMOS
devices have been taking place to achieve better
performance in terms of speed, power dissipation, size
and reliability. The major area of concern in today‟s
CMOS technology is Data retention and leakage current
reduction. SRAM (Static Random Access Memory) is
memory used to store data. Conventional Static Random
Access Memory (SRAM) cells suffer from an intrinsic
data instability problem due to directly-accessed data
storage nodes during a read operation. Noise margins of
memory cells further shrink with increasing variability
and decreasing power supply voltage in scaled CMOS
technologies. The comparison of different SRAM cell on
the basis of different performance metrics like Read
delay, Write delay, Power dissipation, noise margin, area
is done in this review paper.
Keywords – SRAM, SNM,6T, 8T, 9T,delay,DRV
I.
INTRODUCTION
Technology and supply voltage scaling continues to
improve the logic circuit delay with each technology
generation. However, the speed of the overall circuit is
increasingly limited by the signal delay over long
interconnects and heavily loaded bit-lines due to
increased capacitance and resistance [1]. Static randomaccess memory (SRAM) is a type of semiconductor
memory that uses bi-stable latching circuitry to store
each bit. SRAM exhibits data remanence, but it is still
volatile in the conventional sense that data is eventually
lost when the memory is not powered. The stability and
area of SRAM need to be concern in designing SRAM
cell. SRAM cell must be able to write and read data and
keep it as long as the power is applied. The main
challenge in designing SRAM cell is to ensure that the
circuitry holding the state is weak enough to be
overpowered during a write, and still strong enough to
be not disturbed during read operation. For nearly 40
years CMOS devices have been scaled down in order to
achieve higher speed, performance and lower power
consumption. Due to their higher speed SRAM based
Cache memories and System-on-chips are commonly
used. In order to obtain higher noise margin along with
better performance new SRAM cells have been
introduced. In most of these cell read and write operation
are isolated to obtain higher noise margin. SRAM
represents a large portion of the chip, and it is expected
to increase in the future in both portable devices and
high-performance processors. To achieve longer battery
life and higher reliability for portable application, lowpower SRAM array is a necessity [2].
II.
SRAM CELL CIRCUIT DESCRIPTION
Static Random Access Memory (SRAM) is a type of
semiconductor volatile memory (RAM) which keeps its
data until the power is turns OFF. SRAM will store the
binary logic bits „1‟ or „0‟ [3]. It consists of an array of
memory cells along with the row and column circuitry.
SRAM has design to fill needs that are to provide direct
interface with CPU at speeds not achievable by DRAMs
and to replace DRAMs in systems that require very low
power consumption. The basic architecture of a static
RAM includes one or more rectangular arrays of
memory cells with support circuitry to decode addresses,
and implement the required read and write operations.
SRAM memory arrays are arranged in rows and columns
of memory cells called word-lines and bit-lines,
respectively. In SRAMs, the word-lines are made from
polysilicon while the bit-lines are metal. Each memory
cell has a unique location or address defined by the
intersection of a row and column. Each address is linked
to a particular data input/output pin. The number of
arrays on a memory chip is determined by the total size
of the memory, the speed at which the memory must
operate, layout and testing requirements and the number
of data I/Os on the chip. In designing a robust SRAM the
challenge is to ensure a reasonable noise margin, which
is normally measured by the Static Noise Margin (SNM)
and the Write Trip Point (WTP) [4], [5]. According to
[4], these two design factors they are linearly dependent
on the supply voltage, reducing which to save power has
a negative impact on the cell stability. As a result, it is
extremely difficult to maintain the cell stability.
Unfortunately, these two factors conflict with each other
and hence improving one is likely to jeopardize the
other. An SRAM cell has three different states it can be
in: standby where the circuit is idle, reading when the
www.ijaert.org
International Journal of Advanced Engineering Research and Technology (IJAERT) 207
Volume 3 Issue 6, June 2015, ISSN No.: 2348 – 8190
data has been re-quested and writing when updating the
contents. The SRAM to operate in read mode and write
mode should have “read-ability” and “write stability”
respectively.
memory cell area overhead as compared to the 9T
SRAM circuit.
Figure 2: 8T SRAM cell
1. 6T SRAM cell
In the conventional 6T SRAM cell the condition of a non
destructive read operation and a reliable write operation
is fulfilled by appropriately sizing all the transistors in
the SRAM cell. Sizing is done according to the cell ratio
(CR) [6] and pull up ratio (PR) [6] of the transistor.
Table 1: Width of transistor used in 6T SRAM cell
Transistor
Width(mm)
M1,M2,M3,M4
120
M5,M6
600
Table 2: Width of transistor used in 8T SRAM cell
Transistor
Width(mm)
M1,M2,M3,M4
120
M5
600
480
M7,M8
M6
240
Figure 1: 6T SRAM cell
Access to the cell is enabled by the word line (WL in
figure) which controls the two access transistors M5 and
M6 which, in turn, control whether the cell should be
connected to the bit lines: BL and BL bar [7]. They are
used to transfer data for both read and write operations.
Although it is not strictly necessary to have two bit lines,
both the signal and its inverse are typically provided in
order to improve noise margins.
2. 8T SRAM cell
In 8T SRAM cell read noise margin of the sram cell has
been enhanced by isolating the read and write operation.
The 8T SRAM cell consists of 8 transistors. Utilizing
single-ended data access for read operations with an
alternative 8T SRAM circuit structure [8] reduces the
The left sub-circuit of the 8T memory cell is a
conventional 6T SRAM cell. The write operation is
identical with the conventional 6T SRAM cell. An
alternative communication channel that is composed of a
read bitline and a transistor stack formed by M6,M7and
M8 is used for reading the stored data from the cell.
3. 9T SRAM cell
Read noise margin of the 9T SRAM cell has been
enhanced by isolating the read and write operation Due
to the higher number of transistor used in 9T SRAM cell
its leakage energy consumption increases. To reduce the
leakage current in 9T SRAM dual threshold voltage
technology [9] has been used. High threshold voltage
transistors are not used for the access transistor as it
increases the write delay. The upper sub-circuit of the 9T
memory cell is essentially a conventional 6T SRAM
cell. The write operation is identical with the
conventional 6T SRAM cell. The lower sub-circuit of
the 9T memory cell is a differential read port. Prior to a
read operation, both bitlines are precharged to VDD. To
start a read operation, the read signal transitions from 0
www.ijaert.org
International Journal of Advanced Engineering Research and Technology (IJAERT) 208
Volume 3 Issue 6, June 2015, ISSN No.: 2348 – 8190
to 1. One of the bitlines is discharged depending on the
data that is stored in the cell.
Read delay is highest for 9T SRAM cell because high-Vt
transistors are used in it, due to which the driving
capability of the transistor reduces. Due to the single bit
line in 8T SRAM cell its write delay is higher as
compared to other SRAM cell.
3. SNM
SNM measures how stable a cell is. It is defined as the
worst case noise level available at the gates of the
inverters that does not cause the cell to flip. Therefore,
SNM is normally associated with the Read operation and
it is desirable to have as high SNM as possible .Read
data stability is therefore enhanced in the 7T, 8T, and 9T
SRAM cells as compared to the conventional 6T SRAM.
4. Active power consumption
The tri-Vt7T memory array [11] consumes the lowest
write power. The single write bitline of a 7T SRAM cell
is maintained at VDDor VGND following a write
operation. The write bitline is not necessarily charged or
discharged prior to each write operation if the incoming
data is identical with the initial state of the write bitline.
Alternatively, one of the two bitlines is discharged prior
to a write operation regardless of the incoming data in an
8T or 9T SRAM cell. The tri-Vt 8T SRAM array
consumes the lowest read power. Alternatively, the tri-Vt
7T SRAM array suffers from the highest read power
consumption due to the highest read bitline capacitance
and bitline voltage drop.
Figure 3: 9T SRAM cell
Table 3: Width of transistor used in 9T SRAM cell
Transistor
Width(mm)
M1,M2,M3,M4
120
M5,M6
600
M7,M8
240
M9
480
III.
COMPARISION
1. The area and parasitic capacitance[10]
Table 4:Area and parasitic capacitance of SRAM cells
SRAM
Area (mm²)
Paracitic
Cells
capacitance(pF)
6T
12.35
2.71
8T
11.40
2.73
9T
15.46
3.50
The area and parasitic capacitance for different SRAM
cell is given above. The write power is high in 9T is
because of high parasitic capacitance.
2. Delay and data retention voltage
Simulation results for data retention read delay and write
delay is shown in Table below.[10]
Table 5: Delay and DRV of SRAM cells
SRAM
DRV(mV)
Read
Write
cell
delay(ps)
delay(ps)
6T
252.2
72.82
8.976
8T
93.64
77.72
45.47
9T
84.5
98.85
10
Figure 4: Read and write power consumption of SRAM
cells [11]
Table 6: Comparison of SRAM cells on the basis of
power consumption, delay, SNM and PDP[12]
Parameters
6T
8T
9T
Power
consumption
delay
SNM
PDP
2.0e-6
2.12e-6
501e-3
10.83e-1
596.88
21.66e-1
10.08e-9
550.04
21.97e-1
1.16e-12
541.8
581.16e-1
www.ijaert.org
International Journal of Advanced Engineering Research and Technology (IJAERT) 209
Volume 3 Issue 6, June 2015, ISSN No.: 2348 – 8190
Table above shows the comparison of 6T, 8T and 9T
SRAM cells. The comparison is done on the basis of
power consumption, delay, SNM and PDP.
IV.
CONCLUSION
In this paper we have analyzed the performance of some
topologies of SRAM cells for parameters like cell power
consumption, delay, SNM, data retention voltage and
area. From results it looks like that 6T SRAM is the
better one out of three. The results can be used to select
SRAM cell topology to design and fabricate memory
chips which is best suitable for different type of
application. For power constrained projects like space
exploration and satellites the SRAM cell which
consumes minimum power should be used while for
very fast processing devices the SRAM cell which has
minimum time delay should be used. The SRAM cell
which has maximum SNM can be used in the device
which works in noisy environment. The design of
SRAM cell can be optimized by tradeoff between
various performance parameters.
node and beyond,” Proceedings of the IEEE Symposium
on VLSI Technology, pp. 128-129, June 2005.
[9] J. T. Kao and A. Chandrakasan, “Dual-Threshold
Voltage Techniques for Low-Power Digital Circuits,”
IEEE J. Solid State Circuits, Vol. 35, no. 7, July 2000,
pp.1009-1018
[10] Paridhi Athe,S. Dasgupta,"A Comparative Study of
6T, 8T and 9T Decanano SRAM cell", 2009 IEEE
Symposium on Industrial Electronics and Applications
(ISIEA 2009), October 4-6, 2009, Kuala Lumpur,
Malaysia.
[11] Hong Zhu et al.,"A Comprehensive Comparison of
Superior Triple-Threshold-Voltage 7-Transistor, 8Transistor, and 9-Transistor SRAM Cells",978-1-47993432-4/14/$31.00 ©2014 IEEE.
[12] Dadoria et al.,"Comparative Analysis Of Variable
N-T Sram Cells", International Journal of Advanced
Research in Computer Science and Software
Engineering 3(4),April - 2013, pp. 612-619.
REFERENCES
[1] N. Dist, “Analysis of New Current Mode Sense
Amplifier,” pp. 1–6
[2] A.V Gayatri, “Efficient Current Mode Sense
Amplifier for Low Power SRAM,” vol. 1, no. 2, pp.147–
153, 2011.
[3] J. Zhu, N. Bai, and J. Wu, “A Review of Sense
Amplifiers for Static Random Access Memory,” vol. 30,
no. 1, 2013.
[4] E. Grossar et al., “Read stability and write-ability
analysis of SRAM cells for nanometer technologies,”
IEEE J. Solid-State Circuits, vol. 41, no.11, pp. 2577–
2588, Nov. 2006.
[5] V. Gupta and M. Anis, “Statistical design of the 6T
SRAM bit cell,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 57, no. 1, pp. 93–104, Mar. 2010.
[6] A. Pavlov and M. Sachdev, “CMOS SRAM circuit
design and parametric test in Nano scaled technologies”,
Springer Netherlands, 2008
[7] Shigeki Ohbayashi, Makoto Yabuuchi, Koji Niiand,
Susumu Imaoka “A 65-nm SoC Embedded 6T-SRAM
Designed for Manufacturability With Read and Write
Operation Stabilizing Circuits” IEEE journal of solidstate circuits, Vol. 42,April 2007, pp820 -829
[8] L. Chang, D. M. Fried, J. Hergenrother, J. W.
Sleight, R. H. Dennard, R. K. Montoye, L. Sekaric, S. J.
McNab, A. W. Topol, C. D. Adams, K. W. Guarini, and
W. Haensch, “Stable SRAM cell design for the 32nm
www.ijaert.org