Download Variation Tolerant Differential 8T SRAM Cell for Ultralow Power

Variation Tolerant Differential 8T SRAM Cell for Ultralow Power Applications
Abstract:
Low power and noise tolerant static random access memory (SRAM) cells are in
high demand today. This paper presents a stable differential SRAM cell that
consumes low power. The proposed cell has similar structure to conventional 6T
SRAM cell with the addition of two buffer transistors, one tail transistor and one
complementary word line. Due to stacking effect, the proposed cell achieves
lower power dissipation. In this paper, impact of process parameters variations on
various design metrics of the proposed cell are presented and compared with
conventional differential 6T (D6T), transmission gate-based 8T (TG8T), and single
ended 8T (SE8T) SRAM cells. Impact of process variation, like threshold voltage
and length, on different design metrics of an SRAM cell like, read static noise
margin (RSNM), read access time (TRA), and write access time (TWA) are also
presented. The proposed cell achieves 1.12×/1.43×/5.62× improvement in
TRA compared to TG8T/D6T/SE8T at a penalty of 1.1×/4.88× in TWA compared to
D6T/TG8T and 1.19×/1.18× in read/write power consumption compared to D6T.
An improvement of 1.12×/2.15× in RSNM is observed compared to D6T/TG8T. The
proposed cell consumes 5.38× less power during hold mode and also shows 2.33x
narrower spread in hold power @ VDD = 0.4 V compared to D6T SRAM cell.