Download noise coupling, substrate noise - Department of Electrical and

Overview
System-on-Chip
• “Switching” noise generation
• Noise injection and reception
Noise coupling in SoC/SiP
• Substrate coupling in CMOS
• Noise propagation
• Biasing strategies
Pietro Andreani
Dept. of Electrical and Information Technology
Lund University, Sweden
P. Andreani – System-on-Chip
Types of noise coupling
2
Reducing crosstalk through metal wires
In nm CMOS technologies Æ wire spacing is small Æ large
crosstalk Æ must be reduced:
Thickness
Spacing
• Crosstalk
Crosstalk
• dV/dt, dI/dt
• Power line noise coupling (dI/dt)
Vdd
• No parallel lines (difficult to realize)
• Large space between lines (area penalty)
dI/dt
Vss
Vdrop
Cir.1
• Reduce Cm/C and Lm/L with a ground plane close to lines
(speed and power penalties)
Cir.2
• Place ground lines between active lines (area penalty, as well
as speed)
• Substrate noise coupling (dV/dt)
• CAD tools to estimate the crosstalk and to limit the crosstalk
within an acceptable level
Substrate
• Radiation noise coupling
• Special coding to cancel the crosstalk from two or more active
“digital” lines, e.g. differential in the case of 2 active lines
λ1GHz
=1.25cm
2
P. Andreani – System-on-Chip
Noise coupling
Noise coupling
• Innovative CMOS process steps are needed in general!
3
P. Andreani – System-on-Chip
Noise coupling
4
General power supply distribution model
Noise due to wire resistance
Average/peak voltage drops in wires with full current densities
Wire type
Board
Sheet resistance
Current density
100 μm long
1000 μm long
10 mm long
Chip
• Internal power/ground distribution can be seen as resistive except bond
wires
0.08 Ω
1 mA/μm
7mV/70mV
70mV/0.7V
0.7V/7V
0.04 Ω
1 mA/μm
4mV/40mV
40mV/0.4V
0.4V/4V
Peak voltage drop (noise) is a fundamental source of noise in SoC
• At the board level, large decoupling components can be used – more
difficult to do so at the chip level
Noise coupling
Metal-top
Note: In synchronous circuits, Ipeak ≈ 10 × Iaverage
• Noise may be transmitted from one chip to another chip Æ the small
sensitive analog signals may easily become corrupted
P. Andreani – System-on-Chip
Metal-1
Inductance is even more critical than resistance
5
P. Andreani – System-on-Chip
Noise coupling
6
Chip interface
dI/dt noise via power supply
Inductance of power lines and bonding wires Æ often crucial
L
I
V
V=L
dΙ
dt
(a) Wire bonding.
(b) Flip-chip bonding.
P. Andreani – System-on-Chip
Noise coupling
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P. Andreani – System-on-Chip
Noise coupling
8
Pad circuit (with bond wire)
dI/dt noise in CMOS
Vdd
Pin
Bond wire
inductance
Pad
Lb≈1-5nH
50x50 μm2
large
protective
diodes
• Simultaneous switching noise (SSN), also called ground
bounce
• Output buffers drive large loads Æ especially important Æ
multiple pins may be needed
I/O
• Millions of gates switching simultaneously Æ very large current
spikes
Cpin > 1pF Cpad≈0.25pF
Out/In
Cn+Cn > 1pF
L>1nH
In/Out
C1>1pF
P. Andreani – System-on-Chip
• Logic families with almost constant power consumption have
been proposed, similar to BJT ECL logic (i.e. enhanced sourcecoupled logic, folded source-coupled logic) Æ large quiescent
power consumption Æ not popular
• On-chip or on-package decoupling capacitors are always
needed
C2>1pF
Noise coupling
9
Design criteria for reducing dI/dt noise
Inductive
time constant
L
R
1.
2.
L
10
Decoupling capacitor CD reduces fluctuation
I
L1
L1
R1
<< RC
dI
<< VDD
dt
Noise coupling
ΔV
Capacitive
time constant
VDD
P. Andreani – System-on-Chip
+
-
VDD
R2
L= L1+L2
L2
+
-
CD
C
L2
C1
C2
Assuming all current is supplied by CD (worst case)
CDVDD = (VDD + ΔV)(CD +C)
• Simultaneously switching Æ large dI/dt
• High speed Æ RC must be small Æ harder to meet L <<
ΔV =
R2C
C
CD + C
VDD
• Large designs Æ small R Æ harder to meet L << R2C
• If a max. 10% voltage drop is allowed Æ CD > 10C required
• During switching, power fluctuation must be kept to a small part of
VDD, not only for analog but also for digital circuits.
• If total chip capacitance of a microprocessor is 1nF Æ CD should
be larger than 10nF (!)
• In reality, the unswitched fraction of C acts as a decoupling
capacitance
P. Andreani – System-on-Chip
Noise coupling
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P. Andreani – System-on-Chip
Noise coupling
12
Technological differences of P-/P+ substrates
Substrate noise coupling in CMOS
Voltage
transient
Epitaxial layer:
4-15 μm
1-50 Ωcm
Digital GND
Wires & pads
Cj
Biasing
contact
p1-50 Ωcm
p-
Wafer thickness
50-500 μm
Low-conductive
lightly-doped wafer
1
Analog GND
Cj
3
Biasing
contact
VBS Æ VT Æ IDS
p-
1-50
mΩcm
p+
2
Sensitive
Node
1. Noise injection through reverse-biased junction capacitance
High-conductive
heavily-doped wafer
with an epitaxial layer
2. Noise injection through contacts
3. Noise injection through wire-to-substrate capacitance
Also others: through forward-biased junction and hot carriers
P. Andreani – System-on-Chip
Noise coupling
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Noise injection via substrate contacts
Digital GND
200-500 mV
Biasing
contact
P. Andreani – System-on-Chip
Noise coupling
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Noise injection via parasitic capacitance
Digital POWER
200-500mV
n-well
Biasing
contact
Power/Ground wires
Pads
p-
RF inductor
• Due to simultaneous switching, noise amplitudes on power and ground
wires may reach 500mV
• Lowest level of wire parasitic capacitance to substrate is another
source of noise injection
• This noise directly affects the substrate through bias contacts
• Pads, power/ground wires and RF inductors are particularly
significant in producing substrate noise through their large parasitic
capacitance
• Contacts are spread all over the substrate Æ large impact, even more
significant than that of junction capacitances
P. Andreani – System-on-Chip
Noise coupling
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P. Andreani – System-on-Chip
Noise coupling
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Noise injection via forward biased junction
Why an 8-form coil??
n-well
Noise on digital
ground wire
Reverse-bias
Digital ground wire
Protective
diodes
Forward-bias
Source
diodes
Substrate
Substrate
Negative pulses may
be directly injected
into substrate
• The pad protective diodes and the nMOS source diodes can be
forward-biased by the negative noise pulses on the digital ground
wires Æ inject large noise into the substrate
• This noise is similar to that through substrate contacts
N. Itoh et al., “5.8 GHz RF Transceiver LSI Including On-Chip Matching Circuits”,
2006 IEEE BCTM, paper 14.1
P. Andreani – System-on-Chip
Noise coupling
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P. Andreani – System-on-Chip
Noise reception via Cj, Cd, and contacts
Sensitive node
Cj
Cd
18
Noise reception via body effect
Noise at drain (V)
Analog GND
Sensitive node
0.020
0.018
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
Biasing
contact
VBS
Bulk
(substrate)
4E16
6E16
8E16 1E17
Substrate doping (cm-3)
• The substrate noise can be received by the sensitive node through
Cj and Cd, where Cd is the capacitance between the channel and
substrate (which are separated by the depletion layer)
VT = Vto+γ( 2φb-VBS -
• The noise can also be received by the analog ground through the
substrate contact. For an analog circuit with a low PSRR, this
would be a major noise source
Noise coupling
Analog GND
Source
VDS = 2.5V
VBS = 10mV
2E16
P. Andreani – System-on-Chip
Noise coupling
2φb )
VBS Æ VT Æ IDS (Æ VDS )
19
P. Andreani – System-on-Chip
γ =
2qεsiNA
Cox
KT
φb = q
Noise coupling
N
ln n A
i
20
Effect of a guard ring (P-)
Replacing guard ring with contacts (P-)
No backplane contact
(less important in P-)
Without a guard-ring
5 contacts (each 10 μm)
continuous trench (100μm)
Constant voltage contour lines simulated with the RAPHAEL
With a guard-ring
3 contacts (each 10 μm)
P. Andreani – System-on-Chip
Noise coupling
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Noise reduction techniques (ideal supply lines)
Noisy NMOS
10μm
Noise coupling
22
Noise reduction techniques – II
NMOS
2μm
P. Andreani – System-on-Chip
2 contacts (each 10 μm)
SiO2
0V
0V
N+
P+
2μm
500μm
P
P-
-
1) No measure
P-
2) An oxide trench
+5V
+5V
N+
N+
N-well
P-
5) An N-ring to ground
6) A P-ring to ground
0V
0μm
4μm
N+
P-
3) An N-ring to Vdd
P. Andreani – System-on-Chip
P-
P-
4) An N-ring inside an N-well
Noise coupling
8μm
7) A buried layer to ground
23
P. Andreani – System-on-Chip
Noise coupling
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Comparison between the different techniques
Noise reduction in SOI technology
No measure (1)
Analog part
Oxide trench (2)
Digital part
SiO2
N-ring to Vdd (3)
P substrate
N-ring inside N-well (4)
N-ring to ground (5)
• Silicon on Insulator (SOI) technology isolates analog and digital
parts into separate substrate islands Æ better for noise reduction.
P-ring to ground (6)
• At high frequency, however, the two islands are still coupled
through the capacitance to the p-substrate Æ limited noise
reduction, high cost Æ SOI not very attractive in general
Buried layer (7)
0
25
50
75
100
125
150
175
Peak-to-peak noise level (mV)
However, these results may be process dependent!
P. Andreani – System-on-Chip
Noise coupling
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P. Andreani – System-on-Chip
Conclusions
Noise attenuation increases with
distance
Backside contacts
Almost useless
Type of guard-ring
P+ in P- and N+ in N- substrate
Contacts instead of ring
Yes, easy for wire crossing
Length of guard ring
Less important
Position of guard ring
Across the path, close to source
Width of guard ring
Less important
Low impedance to ground
Important
• What is better for biasing the substrate, digital ground or analog
ground?
• Is it better to use an exclusively dedicated substrate biasing line?
What will be the consequences?
• Is a guard ring really effective? Where should the guard ring be
connected?
• For a given biasing strategy, is it better to use many or just a few
contacts?
• Will the pad ring affect the biasing strategy?
In general, the effectiveness of decoupling depends on the impedance of the return path
Æ guard ring contacts should have a very low impedance
Backplane contact not important in P-
P. Andreani – System-on-Chip
Noise coupling
26
Fundamental questions
P- substrate
Noise vs. distance with an
ideally grounded backplane
Noise coupling
27
P. Andreani – System-on-Chip
Noise coupling
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Preliminary floor plan of the test circuit
Test circuit arrangement
Analog signals
Power/
ground
• Technology: 2M N-well 1.2μm CMOS (old!!)
Power/
ground
• Digital part: 256 noisy inverters in 16 groups, 16 inverters each
group, driven by a combinational tree
• Analog part: a simple sense amplifier with short-circuited input
and output at a DC voltage of Vdd/2, i.e. 2.5 V in this case,
loaded by another identical sense amplifier
• Power supply: independent lines for the analog part, the digital
part, and the digital pads
Digital
signals
• Pads: 30 digital and 10 analog pads
Digital
signals
• Parasitic capacitance: extracted from the layout
• Substrate resistance: extracted by device simulator MEDICI
Power/ground rings
Digital
signals
P. Andreani – System-on-Chip
Noise coupling
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P. Andreani – System-on-Chip
Illustration of the test circuit
(VEP-A)
.
(VAP)
(VDP)
256
inverters in
16 groups
(3) Terminology for lines:
A:
the line feeds analog section
D:
the line feeds digital section
E:
the line used for biasing without
feeding current to any transistor
50/1.2
(4) Terminology for biasing:
30/1.2
(VDG)
(VAG)
(VEG-D)
Figures for
a large chip
Mutual inductance
between different
pins is disregarded!
(VEG-A)
(2) Clock frequency: 20 MHz
All biasing strategies will be evaluated
P. Andreani – System-on-Chip
30
Other conditions and terminology
(1) Equivalent circuit of a package pin:
(VEP-D)
Noise coupling
Noise coupling
31
P. Andreani – System-on-Chip
X/Y: a biasing combination
X indicates the line to which
digital contacts are connected
Y indicates the line to which
analog contacts are connected
X/G/Y: G is the line to which the guard
ring contacts are connected
Noise coupling
32
Biasing strategies (1)
D/D
VDP
VDG
Biasing strategies (2)
D/A
D
A
D
A
VAP
VDP
VAG
VDG
E/A
D
A
D
A
D/E
VEP
VDP
VAP
VDG
VAG
E/E
D
A
D
A
VEG
VAP
VAG
A/A
D
VDP
VAP
A
D
VDG
VEG
D
A
D
A
VAP
VAG
No SSN
VEP
VDP
VEP
VDP
A
VAP
VDP
D
A
VAP
SSN – Simultaneous
Switching Noise
D
VDG
A
VAG
D
VDG
A
VAG
VDG
VEG
P. Andreani – System-on-Chip
Noise coupling
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P. Andreani – System-on-Chip
Noise level in P- substrate
D
A
VAG
Noise coupling
34
A/A - the worst biasing strategy
D/D
D/A
D/E
A/A
VDP
VAP
VDG
VAG
66.5mV
E/A
E/E
No SSN
Normalized noise level
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
• A/A is the worst strategy, while D/E or E/A are the best
• D/A and E/A minimize body effects, but noise propagates through substrate, then
couples to supplies through contacts/capacitances
• Notice however that D/A is even (slightly) better than E/E Æ great, no need of
dedicated lines
Noise goes first to nearby contacts and then
directly through wires to the analog section
• With ideal pins (no SSN), noise only through substrate Æ insignificant compared
to that through power/ground contacts
P. Andreani – System-on-Chip
Noise coupling
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P. Andreani – System-on-Chip
Noise coupling
36
D/D - the second worst biasing strategy
D/A - a good biasing strategy without E-line
VDP
VAP
VDP
VAP
VDG
VAG
VDG
VAG
The only path for noise going to analog section is the P- substrate,
which will attenuate the noise due to its large resistance. D/A is
better than D/D or even E/E
Noise can directly go to the contacts of analog
section and reach the source node in close distance
P. Andreani – System-on-Chip
Noise coupling
37
P. Andreani – System-on-Chip
D/E - one of the best biasing strategies
VEP
VDP
VAP
VDG
VAG
VDG
VEG
VEG
Noise coupling
VAP
VAG
Compared to D/A, noise is decoupled from
the digital power supply lines
Compared with D/A, supply noise is decoupled
with analog power supply lines
P. Andreani – System-on-Chip
38
E/A - one of the best biasing strategies
VEP
VDP
Noise coupling
39
P. Andreani – System-on-Chip
Noise coupling
40
E/E - worse than D/E or E/A
E1/E2 - the best biasing?
VEP
VEP1
VDP
VDP
VAP
VDG
VEP2
VAG
VAP
VDG
VEG
VAG
VEG2
VEG1
The noise coupled to nearby digital contacts directly
goes to analog section via wires and makes things worse
P. Andreani – System-on-Chip
Noise coupling
It should be the best biasing at the cost of two dedicated supplies.
There are no internal wires between digital and analog sections.
41
P. Andreani – System-on-Chip
No SSN - attractive but practically unfeasible
Noise coupling
42
What if fewer contacts?
VDP
VDP
VAP
VAP
VD
VAG
G
10×
Unchanged
10×
10×
VAG
VDG
p-
Fewer contacts Æ contact-related resistance increases Æ less noise
drained Æ coupling between devices increases, but noise on supply
lines decreases
Without inductance, the substrate is ideally biased, only device noise
remains. The two power supplies may be merged. However, it is
unfeasible practically.
P. Andreani – System-on-Chip
Noise coupling
10×
10×
43
P. Andreani – System-on-Chip
Noise coupling
44
The fewer the contacts, the higher the noise (P-)
D/D
D/A
D/A
D/A/A
D/E/A
Reference circuit
1/10 contact number
10%
8%
D/E
A/A
The effect of guard ring biasing (p-)
D/E
D/E/E
E/A
E/A/A
E/E/A
E/E
E/E/E
21%
40%
E/A
E/E
37%
35%
No SSN
122%
0
No SSN
10
20
30
40
50
60
70
80
Root-mean-square voltage over a 10ns period (mV)
90
Normalized noise level
100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
• Little change, since the large parasitic capacitances on the supply lines are
the dominating mechanism
• The “no SSN” case has the largest relative increase – this is
because device coupling is maximized in this case
• D/A/A and E/A/A bias the rings with analog supply, and the reason for the
limited effect is that the original analog ground is already a guard ring
• The other results are less straightforward to interpret
• E/E/A biases the ring with the same line biasing the digital section, it
introduces noise (D/D/A or D/D/E are similar to D/D (i.e., bad))
P. Andreani – System-on-Chip
Noise coupling
45
P. Andreani – System-on-Chip
The effect of pin inductance (p-)
D/A
• Minimize impedance on supply lines
D/E
• Separate supply domains for analog/digital – use D/A
or D/E for biasing (E/A ok, but may cause latch up)
66.5mV
A/A
E/A
• Distance between analog and digital helps always
E/E
• Guard rings help, too Æ best if biased with dedicated
lines
No SSN
Normalized noise level
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
46
Conclusions (P- substrate)
10 nH
1 nH
D/D
Noise coupling
0.9
1.0
• And, implement all analog functions as differential
circuits whenever possible
• With small terminal inductance (almost no SSN), there is little difference
between different biasing strategies
• For a chip with large terminal inductance, the selection of biasing strategy
becomes important
• Inductance “large” or “small” Æ depends on the noise level we can tolerate
P. Andreani – System-on-Chip
Noise coupling
47
P. Andreani – System-on-Chip
Noise coupling
48
Buried layers with deep contacts
Buried layers without deep contacts
(1) Only under the noisy section with deep contacts:
digital
GND
noisy
NMOS
noisy
PMOS
digital
Vdd
analog
GND
sensitive
NMOS
N-well 10 Ω⋅cm
P-BL 50 mΩ⋅cm
(4) Only under the noisy section without deep contacts:
sensitive
PMOS
analog
Vdd
digital
GND
N-well 10 Ω⋅cm
noisy
NMOS
noisy
PMOS
digital
Vdd
P-BL 50 mΩ⋅cm
analog
GND
sensitive
NMOS
N-well 10 Ω⋅cm
sensitive
PMOS
analog
Vdd
digital
GND
noisy
PMOS
analog
GND
P. Andreani – System-on-Chip
analog
Vdd
N-well 10 Ω⋅cm
digital
Vdd
noisy
PMOS
analog
GND
sensitive
NMOS
N-well 10 Ω⋅cm
sensitive
PMOS
analog
Vdd
N-well 10 Ω⋅cm
P-BL 50 mΩ⋅cm
sensitive
NMOS
sensitive
PMOS
analog
Vdd
digital
GND
noisy
NMOS
N-well 10 Ω⋅cm
N-BL 25 mΩ⋅cm
sensitive
PMOS
N-BL 25 mΩ⋅cm
(6) Under all the circuitry without deep contacts:
N-well 10 Ω⋅cm
P-BL 50 mΩ⋅cm
sensitive
NMOS
N-BL 25 mΩ⋅cm
N-BL 25 mΩ⋅cm
(3) Under all the circuitry with deep contacts:
noisy
NMOS
noisy
NMOS
N-well 10 Ω⋅cm
digital
Vdd
analog
GND
(5) Only under the sensitive devices without deep contacts:
P-BL 50 mΩ⋅cm
digital
GND
digital
Vdd
noisy
PMOS
N-well 10 Ω⋅cm
N-BL 25 mΩ⋅cm
(2) Only under the sensitive devices with deep contacts:
digital
GND
noisy
NMOS
P-BL 50 mΩ⋅cm
analog
GND
sensitive
NMOS
N-well 10 Ω⋅cm
N-BL 25 mΩ⋅cm
Noise coupling
digital
Vdd
noisy
PMOS
P-BL 50 mΩ⋅cm
49
N-BL 25 mΩ⋅cm
P. Andreani – System-on-Chip
Three possible arrangements of buried layers
sensitive
PMOS
analog
Vdd
N-well 10 Ω⋅cm
P-BL 50 mΩ⋅cm
N-BL 25 mΩ⋅cm
Noise coupling
50
How to bias buried layers
(1) D/D, A/A and E/E are bad biasing strategies for buried layers
VP
VG
(1)
(4)
(2)
(5)
N-well 10 Ω⋅cm
P-BL 50 mΩ⋅cm
N-well 10 Ω⋅cm
P-BL 50 mΩ⋅cm
N-BL 25 mΩ⋅cm
(6)
(3)
• As expected, buried layers reduce substrate noise significantly
(2) D/A and E/A are good biasing strategies for buried layers
• The deep bias contacts are essential, particularly for buried layers
under the analog section – otherwise, basically same situation as P+
without backplane contacts (N/P buried layers are connected by a
relatively large junction capacitance)
VDG or VEG
Noise coupling
P-BL 50 mΩ⋅cm
51
P. Andreani – System-on-Chip
VAP
VDP or VEP VAG
N-well 10 Ω⋅cm
• The best arrangement is case (3), i.e. to place buried layers under all
the circuitry with deep contacts, although case (2) already gives
substantial noise reduction
P. Andreani – System-on-Chip
N-BL 25 mΩ⋅cm
N-BL 25 mΩ⋅cm
N-well 10 Ω⋅cm
P-BL 50 mΩ⋅cm
Noise coupling
N-BL 25 mΩ⋅cm
52
Design criterion for buried layers
Add buried layers in CMOS process needs at least 3 extra masks Æ (much) more
expensive – also, the density of digital cells would be lower
Digital P-well & P-BL
Allow only capacitive junctions between
buried layers under different sections
Never allow low-resistive paths between
analog and digital
Available buried layers in BiCMOS
Digital N-well & N-BL
Digital N-well
& N-BL
Digital P-well
& P-BL
Buried layers are available in high performance BiCMOS process (N-BL is always
needed to decrease the parasitic collector resistance in npn BJTs) – the only extra
mask is for the deep contact of P-BL
Analog P-well
& P-BL
Analog N-well
& N-BL
Analog N-well & N-BL
Analog P-well & P-BL
P-well
contact NMOS
or
P+
Digital P-well & P-BL
Digital N-well & N-BL
N+
N+
P-well
P-BL
N-well
PMOS contact
P+
P+ N+
N-well
N-BL
NPN bipolar transistor
Emitter Base
Collector
N+
Pwell
P-BL
P+
N-well
N+contact
N-BL
Digital N-well & N-BL
Used for insulation in high
performance BiCMOS, without biasing
Digital P-well & P-BL
P- substrate
Analog N-well & N-BL
Analog P-well & P-BL
P. Andreani – System-on-Chip
Noise coupling
53
Triple-well nMOS in CMOS processes
State-of-the-art CMOS processes provide triple-well nMOS devices for
improved isolation
Deep contacts usually not available
Isolation is very good at low frequencies – decreases after a few GHz
because of capacitive coupling
P-well
contact NMOS
P+
N+
N+
P-well
N-well
contact
N+
N-well
P- substrate
P. Andreani – System-on-Chip
Noise coupling
55
P. Andreani – System-on-Chip
Noise coupling
54