Download 1 - Suraj @ LUMS

Computer Organization & Assembly Language, Spring 2002-03
Quiz 4
CS 223/ CmpE 221
Name: Mr. Right___________________
23/04/2003
Time allowed: 30 min
Roll No: __Sol-__u__-_tion_
Question No. 1 (2+2+2+2+2+2):
1000h
1000h
3418h
1004h
R0
0000h
1004h
1008h
R1
100Bh
2000h
100Bh
R1
1004h
R3
3418h
R4
1424h
R5
1008h
R6
341Bh
2000h
3418h
R7
1000h
0001h
341Bh
16 bits
0070h
3420h
0071h
3424h
16 bits
Register
Memory
Consider the situation depicted in the figure above. What is the location of the
operand pointed to for the given addressing mode and instruction in parts a-f.
Note that all numbers are given in HEX (h) format.
341Bh
a.) Addressing Mode = Immediate, Instruction =
Location = Instruction operand field
Value = 341Bh
b.) Addressing Mode = Direct, Instruction =
341Bh
Location = 341Bh (in memory)
Value = 0001h
c.) Addressing Mode = Indirect, Instruction =
Location = 1004h (in memory)
1008h
Computer Organization & Assembly Language, Spring 2002-03
23/04/2003
Value = 3418h
2h
d.) Addressing Mode = Register, Instruction =
Location = R2 (register)
Value = 1004h
1h
e.) Addressing Mode = Register Indirect, Instruction =
Location = 100Bh (in memory)
Value = 2000h
f.) Addressing Mode = Displacement, Instruction =
4h
100Bh
Location = 1424h + 100Bh = 242Fh
Value = ????h
Question No. 2 (5):
Explain the operation of an interrupt cycle using PC, MAR and MBR registers
within the CPU.
1. MBR <- PC: Save contents of PC to MBR, to be stored somewhere for
retrieval after the ISR has been serviced
2. MAR <- Stack Pointer/ Some other register: Supplied by the control
unit.
3. PC <- Address(ISR): Load starting address of the ISR into the PC. The
ISR will begin executing in the next cycle.
Question No. 3 (5):
Avg. number of instructions between branch instructions = n = 9
Number of pipeline stages = k = 5
Speedupenhanced =
nxk
k + (n-1)
.
= (9 x 5)/(5 + 8) = 45/13 = 3.46
Computer Organization & Assembly Language, Spring 2002-03
23/04/2003
Question No. 4 (4+2+2):
(a) Why is dealing with conditional branches considered a hazard in
pipelining?
(b) Suggest two techniques of overcoming the branch hazards.
(a) In order to achieve maximum speedup from a pipeline, it is necessary that
there is a steady flow/ supply of instructions at the pipeline’s input. Branches,
especially conditional branches, usually have to pass through a number of
pipeline stages before it can be decided whether there is a jump or not.
Meanwhile, some of the instructions following the branch instruction are
already in some earlier stages of the pipeline and have to be discarded. This
reduces the actual speedup achieved.
(b) Any two of these 5 techniques will do

Multiple Streams

Prefetch branch target

Loop buffer

Branch prediction

Delayed branch
Multiple Streams: Fetch both instructions, next and branch target instruction,
process both in separate pipelines until condition is evaluated and it is
determined which stream to discard.
Prefetch Branch target: Fetch possible branch target instructions while branch
condition is being evaluated. If the branch is taken the target instruction will
already have been fetched.
Loop Buffer: Use a small, fast memory to store some of the most recent
branch targets. Useful in loops.
Branch Prediction: Use a branch prediction technique to “guess” the most
likely outcome of the branch condition evaluation and prefetch the next
instruction accordingly.
Delayed Branch: Rearrange the instructions such that the instructions after a
conditional branch never have to be discarded, i.e. by the time the branch
condition is evaluated and it is decided whether or not to take the branch, the
instructions following it that are already in some stages of the pipeline will
complete execution. This is usually done by the assembler/ compiler.
Computer Organization & Assembly Language, Spring 2002-03
23/04/2003