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North-East Asia Symposium on Nano, IT & Reliability (NASNIT) Vol. 14 No. 1 May 2009
An Enhanced Output Voltage Settling-Time
For High Speed LDO
Ji-Woong Kim*, Kyoung-Su Park, and Kae-Dal Kwack
Division of Electronics and Computer Engineering, Hanyang University, 17
Haengdang-dong, Seongdong-gu, Seoul 133-791, Korea
Abstract – This paper is Enhanced Single-Transistor Control
II. STRUCTURE AND OPERATION OF STC-LDO [4]
Low-dropout regulators (LDO) provides fast response and high
slew rate with Class-AB buffer. The improved low dropout
voltage regulator is settles very faster, achieving within 0.8us
settling time for a 200mA load step. The LDO is designed and
fabricated on a 0.18um CMOS process with 1.8V supply voltage.
The large external capacitor used in this LDO. Experimental
results demonstrate that the proposed LDO architecture
achieves faster transient response than previous architecture.
I. INTRODUCTION
Power management is essential in all battery-powered portable
devices such as cellular phones and PDAs in order to reduce the
standby power and prolong the battery runtime. Low-dropout
regulators (LDOs) are one of the most critical power management
modules, as they can provide regulated low-noise and precision
supply voltages for noise-sensitive analog blocks. With the
widespread proliferation of modern of the LDO are needed. First,
low dropout voltage across the pass device of the LDO is required
provide high power efficiency. In addition, the increased level of
integration in portable devices not only demands the LDO to
deliver high load current, but also requires the no-load quiescent
current of the LDO to be minimized for improving the current
efficiency. Good load transient response with small output-voltage
variation including overshoots and undershoots upon load
switching is critical to prevent an accidental turn off or resetting of
the portable device. These four major performance requirements of
the LDO, including low dropout voltage high output current, low
no-load quiescent current and small output transient undershoots
and overshoots are, however, difficult to achieve simultaneously.
The unity gain frequency, slew rate and stability of the LDO circuit
determine the overall transient response of the LDO. The output
capacitance and its associated parasitic elements affect the transient
response of the LDO circuit also [1].
It is well known that generic LDO structure suffers from
unavoidable tradeoffs between the accuracy and feedback stability
[2-3]. A high loop gain, which results in improved steady state
regulation, degrades close-loop stability, so that different
methodologies such as an advanced pole-zero cancellation scheme
in [2], a load-dependent reference voltage concept in [3].
The organization of this paper is as follows: Section II will
explanation the previous STC-LDO structure and operation.
Section III will introduce the enhanced STC-LDO and discuss the
performance of LDO. Experimental results and discussion will be
included in Section IV. Conclusions will included in Section V.
Fig. 1 Typical STC LDO with the control-voltage generation circuit
The STC-LDO is mainly composed of MP (The power PMOS
FET to deliver load current from the supply to the output), MC (The
control transistor) and a current source IBIAS. This paper used in an
off-chip capacitor COUT with ESR of RE. IOUT models the loading
circuit.
The source terminal of MC is the sensing terminal of the
common-gate amplifier MC. When VOUT varies, MC provides an
error voltage at its drain to control the gate voltage of MP. This
mechanism controls the amount of drain current delivered by MP to
regulate VOUT. The control voltage VCTRL is to provide the preset
VOUT, according to the relationship
VOUT = VCTRL +VSGC
(1)
Where VSGC is the source-gate voltage of MC. VSGC is a constant
and is independent of IOUT since it is biased constantly by IBIAS.
It is obvious from (1) that VOUT cannot be controlled
independently of temperature and process variations due to VSGC.
Therefore, a control-voltage generator is designed in Fig. 1 to
overcome this problem.
The control-voltage generator is basically a simple amplifier in
unity-gain configuration, except an additional transistor MC2 in
diode connection biased by IBIAS (same bias level of MC) is inserted
at the output stage. By providing reference voltage V REF at the
input of the unity-gain buffer, this VREF will be re-generated at the
output of the buffer. Thus, VCTRL is given by
VCTRL = VREF - VSGC2
(2)
where VSGC2 is the source-gate voltage of
MC2. Since
VSGC2=VSGC (MC and MC2 are of the same size and of the same bias
North-East Asia Symposium on Nano, IT & Reliability (NASNIT) Vol. 14 No. 1 May 2009
condition), the following relationship is achieved:
VCTRL = VREF - VSGC2
(3)
LDO is designed for voltage regulation at a small dropout
voltage for maximizing the power-conversion efficiency. Therefore,
the typical application of the LDO is to provide a regulated voltage
from a close-to-output supply voltage or as a post-regulator. The
STC-LDO is well-suited for these applications, due to its extremely
simple structure. The regulation range of the STC-LDO is given by
VIN < VOUT + VSGP - VSDC(sat)
(4)
Fig. 2 High speed STC-LDO circuit with reduced settling-time
The mechanism of voltage regulation is explained here.
Supposing VOUT is lower than the preset value, V SGC will be
enforced to be reduced such that the gate voltage of M P decreases
due to the non-inverting voltage gain of a common-gate amplifier.
The increase of VSGP causes more drain current to be sourced to the
load, as well as to the output capacitor. V OUT therefore increases.
Similarly, when VOUT is higher than the preset value, VSGP is
reduced and MP delivers less drain current to cause a decrease of
VOUT. This continuous feedback results in the voltage regulation of
STC-LDO at the preset voltage defined by VREF.
The line and load regulations of a LDO of a LDO are given by
[2]
RO
1
Load regulation = VOUT 

I OUT 1  AEAGm RO AEAGm
(5)
Fig. 3 Class-AB push-pull Common-Drain circuit
IV. EXPERIMENTAL RESULTS AND DISCUSSION
Gm RO
1
Line regulation = VOUT 

VIN
1  AEAGm RO AEA
(6)
where AEA is the voltage gain of the error amplifier in LDO; Gm
and RO are the transconductance and open open-loop output resistance of the power PMOSFET. RO in STC-LDO is reduced by 1/gmc.
In general, GmRO>1 for low-to-moderate IOUT. The approximations
in both (5) and (6) are valid. This shows that the STC-LDO
behaves similar to the conventional LDO. When IOUT is high, RO
will be dominated by rop but not 1/gmc. However, although GmRO
may not be greater one and the approximations in (5) and (6) are no
longer valid, both load and line regulations of the STC-LDO are
just same as those of the conventional LDO. Therefore, the key to
improve both load and line regulations is to develop a high-gain
error amplifier, while unaffecting the closed-loop stability.
The LDO regulator shown in Fig. 2 has been implemented in
hynix 0.18-um CMOS process. The regulator is designed to
provide a load current of 0-200mA with an output voltage of 1V
from 1.2V supply. The drop out voltage is about 200mV at the
maximum.
Enhanced STC-LDO structure provides much better LDO
transient response than the previous STC-LDO. A design condition
to improve the sensitivity of the control transistor has been derived.
Experimental results have proven the analysis and the stated
arguments.
III. ENHANCED STC-LDO CIRCUIT
At error amplifier of previous STC-LDO circuit connect the
class-AB push-pull common-drain amplifier in fig. 1. And bias
current provide to the LDO circuit by wide-swing cascade current
source. A Class AB output buffer using SFs is seen in Fig. 3. The
output buffer is comprised of M1-M4. This sets the DC current in
M1/M2 to a known value (important) [5]. This turns M1 on and
shuts M2 off (thus the class AB action). As a result, settling time of
output voltage is enhanced fast transient response and distortion for
cross-over is minimized.
Fig. 4 VOUT result to ILOAD variation in previous STC-LDO circuit
North-East Asia Symposium on Nano, IT & Reliability (NASNIT) Vol. 14 No. 1 May 2009
Fig. 5 VOUT result to ILOAD variation in Enhanced STC-LDO circuit
V. CONCLUSIONS
In this paper, the LDO regulator bases on the STC-LDO circuit.
Most important is transient response and stability. So we focused
on settling time and output impedance. Enhanced STC-LDO
structure provides much better LDO transient response than the
previous STC-LDO. A design condition to improve the sensitivity
of the control transistor has been derived. Experimental results
have proven the analysis and the stated arguments.
Finally Table I summarizes compared STC-LDO with Enhanced
LDO. Focusing on the improving the stability and transient
response, as well as the most recent work-simpler LDO structure,
which is the contribution of this paper.
Table I Compare previous STC-LDO to Enhanced LDO circuit
Tech.
STC-LDO
Proposed LDO
hynix 0.35um
0.18 × 0.24 = 0.0434
IMAX
50mA
200mA
Response Time
< 24us
< 0.8us
VDROP
200mV
200mV
ACKNOWLEGEMENT
This work was supported by the Electronics and
telecommunications Research Institute for IT-SoC core human
resources training Programs.
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