Download 210254: MICROPROCESSOR INTERFACING LABORATORY

Assignment 9
Aim: Write 8086 ALP to interface DAC and generate following waveforms on oscilloscope,
(i) Square wave - Variable Duty Cycle and Frequency.
(ii) Ramp wave - Variable direction,
(iii) Trapezoidal wave
(iv) Stair case wave
Apparatus: 8086 Kit, DAC 0808 Card, Interfacing Cables, CRO, SMPS.
Objective:
1. To understand the interfacing of DAC 0808 kit to 8086 kit,
2. To understand the operation of DAC 0808 to generate different waveforms.
Theory:
1. Performance parameters
a. Resolution: This is the number of possible output levels the DAC is designed
to reproduce. This is usually stated as the number of bits it uses, which is the
base two logarithm of the number of levels.
b. Maximum sampling rate: This is a measurement of the maximum speed at
which the DACs circuitry can operate and still produce the correct output.
c. Monotonicity: This refers to the ability of a DAC's analog output to move
only in the direction that the digital input moves
d. Settling time: settling time is the interval between a command to update
(change) its output value and the instant it reaches its final value, within a
specified percentage.
2. Different techniques of conversions:
a. Binary weighted resistor D/A converter
b. R/2R Ladder D/A converter,
SE Comp 2008 course
3. Sources of errors in DAC:
a. Differential Nonlinearity error: DNL error is the difference between the
ideal and the measured output responses for successive DAC codes. An ideal
DAC response would have analog output values exactly one code (LSB) apart
(DNL = 0).
b. Offset error: Offset error, often called 'zero-scale' error, indicates how well
the actual transfer function matches the ideal transfer function at a single
point. For an ideal data converter, the first transition occurs at 0.5LSB above
zero. For a DAC, offset error is the analog output response to an input code of
all zeros.
c. Gain error: indicates how well the slope of an actual transfer function
matches the slope of the ideal transfer function. Gain error is usually
expressed in LSB or as a percent of full-scale range (%FSR), and it can be
calibrated out with hardware or in software. Gain error is the full-scale error
minus the offset error.
4. Block Diagram of DAC 0808:
5. Pin Diagram & Features of DAC 0808
Pin Diagram
Features:
o Relative accuracy: ±0.19% error maximum
o Full scale current match: ±1 LSB typ
o Fast settling time: 150 ns typ
o Noninverting digital inputs are TTL and CMOS compatible
o High speed multiplying input slew rate: 8 mA/μs
o Power supply voltage range: ±4.5V to ±18V
o Low power consumption: 33 mW @ ±5V
E-mail: [email protected]
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SE Comp 2008 course
Procedure:
1. Get machine codes for assembly language program to generate different analog
waveforms.
2. Connect SMPS to DAC & 8086 kit.
3. Connect CRO to DAC.
4. Connect DAC card to 8086 kit using 26 pin FRC, through J2 (Used for U7- 8255 IC),
5. Enter machine codes to generate different waveforms and execute.
6. Observe the different waveforms on CRO,
7. Take readings for different parameters like Amplitude, Frequency, Duty cycle
8. Draw waveforms on graph paper.
Working of DAC Card:
1. We are using U7- 8255 IC to interface DAC kit,
2. Port A & B are used as output ports and port C as input port.
3. Port A is connected to DATA lines of DAC, PB0 is connected to ‘G’ pin of 74373
Latch IC, Port C is used to read status of DAC,
4. Initialise 8255 using control word (89 - to set PA,PB as output port, PC as input port
and all ports in MODE 0)
5. Initialise 74373 Latch IC by making PB0 high i.e. by sending 01h to on port PB,
6. Execute the program to generate different waveforms,
7. Observe the waveform on CRO.
8. Take readings.
Algorithms for programs:
A) Algorithm for Square wave with Variable Duty Cycle and frequency:
1.
2.
3.
4.
5.
6.
7.
Initialise U7- 8255 with CW 89h
Initialise 74373 Latch IC by sending 01h to PB,
Get 0FFh in AL register and send to DAC using PA,
Insert delay equal to ON time (Ton)
Get 00h in AL register and send to DAC using PB,
Insert delay equal to OFF time (Toff)
Repeat Steps from 3 to 6,
For variable Duty cycle:
Change Ton & Toff without changing T (Ton+Toff)
For variable Frequency:
Change T (Ton + Toff)
B) Algorithm for Ramp wave (Variable Direction) generation:
1.
2.
3.
4.
5.
6.
Initialise U7- 8255 with CW 89h
Initialise 74373 Latch IC by sending 01h to PB,
Get 00h in AL register
Send to DAC
Increment AL &
Repeat 4 & 5
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SE Comp 2008 course
For reverse direction:
1. Initialise U7- 8255 with CW 89h
2. Initialise 74373 Latch IC by sending 01h to PB,
3. Get 0FFh in AL register
4. Send to DAC
5. Decrement AL &
6. Repeat 4 & 5
C) Algorithm for Trapezoidal wave generation:
1. Initialise U7- 8255 with CW 89h,
2. Initialise 74373 Latch IC by sending 01h to PB,
3. Get 80h in AL register,
4. Send to DAC,
5. Increment AL & repeat till AL= FFh,
6. Insert delay ,
7. Decrement AL & Send to DAC till AL = 00h,
8. Insert delay,
9. Repeat from step 4.
D) Algorithm for Staircase wave generation:
1. Initialise U7- 8255 with CW 89h,
2. Initialise 74373 Latch IC by sending 01h to PB,
3. Initialise SI with 2000h
4. Initialise counter with 05h
5. Get Byte from lookup table and send to DAC,
6. Insert delay,
7. Increment SI
8. Decrement count & repeat step 5,6,7 & 8 till count get zero,
9. Initialise counter with 05h
10. Get byte from lookup table and send to DAC,
11. Insert delay,
12. Decrement SI
13. Decrement count & repeat step 10,11,12 & 13 till count get zero,
14. Repeat from step 3
Conclusion: Hence we have performed the practical to generate different waveforms using
Dyna86 kit and DAC card.
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