Download Background Statement for SEMI Draft Document 5842 New

Background Statement for SEMI Draft Document 5842
New Standard: Test Method for Metal Wrap Through Solar Cell Via
Resistance
Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in
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“patented technology” is defined as technology for which a patent has issued or has been applied for. In the latter case,
only publicly available information on the contents of the patent application is to be provided.
Background Statement:
The quality of metallized vias has significant effects on the electrical parameters of Metal Wrap Through
(MWT) solar cell. Optimization of metallized vias is desired; however, currently this is limited not only by
the screen but also the characteristics of the via filling paste, so a trade-off is needed in design. Therefore,
measurement of the quality of the metallized vias is required when adopting new screen and new paste in
the trial process. Due to frequent screen changes, it is necessary to monitor the quality of the metallized vias
to guarantee stability of mass production. This standard is intended to develop an accurate and rapid method
for determining the metallized vias quality of Metal Wrap Through solar cells by using 4 points of
single-side test. This standard is expected to fill the gap of domestic and international standards. The ballot
results will be reviewed and adjudicated at the meetings indicated in the table below. Check www.semi.org/standards
under Calendar of Events for the latest update.
Review and Adjudication Information
Group:
Task Force Review
Committee Adjudication
Crystalline Silicon Solar Cell Task Force
China PV Committee
July 29th, 2016
9:00 ~ 18:00
Yinchuan International Communication
Center Hotel
Yinchuan, Ningxia
TBD
Time & Timezone: TBD
Location:
TBD
Date:
City,
State/Country:
China
Leader(s):
Song Dengyuan (Yingli)
Chen Rulong (Suntech)
Cai Xianwu (CETC48)
Guangchun Zhang(CanadianSolar)
Jun Liu(CESI)
Standards Staff:
Kris Shen(SEMI China)
[email protected]
Kris Shen(SEMI China)
[email protected]
Meeting date and time are subject to change, and additional TF review sessions may be scheduled if
necessary. Contact the task force leaders or Standards staff for confirmation. Check
www.semi.org/standards for the latest schedule.
If you have any questions, please contact to SEMI PV Module Task Force
Xusheng Wang / Canadian Solar
Tel: +86 66908088
E-mail: [email protected]
Or contact SEMI Staff, Kris Shen at [email protected]
Semiconductor Equipment and Materials International
3081 Zanker Road
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Phone: 408.943.6900, Fax: 408.943.7943
DRAFT
SEMI Draft Document 5842
New Standard: Test Method for Metal Wrap Through Solar Cell Via
Resistance
1 Purpose
1.1 The purpose of this standard is to standardize a fast and accurate test method for determining metallized vias
quality of metal wrap through solar cells.
2 Scope
2.1 This standard defines the test method for determining metallized vias quality of Metal Wrap Through (MWT)
solar cells.
2.2 This standard applies to test method for metallized vias quality of metal wrap through solar cells by four points
test.
NOTICE: SEMI Standards and Safety Guidelines do not purport to address all safety issues associated with their use.
It is the responsibility of the users of the documents to establish appropriate safety and health practices, and determine
the applicability of regulatory or other limitations prior to use.
3 Referenced Standards and Documents
3.1 ISO Standard1
ISO 14644-1:2015 Cleanrooms and associated controlled environments. Part 1:Classification of air cleanliness by
particle concentration
NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions.
4 Terminology
4.1 Abbreviations and Acronyms
4.1.1 mΩ — milliohm
4.1.2 Ω — ohm
4.1.3 A — ampere
4.1.4 V — volt
5 Summary of Test Method
5.1 Four points test is a method to evaluate the quality of Metal Wrap Through solar cells by calculating equivalent
resistance according to Ohm’s law (see Figure 1).The advantages of four points test are shown in Appendix 2.
Figure 1
The Test Principle
1
International Organization for Standardization, ISO Central Secretariat, 1, ch. de la Voie-Creuse, CP 56, CH-1211 Geneva 20, Switzerland;
Telephone: 41.22.749.01.11, Fax: 41.22.733.34.30, http://www.iso.org
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development)
activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Doc. 5842  SEMI
LETTER BALLOT
Document Number: 5842
Date: 5/10/2017
Semiconductor Equipment and Materials International
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San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
DRAFT
5.1.1 Via B in the dashed box is the measured hole, and Via A and Via C are adjacent to Via B. The letters b, d, and f
indicate the frontages of the three holes, which are connected through grid lines of the cell.
5.1.2 Letters a, c, and e are the isolated back contacts of holes b, d, and f.
5.1.3 One probe of the current source is placed on the back contact (a) of Via B, and the other one is placed on the
back contact (e) of Via A.
5.1.4 One probe of the voltmeter is placed on the back contact (a) of Via B, and the other one is placed on the back
contact (c) of the adjacent Via C.
5.1.5 5.1.5 According to Ohm's law, the equivalent resistance of the measured Via B can be calculated.
5.2 The equivalent circuit of the test (see Figure 2).
Figure 2
The Equivalent Circuit of the Test
5.2.1 The bulk resistivity of silicon is much higher than electrical resistivity of metal, so the bulk resistance of silicon
can be ignored. Figure 2 is the equivalent circuit of the test. From the circuit, we can derive
Rmeasured  Rvia  R pad
（1）
Where:
Rmeasured
: Equivalent resistance of the measured hole
Rvia : Resistance of the measured hole
R pad : Electrode resistance
5.2.2 In MWT solar cells, to form the current path from the frontage to the back surface, each hole should be filled
with metal paste. However, some holes cannot be completely filled in actual production due to factors such as the
vacuum degree, the properties of pastes, operating parameters of the screen printing, etc. This phenomenon can cause
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development)
activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
Page 2
Doc. 5842  SEMI
LETTER BALLOT
Document Number: 5842
Date: 5/10/2017
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
DRAFT
a sharp increase of the value of Rvia . Since R pad can be seen as a constant, the value of
Rmeasured
can indirectly
represent the quality of the holes. In addition, contact characteristics between the metal and the semiconductor might
affect the testing results. The I-V curve using four points test is shown in Appendix 1.
6 Apparatus
6.1 Current Source – used to test current values across the resistor of measured via.
6.2 Voltmeter – used to test voltage values in the resistor of measured via.
7 Safety Precautions
7.1 Power switch and the power outlet of the current source are checked for safe operation before and after use.
8 Test Specimens
8.1 Sample required: Finished MWT cells.
9 Preparation of Apparatus
9.1 Because of the high sensitivity of the crystalline silicon cell surface, the testing environment should meet the
following requirements:
9.1.1 Ambient temperature should be 25℃±2℃; ambient humidity should be 60%RH±20%RH.
9.1.2 Environmental cleanliness should be better than 6 grade clean room requirements as defined in ISO
14644-1:2015 "Cleanrooms and associated controlled environments. Part 1:Classification of air cleanliness by particle
concentration".
10 Calibration and Standardization
10.1 Instruments should be calibrated regularly to maintain the best test condition.
10.2 Reset the balance before using the electronic balance and voltmeter.
11 Procedure
11.1 Select the test sample: finished MWT cells.
11.2 Adjust the sample position: Place the sample on the testing platform with the front side up and back side down.
11.3 The platform should be set at flat level.
11.4 Select the test vias on the sample according to the test requirements.
11.5 Test vias on the sample by following the steps described in the Section 5.
11.6 Finish test and record results.
12 Calculation
12.1 Calculation Formula
Rmeasured 
U measured
(m)
I measured
(2)
Where:
Rmeasured
: Equivalent resistance of the measured hole
U measured : Voltage meter reading
I measured : Current source for reading
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development)
activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
Page 3
Doc. 5842  SEMI
LETTER BALLOT
Document Number: 5842
Date: 5/10/2017
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
DRAFT
Document Number: 5842
Date: 5/10/2017
LETTER BALLOT
13 Report
13.1 The report shall contain the following elements:
13.1.1 Sample sources, sample names.
13.1.2 Characterization and condition of the test item.
13.1.3 Date of receipt of test item and date of test, where appropriate.
13.1.4 Test result (including the test cure and the calculation results).
13.1.5 Tester, review, approval, report number.
13.1.6 Testing agencies, testing name, testing address.
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development)
activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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DRAFT
APPENDIX 1
Experimental Verification of the Diode Effect
NOTICE: The material in this Appendix is an official part of SEMI [document 5842#] and was approved by full letter
ballot procedures on [A&R approval date].
A1-1 Experimental Verification of the Diode Effect
A1-1.1 The I-V curve using four points test is shown in Figure A1-1. There is good linearity between the current and
the voltage. Therefore, we can make the conclusion that the influence of diode effect on resistance testing can be
ignored.
I-V curve
8.00
6.00
Current(A)
4.00
-0.03
2.00
0.00
-0.02
-0.01
-2.00
0
0.01
0.02
0.03
-4.00
-6.00
-8.00
Voltage(V)
Figure A1-1
The typical I-V curve
This is a Draft Document of the SEMI International Standards program. No material on this page is to be construed as an official or adopted Standard or Safety Guideline.
Permission is granted to reproduce and/or distribute this document, in whole or in part, only within the scope of SEMI International Standards committee (document development)
activity. All other reproduction and/or distribution without the prior written consent of SEMI is prohibited.
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Doc. 5842  SEMI
LETTER BALLOT
Document Number: 5842
Date: 5/10/2017
Semiconductor Equipment and Materials International
3081 Zanker Road
San Jose, CA 95134-2127
Phone: 408.943.6900, Fax: 408.943.7943
DRAFT
APPENDIX 2
The Advantages of Four Points Test
NOTICE: The material in this Appendix is an official part of SEMI [document 5842#] and was approved by full letter
ballot procedures on [A&R approval date].
A2-1 The Advantages of Four Points Test
A2-1.1 Easy to operate and all the probes are distributed on the rear surface of the cells.
A2-1.2 The contact resistances between probes and metal are eliminated.
A2-1.3 More accurate, better repeatability.
A2-1.4 No impact of light induced current.
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Doc. 5842  SEMI
LETTER BALLOT
Document Number: 5842
Date: 5/10/2017