Download File - J

Reference
Revision
Date
2800.1010.5014
A
04/03/2016
Technical Details
J-Testr Demo Interposer MK2
1 UUT Features
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3.3V 6A (12V input) supply for UUT
2.5V 6A (12V input) supply for UUT
1.8V 500mA LDO (powered from the 2.5V UUT supply)
2 Atmel UC3L 32bit CPUs Devices (JTAG and serial connected)
Multiple voltage IOs with level shifting to device 2
32 IO connected to UUT
12 Bit DAC (with shared and simulated separate reference)
12 Bit ADC (with shared and simulated separate reference)
14.7456MHz clock oscillator
7.3728MHz clock oscillator
2 Interposer Features

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JTAG IO or LVIO Peripheral Card connection
(1010-1002 // 1010-1010)
LV or HV Power Supply Peripheral Card connection (1010-1004 // 1010-1008)
80W Load Peripheral Card connection
(1010-1006)
Precision ADC/DAC Peripheral Card connection
(1010-1005)
Timer Peripheral Card connection
(1010-1007)
HVIO Peripheral Card connection (breakout only) (1010-1009)
Interposer bypass adapter
(1010-6000)
Custom PSU ripple amplifier/comparator
Status LEDs and run button
Power-on LEDs
LED array attached to the Timer Card (for Signal Generator evaluation)
Precision ‘Go J-Safe’ circuitry triggered from UUT
3 Description
The J-Testr Demo Interposer card and UUT are coupled with some of the more popular & common J-Testr Peripheral
Cards to demonstrate the powerful features that the J-Testr system can bring to customers. The Demo UUT has IO,
analogue and power functions, and the Demo Interposer connects to it via either a direct connection or via ribbon
cables so that the UUT can be housed on the J-Testr ‘Top Mounting Plate’ or within a test fixture.
The demo shows how this UUT can be 100% tested for functionality using JTAG tools (via the JTAG connection) or via
any other software platform that can communicate via Ethernet (e.g. Winsock on Windows).
The tests include advanced tests that are difficult, if not impossible, on other test systems. Such tests include:




Power supply UVLO threshold testing
Power supply operational frequency measurement
Power supply transient response testing
Accurate measurement of higher frequency signals
All these tests are achieved within the small footprint of the J-Testr system without the use of any bulky external
measurement equipment.
Page 1 of 14
Copyright © 2014 Eigerdesign GmbH
Test code is provided for the XJTAG XJEASE software, and also for ATEASY, but other JTAG or test SW platforms (such
as JTAG Technologies, Goepel, Labview, Python, etc.) can also be used. No other supplementary programs are usually
required.
When using JTAG software tools, test speeds are shown to be extremely fast, especially given the high level of
testability, this is mostly due to the high efficiency JTAG to System Bus converter at the heart of the J-Testr system.
Similar speeds are achieved in more conventional test tools, via the Ethernet connector, however these tools may
take slightly longer vs. JTAG due to the efficient way some JTAG test tools handle IO testing.
The demo also shows how easily additional circuitry can be added to the ‘customer’ interposer, whilst maintaining a
very high level of signal integrity due to the lack of cables to the stimulation peripheral cards.
Page 2 of 14
Copyright © 2016 Eigerdesign GmbH
4 UUT Block Diagram
3.3V 6A
Switching
Power Supply
Power Out
Connector
3V3
Power In
Connector
2.5V 6A
Switching
Power Supply
2V5
1V8_Measure
1V8
LDO
500mA
3V3
DAC SPI x 3
UUT DAC
12 Bit
SPI ADC
UUT ADC
1V8
12 Bit
SPI DAC
3V3
JTAG
Connector
Level Shifting
ADC SPI x 3
TDI
TDO
PortB
FW
Heartbeat
LED
FW
Heartbeat
LED
(non JTAG only)
(non JTAG only)
D2_LS_Measure
Level
Shifter
3V3
IO
X8
D2_LED_Measure
2V5 IO x8
LED
3V3 IO x8
D1_LED_Measure
(for non-JTAG Testing only)
D1 Test Comms
DAC SPI x 3
LED
2V5
IO
X8
PortA
D2 Test Comms
PortA
3V3 IO x8
7.3728
MHz
Clock
UC3L
Device 2
ADC SPI x 3
D1_Frequency
UC3L
Device 1
(for non-JTAG Testing only)
14.7456
MHz
Clock
Port B
3V3
2V5
2V5
1V8
ID1
Reset
ID0
Reset
3V3
1V8
TDI
TDO
D2_Frequency
Signal Connectors
Page 3 of 14
Copyright © 2016 Eigerdesign GmbH
PWR LED
5 Interposer Block Diagram
PWR LED
2V5_In
2V5
Sys_3V3
D2_LS_Measure
D1_LED_Measure
D2_LED_Measure
D1 Test Comms
JTAG Lines x 4
UUT
JTAG Connector
Sys_5V
Precision
OV Circuit
1V8_Measure
1V8_Measure
ADC_DAC Card Connector
(Slot 6)
UUT ADC
UUT DAC
ADC
Remote Sense
3V3_Level
nSystem_Reset
nSystem_JTAG_Mode (not used)
nOV_Trigger
DAC
Load Card Connector
(Slot 7)
3V3_VRipple
UUT
Power Out
Connector
Sys_5V
nBypass
LED
5120_1010_6000
Interposer Bypass Adapter
Sys_2V5
2V5_VRipple
Transient response
Sense Circuitry
Sys_5V
Sys_3V3
3V3
2V5_Level
UUT
Power In
Connector
Supply Card Connector
(Slot 0)
3V3_In
Pass
LED
Fail LED
Runnin
g LED
Run
Switch
GP_LED x 1
D1_Frequency
D1_PB_3V3 IO x8
D1_LED_Measure
D1 Test Comms
(for non-JTAG Testing
only)
Bank1
3V3_VRipple
GP_LED x 8
8 Bit General
Purpose
LED Array
2V5_VRipple
D1_PA_3V3 IO x8
1V8_Measure
UUT ADC
D2 Test Comms
IO_3V3
D1_PB_3V3 IO x8
IO_3V3
D1_PA_3V3 IO x8
Modules
D2_PA_ 3V3 IO X 8
D2_PB_2V5 IO x8
D2_LED_Measure
D2 Test Comms
(for non-JTAG Testing
only)
D2_PA_ 3V3 IO X 8
D2_LS_Measure
IO_2V5
IO_3V3
CPLD4
(Bank3)
IO_3V3
D2_Frequency
UUT Card Connectors
CPLD3
(Bank2)
D2_PB_2V5 IO x8
Peripheral Card Connectors
CPLD2
(Bank1)
UUT DAC
IO_2V5
Custom Circuitry
IO Card Connector
(Slot 4)
CPLD1
(Bank0)
UUT
Signal Connectors
Timer Card Connector
(Slot 5)
Bank0
1 Bit General
Purpose
LED
D1_Frequency
D2_Frequency
Page 4 of 14
Copyright © 2016 Eigerdesign GmbH
6 Test Safety (J-Safe)
The demo uses the safety features built into J-Testr as standard as below:
3.3V and 2.5V UUT Power Supply Input Over-Voltage
If the Input voltage of the UUT power supplies goes over the set limit on the power supply card, the J-Testr
will enter J-Safe condition and shutdown the whole system immediately.
3.3V and 2.5V UUT Power Supply Output Over-Voltage
Using the special ‘Over Power’ voltage threshold on the electronic loads, if the output voltage from the UUT
power supplies goes over the set limit, the J-Testr will enter a J-Safe condition and shutdown the whole
system immediately.
3.3V and 2.5V UUT Power Supply Input Over-Current
If the output current from the J-Testr power supplies goes over the set limit on the power supply card, the JTestr will enter J-Safe condition and shutdown the whole system immediately.
1.8V Over-Voltage
The demo interposer will trigger a J-Safe condition, using the unique ‘Go-Safe’ input feature, if the 1.8V
exceeds the hardware set threshold. This is achieved with a simple comparator circuit on the interposer that
compares the voltage to be protected (i.e. 1V8 in this case), with a known reference and outputs the logical
result to a User_IO configured as a Go-JSafe input pin.
This feature can help protect very sensitive internal power rails that are often used by many modern logic or
processor devices, and which can easily be damaged by over-voltages.
Once the ‘Go-Safe’ input is triggered the J-Testr enters a J-Safe condition shutting down the whole system
immediately.
The circuit used in the demo is a precision circuit and does a differential measurement of the 1.8V being
protected. A simpler, but less accurate, circuit could also be implemented using only a comparator and a
reference or even a single chip ‘power monitor’ type device.
To trigger the Over-Voltage on the demo UUT short:
J31
ERR OV 1V8 VOLT
UUT 1.8V Voltage Error OV High (Component Value Error)
System Over-Voltages and Over-Current
The internal system voltages, which are generated on the motherboard, all have their own fixed over-voltage
and over-current thresholds that will trigger a J-Safe condition. Like with all J-Safe conditions the J-Testr will
shut down the whole system immediately to protect the UUT.
Page 5 of 14
Copyright © 2016 Eigerdesign GmbH
7 Functional Tests
7.1 Power supply UVLO
7.1.1 Description
Both the UUT 2.5V and 3.3V supplies are tested to determine the trigger threshold of the under-voltage lockout
(UVLO).
7.1.2 Testing
Correct fitted component values and bad solder joints in the PSU under voltage circuit.
7.1.3 Error Simulation
Removing the below connector links will cause UVLO errors:
J29
nERR 3V3 UVLO
UUT 3.3V UVLO Error High (Component Value Error)
J13
nERR 2V5 UVLO
UUT 2.5V UVLO Error High (Component Value Error)
7.2 Power supply output voltage accuracy
7.2.1 Description
The UUT 1.8V, 2.5V and 3.3V supplies are tested for output voltage accuracy
7.2.2 Testing
Supply basic function and accuracy of component values (wrong values fitted) in the supply feedback circuitry
7.2.3 Error Simulation
Fitting the below connector links will cause supply output errors:
J30
ERR 3V3 VOLT
UUT 3.3V Voltage Error Low (Component Value Error)
J14
ERR 2V5 VOLT
UUT 2.5V Voltage Error Low (Component Value Error)
J32
ERR UV 1V8 VOLT
UUT 1.8V Voltage Error Low (Component Value Error)
7.3 Power supply operation frequency
7.3.1 Description
Tests both the 3.3V and 2.5V switching power supplies for correct operational frequencies. Running at incorrect
frequencies can cause improper PSU performance, and can also stress power supply components which reduces long
term reliability.
This test uses the custom PSU ripple amplifier/comparator circuit added to the interposer
7.3.2 Testing
Makes sure the PSU frequency set resistor is correct and that the PSU is not skipping cycles which can occur when
operating near the minimum or maximum ‘on’ or ‘off’ times.
7.3.3 Error Simulation
Fitting the below connector links will cause supply operational frequency errors:
J25
ERR 3V3 FREQ
UUT 3.3V Frequency Error High (Component Value Error)
J12
ERR 2V5 FREQ
UUT 2.5V Frequency Error High (Component Value Error)
Page 6 of 14
Copyright © 2016 Eigerdesign GmbH
7.4 Power supply efficiency
7.4.1 Description
The efficiencies of both the UUT 3.3V & UUT 2.5V switching power supplies are tested at the middle current rating of
3A
7.4.2 Testing
Tests that supplies are running correctly and that there are not excessive losses in the switching FETS (e.g. due to
overheating of bad thermal connections). Also tests that the supply inductor is fitted correctly and that the DCR value
is not causing excessive losses.
7.4.3 Error Simulation
Error simulation not possible due to difficulty placing test links in high DI/DT parts and/or high current paths of the
supplies.
7.5 Power supply transient response
7.5.1 Description
Tests the UUT 3.3V & UUT 2.5V switching supplies for transient response by placing fast current load transients on the
supply output.
7.5.2 Testing
Proves the supply is correctly compensated and that the component values in the compensation network are the
correct values. Also tests the integrity of the connection of the output capacitors whose ESR value is critical to the
initial response of the supplies
It can also prove the supply is not in oscillation.
This test uses the custom PSU ripple amplifier/comparator circuit added to the interposer
7.5.3 Error Simulation
Removing the below connector links (2x) will cause transient errors
J26 & J27
nERR 3V3 CAP
UUT 3.3V Transient dip error (2nd Output Capacitor not fitted correctly)
J10 & J11
nERR 2V5 CAP
UUT 2.5V Transient dip error (2nd Output Capacitor not fitted correctly)
7.6 Standard IO Testing
7.6.1 Description
Tests the IO connection to the UC3L devices using XJTAG connection tests or with custom firmware with control over
the IO using the UART connection
7.6.2 Testing
Tests all IO lines for short and opens on an individual line bases (No loopback) improving the accuracy/speed of
locating faults.
7.6.3 Error Simulation
Removing the below connector links will cause an open circuit IO Error
J2
nERR D1 IO OPEN
Device 1 IO line open circuit Error (Net 3V3_D1_PA_BUS7)
J17
nERR D2 IO OPEN
Device 2 IO line open circuit Error (Net LS_D2_PA_BUS7)
Placing the below connector links will cause an short circuit IO Error
J1
D1 IO SHORT
Device 1 IO line short (Nets 3V3_D1_PB_BUS0 to 3V3_D1_PB_BUS1)
J20
D2 IO SHORT
Device 2 IO line short (Nets 2V5_D2_PB_BUS0 to 2V5_D2_PB_BUS1)
Page 7 of 14
Copyright © 2016 Eigerdesign GmbH
7.7 Level Shifting Testing
7.7.1 Description
Tests the IO level shifter on Device 2 for correct operation by measuring the IO voltage after the level shifter
7.7.2 Testing
Checks the level shifter device is the correct part (e.g. parts with vs parts without internal Vcc diode) and that the part
is operating as expected and has the correct supply, and is not shorted I/P to O/P on the line(s) measured.
7.7.3 Error Simulation
Placing the below connector links will cause a level shifting error
J19
ERR D2 LS
Device 2 IO Level shifter incorrect voltage shift
7.8 Clock Oscillator Testing
7.8.1 Description
Accurately tests the frequency of the UC3L oscillators
7.8.2 Testing
Checks the correct oscillator has been fitted in each location and checks the clock frequency is within limits
7.8.3 Error Simulation
Placing the below connector links will cause an oscillator error by disabling the device
J24
D1 CLK ERR
Device 1 oscillator disabled / non functional
J16
D2 CLK ERR
Device 2 oscillator disabled / non functional
7.9 LED Testing
7.9.1 Description
Tests the two LEDs on the UUT for function by measuring the voltage across the LED whilst it is turned on. i.e. the
forward operating diode voltage Vf is measured. Although this is not always practical in some test applications, this
simple measurement can prove a low cost & effective way to check that the LED device has been fitted and is the
correct polarity.
Alternatives are:
Visual check
- Slow and requires manual input
Opto-sensor (Like J-Opto) - Requires some kind of fixturing but provides the ultimate in LED testing
7.9.2 Testing
Check the voltage whilst the device is turned ‘On’ – Voltage between 2 – 2.5V
Check the voltage whilst the device is turned ‘Off’ – Voltage below 0.5V
7.9.3 Error Simulation
Removing the below connector links will a LED Error
J3
nERR D1 LED
Device 1 LED not fitted or incorrect polarity
J18
nERR D2 LED
Device 2 LED not fitted or incorrect polarity
Page 8 of 14
Copyright © 2016 Eigerdesign GmbH
7.10 ADC Testing
7.10.1 Description
Tests the UUT ADC using the accurate J-Testr 16bit DAC across a range of settings
7.10.2 Testing
The correct voltage reference value/accuracy, ADC IO operation and ADC linearity across a range
7.10.3 Error Simulation
Removing the below connector link will cause an ADC communication error.
J8
nERR ADC LOGIC
ADC communications data output made open circuit
Removing the below connector link will remove the UUT’s ADC input signal.
J7
nERR ADC MEAS
ADC input signal made open circuit
Placing the below connector link will cause the ADC reference to be approximately 1.5% low
J9
ERR ADC REF
ADC reference made approximately 1.5% low
7.11 DAC Testing
7.11.1 Description
Tests the UUT DAC using the accurate J-Testr 16bit ADC across a range of settings
7.11.2 Testing
The correct voltage reference value/accuracy, DAC IO operation and DAC linearity across a range
7.11.3 Error Simulation
Removing the below connector link will cause a DAC communication error.
J4
nERR DAC LOGIC
DAC communications clock made open circuit
Removing the below connector link will remove the UUT’s DAC output signal.
J5
nERR DAC MEAS
DAC output signal made open circuit
Placing the below connector link will cause the DAC reference to be approximately 1.5% low
J23
ERR DAC REF
DAC reference made approximately 1.5% low
Page 9 of 14
Copyright © 2016 Eigerdesign GmbH
7.12 ADC/DAC Loopback Testing
This test has been added to show how ADC/DAC loopback can fail to detect reference errors.
Test setup requires the below in correct order:
J4
J8
J7
J5
J6
J9
J23
nERR DAC LOGIC
nERR ADC LOGIC
nERR ADC MEAS
nERR DAC MEAS
LOOP
ERR ADC REF
ERR DAC REF
Link Fitted (default)
Link Fitted (default)
Link Removed (non-default)
Link Removed (non-default)
Link Fitted (non-default)
Link Fitted (non-default)
Link Fitted (non-default)
Software:
Disable
TestADC
Disable
TestDAC
Enable
Test ADC DAC Loopback
Adding the links to ERR ADC REF and ERR DAC REF pins simulates the ADC and DAC sharing a reference which has a
1.5% error. This test highlights the need for using external accurate DAC/ADC because such loopback tests are unable
to detect this type of error.
This is an additional problem with testing ADC and DAC in loopback. Other problems include:
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Failure does not indicate which function (ADC or DAC) is at fault.
Accuracy tests are limited, especially when using separate references.
Voltage ranges should be similar or the same
Page 10 of 14
Copyright © 2016 Eigerdesign GmbH
8
Default Setup
The below links must be fitted (GREEN):
nERR 3V3 UVLO
nERR 2V5 UVLO
nERR 3V3 CAP
nERR 2V5 CAP
nERR D1 IO OPEN
nERR D2 IO OPEN
nERR ADC LOGIC
nERR ADC MEAS
nERR DAC LOGIC
nERR DAC MEAS
nERR D1 LED
nERR D2 LED
The below links must not be fitted (RED)
ERR 3V3 VOLT
ERR 2V5 VOLT
ERR UV 1V8 VOLT
ERR OV 1V8 VOLT
ERR 3V3 FREQ
ERR 2V5 FREQ
D1 IO SHORT
D2 IO SHORT
ERR D2 LS
D1 CLK ERR
D2 CLK ERR
ERR ADC REF
ERR DAC REF
LOOP
Page 11 of 14
Copyright © 2016 Eigerdesign GmbH
9 Errata
Rev A
On UUT PCB Silkscreen:
ERR_D2_LS is incorrectly marked as nERR_D2_LS
On UUT PCB Silkscreen:
nERR_D2_LED is incorrectly marked as ERR_D2_LED
10 Disclaimer
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION
PURPOSES ONLY and is not considered by Eiger Design GmbH to be a finished end-product fit for general consumer or
industrial use. It generates, uses, and can radiate radio frequency energy and has not been tested for compliance with
the limits of computing devices pursuant to part 15 of FCC rules or European CE marking regulations.
All Voltages present on the demonstration kit are under 50Vac or 75Vdc, making it exempt from the Low Voltage
Directive (LVD) 2006/95/EC
Page 12 of 14
Copyright © 2016 Eigerdesign GmbH
11
Contents
1
UUT FEATURES .................................................................................................................................................... 1
2
INTERPOSER FEATURES ....................................................................................................................................... 1
3
DESCRIPTION ...................................................................................................................................................... 1
4
UUT BLOCK DIAGRAM ......................................................................................................................................... 3
5
INTERPOSER BLOCK DIAGRAM ............................................................................................................................ 4
6
TEST SAFETY (J-SAFE) .......................................................................................................................................... 5
7
FUNCTIONAL TESTS ............................................................................................................................................. 6
7.1
POWER SUPPLY UVLO .............................................................................................................................................. 6
7.1.1
Description .................................................................................................................................................. 6
7.1.2
Testing......................................................................................................................................................... 6
7.1.3
Error Simulation .......................................................................................................................................... 6
7.2
POWER SUPPLY OUTPUT VOLTAGE ACCURACY ................................................................................................................ 6
7.2.1
Description .................................................................................................................................................. 6
7.2.2
Testing......................................................................................................................................................... 6
7.2.3
Error Simulation .......................................................................................................................................... 6
7.3
POWER SUPPLY OPERATION FREQUENCY ....................................................................................................................... 6
7.3.1
Description .................................................................................................................................................. 6
7.3.2
Testing......................................................................................................................................................... 6
7.3.3
Error Simulation .......................................................................................................................................... 6
7.4
POWER SUPPLY EFFICIENCY ........................................................................................................................................ 7
7.4.1
Description .................................................................................................................................................. 7
7.4.2
Testing......................................................................................................................................................... 7
7.4.3
Error Simulation .......................................................................................................................................... 7
7.5
POWER SUPPLY TRANSIENT RESPONSE .......................................................................................................................... 7
7.5.1
Description .................................................................................................................................................. 7
7.5.2
Testing......................................................................................................................................................... 7
7.5.3
Error Simulation .......................................................................................................................................... 7
7.6
STANDARD IO TESTING ............................................................................................................................................. 7
7.6.1
Description .................................................................................................................................................. 7
7.6.2
Testing......................................................................................................................................................... 7
7.6.3
Error Simulation .......................................................................................................................................... 7
7.7
LEVEL SHIFTING TESTING ........................................................................................................................................... 8
7.7.1
Description .................................................................................................................................................. 8
7.7.2
Testing......................................................................................................................................................... 8
7.7.3
Error Simulation .......................................................................................................................................... 8
7.8
CLOCK OSCILLATOR TESTING ...................................................................................................................................... 8
7.8.1
Description .................................................................................................................................................. 8
7.8.2
Testing......................................................................................................................................................... 8
7.8.3
Error Simulation .......................................................................................................................................... 8
7.9
LED TESTING .......................................................................................................................................................... 8
7.9.1
Description .................................................................................................................................................. 8
7.9.2
Testing......................................................................................................................................................... 8
7.9.3
Error Simulation .......................................................................................................................................... 8
Page 13 of 14
Copyright © 2016 Eigerdesign GmbH
7.10 ADC TESTING ......................................................................................................................................................... 9
7.10.1 Description .................................................................................................................................................. 9
7.10.2 Testing......................................................................................................................................................... 9
7.10.3 Error Simulation .......................................................................................................................................... 9
7.11 DAC TESTING ......................................................................................................................................................... 9
7.11.1 Description .................................................................................................................................................. 9
7.11.2 Testing......................................................................................................................................................... 9
7.11.3 Error Simulation .......................................................................................................................................... 9
7.12 ADC/DAC LOOPBACK TESTING ................................................................................................................................ 10
8
DEFAULT SETUP .................................................................................................................................................11
9
ERRATA ..............................................................................................................................................................12
10
DISCLAIMER .......................................................................................................................................................12
Page 14 of 14
Copyright © 2016 Eigerdesign GmbH