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Transcript
Designing with Advanced CMOS Technologies Elad Alon Stanford University [email protected] Disclaimer • No two technologies are the same • This was always true, but even more so now • No two designers’ opinions are the same either • These are just MHOs What I’ll Focus On • Lots of ways that changes in the technology can affect your design • I’ll give some background, but try to focus on things you may not initially expect What’s Different About Advanced Technologies? • Gate leakage • Can be even larger than S/D leakage, and more noticeably alters circuit design • Aggressive channel length scaling side effects • Many different devices available in the same technology • Thick-oxide, low-Vth, high-Vth, etc • SOI Devices Behavior Gate Leakage • Quantum mechanics caught up to us • Carriers tunnel directly through the oxide • Strongly dependent on W, L, Tox, and Vgx • Ig α ~WL • Ig α exp(1/Tox) • Ig α Vgx4 • Not very dependent on temperature • Probability of tunneling not a strong function of temp. Poly Igs N+ Igc, Igb P Igd N+ Gate Leakage (cont’d) • Electrons more likely to tunnel than holes. Poly • ~2x more gate leakage for NMOS devices Igs • Remember BJTs? • Aggressive MOSFETs have β of ~3000 • DC input impedance of FET no longer infinite • Can affect circuit design in some slightly unexpected ways • (for us MOS guys anyways) N+ Igc, Igb P Igd N+ How Gate Leakage Affects Circuit Design: Example #1 • You will almost never see this again in SPICE: • “**error**: no dc path to ground from node 0:g” • Node g will sit at some leakage defined voltage g g How Gate Leakage Affects Circuit Design: Example #2 • Don’t route control signals and/or biases too far or to too many devices • Was never a good idea – even worse now • Every single receiving device will draw current from the signal • Signal at the end of the line != signal at beginning • Non-linear voltage divider • Wire resistance exacerbates the problem • Don’t fall into the “it’s a DC signal” trap • “Well, my chip didn’t quite work because I couldn’t get it to come out of reset…” How Gate Leakage Affects Circuit Design: Example #3 • Extension of ex. #2: large current mirror ratio can give very unexpected results • May not get any current at the output at all Ibias Iout = ? 1x 1000x Ileak How Gate Leakage Affects Circuit Design: Example #4 Vin Vin Wc W cCg W cIg • Obviously, S&H based circuits are most heavily affected by gate leakage • No more floating nodes, remember? • Time constant of gate node ~independent of sizing: • Area ↑ C ↑, I ↑ How Gate Leakage Affects Circuit Design: Example #4 Vin Thick-oxide • Common solution: don’t use thin oxide devices in sensitive circuits • But, can’t always meet performance or headroom requirements this way • More on this later One Last Warning About Gate Leakage • Leakage in general can be nasty to model – gate leakage even more so • Relatively “new” effect, modeling kinks still being worked out • Some vendors have separate gate leakage models which are not turned on by default • Gate leakage can have a big impact on simulation time • Watch out for unphysical models • I’ve seen models with Ig ≠ 0 even when Vgs = Vgd = Vgb = 0 • I’ve also seen models with S-1 = 160mV/decade… Aggressive Channel Length Scaling • For performance reasons, many companies have scaled Leff faster than wire pitch Poly N+ Poly N+ P N+ N+ P • Clearly increases leakage and “traditional” short channel effects • But has other interesting side effects as well Channel Length Scaling Side Effects Poly Cfringe Cfringe Cov N+ Cgc Cov N+ • Constant Cg/μm vs. tech. assumes Tox and L scale together • L scaled a little faster • Reduces overall gate capacitance: • .35μm: Cg/μm = 2fF/μm • 90nm: Cg/μm = 1.1-1.3fF/μm • 65nm: Cg/μm = 0.9fF/μm Channel Length Scaling Side Effects (cont’d) Poly Cfringe Cfringe Cov N+ Cgc Cov N+ • Reduced gate capacitance mainly due to decrease in gate-tochannel capacitance • Fringe and overlap components become significant • Because Cgc is a smaller portion of total: • Cgd nearly equal to Cgs • Even when the device is in saturation • Lower gate cap. large (relative) delay penalty for driving fixed capacitive loads (i.e. wires) Device Options in Modern Technologies • Scaling has taken us (well) past the point where “1 size fits all” • Tradeoffs between performance, power, high voltage, etc. • Foundries now often provide lots of device options • Low Vth, Super-high Vth, Analog Vth • “Intermediate”, Double gate oxide thickness • 2.5V or 3.3V I/O • Sometimes process is even fragmented into different market segments • E.g. General Purpose (GP) vs. Low Power (LP) in TSMC/ST So How Do We Use These Device Options? • Some circuits can greatly benefit from these “special” devices • Thick-oxide capacitors • High-Vth to minimize leakage in e.g. integrators • Low-Vth to improve performance in digital circuits or reduce headroom • Often mix device types within the same circuit • Thin-oxide, short-channel for speed • Thick-oxide, long-channel tail for CM rejection V+ V- Vbias Some Caveats • Different device types impose additional layout constraints • E.g., often have minimum spacing rules between low-Vth and regular devices Spacemin Low-Vt Implant • Non-standard devices usually won’t have all the characteristics you want • Thick-oxide devices usually have higher Vth Some Caveats (cont’d) • Never rely on matching between different device types • “Special” devices often less well controlled • Low-Vth devices in particular • Tweaks to optimize short-channel devices are also applied to special devices “for free”… • Device options are definitely a good thing • But they also give you more rope to hang yourself with • Always remember K.I.S.S. SOI Devices Poly N+ P N+ Buried Oxide Substrate • Several companies have transitioned to SOI for highperformance products • Reduced S/D parasitic capacitances, improved isolation and short-channel effects • Many challenges in designing with these devices • Most well-known is history effect in partially-depleted (PD) SOI Matching with SOI Devices • In floating body devices, Vth is slaved to the body voltage. • Body voltage often set entirely by leakage • Leakage is exponentially sensitive to many process parameters • Therefore, floating body devices have very poor matching • Mismatch can even vary with temperature… • Typical solution: Body-contacted SOI devices Body-contacted SOI Devices • Extended poly to isolate the channel • P+ region to form an electrical contact to the body S N+ D N+ B - P+ • Sets DC body voltage and greatly improves matching • At the expense of loss in performance due to additional gate capacitance and higher average Vth. Body-contact Resistance • Body connection is through the device silicon • FET itself is not very thick 50-100nm Poly N+ N+ P Buried Oxide Substrate • Large series R to “real” body • Past a certain frequency, bodycontacted devices are floating too! S N+ D N+ B - P+ Effects of High Body-Contact Resistance • Body contacted device still has history • Just that the history doesn’t extend “forever” like in floating body device • Analog circuit designer’s view: vd vd vg gmvg ro Cbd vb gmbvb Cbs Rbody Effects of High Body-Contact Resistance (cont’d) • Typical body-contacted FET gain vs. frequency: 35 Gain (V/V) 30 25 20 15 10 7 10 10 8 9 10 Frequency (Hz) 10 10 • Body feedback causes output impedance (and hence gain) of device to drop • High frequency gain roughly set by gm/ gmb Floating Body Small Signal Model • For completeness, let’s look at floating body devices as well: • Note that because of diode biases, Rbd >> Rbs vd vg Rbd vd gmvg ro Cbd vb gmbvb Cbs Rbs Floating Body Small Signal Response • Low frequency gain set by resistive divider: • Zo ≈ ro||[(Rbd+Rbs)/Rbsgmb] 6 5.5 • High frequency gain set by capacitive divider: 4.5 Gain (V/V) • Zo ≈ ro||[(Cbd+Cbs)/Cbdgmb] 5 • “Kink” bends down because Rbd >> Rbs • At right bias point kink could actually bend the other way… • All devices would become high pass filters 4 3.5 3 2.5 2 1.5 1 4 10 6 10 Frequency (Hz) 8 10 10 10 Closing Thoughts • Process designers’ jobs are getting really hard • They will make the changes they need to make the process manufacture-able • Device changes may not always be desirable for circuit design • But this means that there’s more innovation to be done to make best use of these devices • Remember all the “Is Analog Circuit Design Dead?” panels at ISSCC? • One of the biggest challenge of designing in advanced technologies has nothing really to do with the devices themselves: • Managing complexity is key.