Download Introduction to Class

Ensuring Clean Power
for RF and Digital Applications
Tom Boehler and Steven Sandler
AEi Systems
Los Angeles, CA, 90045; 310-216-1144
[email protected]
[email protected]
Copyright © 2012 AEi Systems, LLC
All Rights Reserved
How Performance is Impacted By Poor
Stability

PSRR
Reverse
Reverse
Transfer
Transfer
Accuracy
Poor Stability Permeates System
Performance
 Degrades PSRR
 Degrades reverse transfer
 Degrades output impedance
 Degrades output noise
 Degrades voltage accuracy
Distributed Architecture Power System
Bus
Input
Filter
Converter
LDO
Filter
1.5V
LDO
Filter
1.8V
LDO
Filter
2.5V
3.3V
Power Supply Measurements
PSRR
Voltage
Regulation
Crosstalk
Ripple &
Noise
Filter
Stability
Dropout
Step
Load
DUT
Input Z
Stability
Output
Z
Tempco
Reverse
Transfer
Bode Plots - Stability





Measures:
 Bandwidth
 Phase Margin
 Gain Margin
Pick your injection
location carefully!
Frequency response will
vary with line voltage
and load current
The transformer is a
crucial part of the
measurement
Injection signal size is
very important as well
Bode Plots - Stability
Output Impedance
Output Impedance

Why is this important?

Many PDNs have impedance requirements
Identifies L-C resonances of filters or parasitics
Provides and alternative way to measure the
stability of a system

30
25
20
15
10
TR1/dB

5
0
-5
-10
-15
-20
102
103
104
105
f/Hz
TR1: Mag(Impedance)
106
107
Output Impedance
Tg
Q
d
d
Tg Freq 
Group Delay from Phase
Quality Factor from Group Delay

4
1  1  4 Q  180

PM  atan


 
4
2 Q


Phase Margin
Output Impedance
Step Load
Step Load
Low resolution



LM117 Step Load Transient
High resolution
Small signal vs. large signal measurements, slew rate limitations
Ring Freq., Amp., & Phase are a function of the load step period!
Sampling Issues – may miss L*di/dt spikes
Step Load
30
25
20
15
TR1/dB
10
5
0
-5
-10
-15
-20
102
103
104
105
106
107
f/Hz
TR1: Mag(Impedance)
Corresponding Output Impedance
How do we know the ringing is real?
We measure it, we model it, and we
can see it in the output impedance.
And Resulting Transient Response
Power Supply Rejection Ratio
Power Supply Rejection Ratio
Power Supply Rejection Ratio



Performance is a strong function of stability
IC manufacturers often spec PSRR at 60-120Hz which is not useful
for space applications
Poor PSRR performance can be a serious issue in distributed
architectures
Power Supply Rejection Ratio
Going back to our PDN example…
Bus
Input
Filter
Converter
LDO
Filter
LDO
Filter
1.8V
LDO
Filter
2.5V
1.5V
iac
3.3V

Current perturbations on the output of a regulator can go right back through to the
bus and due to real bus impedance will present itself as a voltage

These voltage perturbations will then go through other regulators on the bus
through their PSRR
Power Supply Rejection Ratio
Reverse Transfer
Power Supply Rejection Ratio
Reverse Transfer
1
10
TR1/dB
0
-10
-20
-30
f/Hz
TR1/dB
Cursor 1 20.134k 14.048
-40
102
103
104
105
106
107
f/Hz
TR1: Mag(Gain)

Unlike PSRR, at low frequency there is little to no signal
attenuation

Reverse transfer leads to crosstalk between regulators
connected to the same power bus
How RF and Digital Performance is
Impacted By Poor Stability


So how does poor stability affect a power supply?
Many characteristics are severely degraded by poor phase margin
•


Crosstalk, Reverse Transfer, Phase noise, Jitter, ENOB, Noise in ADCs
and other parameters
Many of our classical measurement techniques are no longer valid
Systems are more complex, requiring complete characterization &
verification, moving towards more simulation becoming difficult
•
Many SPICE models offer poor fidelity
How RF and Digital Performance is
Impacted By Poor Stability

PSRR
Reverse
Reverse
Transfer
Transfer
Accuracy
Poor Stability Permeates System
Performance
 Degrades PSRR
 Degrades reverse transfer
 Degrades output impedance
 Degrades output noise
 Degrades voltage accuracy
So why does it matter?
So why does it matter?
So why does it matter?


20MHz clock phase
noise measurement
 Powered by
regulator with
70º of phase
margin
Only 4.9ps of Jitter
– very clean
So why does it matter?


20MHz clock phase
noise measurement
 Powered by
regulator with
15º of phase
margin
Jitter now
measures 481ps –
NOT acceptable.
Summary

As load circuitry becomes more complex and the switching
speeds and magnitudes grow, power systems design
becomes more critical to the overall performance of the
product





We need better characterization data
Measurement of all key aspects of a power system is
ESSENTIAL
We need to make measurements more accurately
There are better test techniques and test equipment that can
help us that don’t cost a fortune
Think of better more stable power supplies as a free
performance boost for digital and RF systems!
Thank you for listening!
Questions?