Download Problem Set #5: Due Date -

ECE 679 – Problem Set #5: Low-Power Transmitter Drivers; Low Power
Equalizers – DUE May 29, 2007
NOTES:
We are well on the way to a 10 x 10 x 10: 10lanes @10Gb/s @ 10mW/link
A current estimate of the power consumption is:
TX:
1mW – Transmitter Data Syncrhonizer
1mW – 2:1 Transmitter Pre-Driver
2mW – Transmitter Output Driver
FX:
1mW – Receiver Continuous-Time Equalizer
1mW – Receiver clk/clkb 1:2 Quantizer
1mW – Receiver Data Synchronizer
CLKS:
0.5mW – One 5GHz LC Oscillator (5mW / 10 shared lanes)
1mW – Two Quadrature-locked LC Oscillators (10mW / 10 shared lanes)
Resulting in about 10mW per 10 lanes
NOTE: Power consumption for the 10 lanes includes all the power of the components
above. For simplicity, we have provided the 1:2 demultiplexing quantizers from my
doctoral student Jing-Guang, found in his directory “ECE679_SCH”.
I have also built the TX data synchronizer and RX data synchronizers in my ‘pchiang’
directory: “library: 90nm_library”, under cells “retimer” and “retimer_rx”.
In regards to the 1UI phase delay, we can build 0.5UI fixed (using quadrature LCs at the
receiver), and only need to generate 0.5UI variable at the receiver. 0.25UI variable(with
fine interpolation range) can be achieved by fine precision of the common-mode voltage
of the quantizers(giving about 10ps of phase shift per 100mV common mode shift).
Hence, only 0.25UI (variable with coarse tuning) is necessary from the data section. This
0.25UI coarse tuning can be done with simple 0.16UI coarse steps in the data.
1. Low Power Output Driver
Clearly, swinging 400mV transmitter output swing is not going to allow us to reach our
target of 2mW for the output driver.
First, if we reduce our output swing to 100mV, we can obtain more than a 4x decrease in
output current. Using a RX-CTLE, we can improve the output eye diagram to 150mV
pk-pk.
a. LVDS Driver – Low Voltage Differential Signaling Output Driver
We obtained a 4x decrease in output swing current by reduced swing. We can reduce
power dissipation another 2x by using a LVDS driver, as seen below:
Vcur2
Dinb
Din
Channel
50 , td
Din
Dinb
Vcur
Here, current sources on top and bottom both push current(PMOS) and pull
current(NMOS) into the line, effectively reducing the dissipated current by ½ for the
same output swing.
*) Modify your current transmitter design for a 100mV output swing. This should reduce
the transmitter power consumption from 16mA to 4mA, and the pre-amp from 4mA to
1mA.
*) Build this LVDS driver, for a 100mV output swing. You will likely set the common
mode(through the biasing of the midpoint of the two 50 Ohm transistors to 0.5*Vdd, and
attempt for a 100mV differential swing.
Obviously, bias Vcur2 and Vcur1 to the same current values. You will need to size the
PMOS and NMOS correctly to ensure that the r0 has a high output impedance.
*) Show the eye diagram after transmission through the transmitter and receiver. What is
the new power dissipation for this LVDS transmitter output driver, including the newly
sized pre-drivers?
HINT: This LVDS driver is good for reduced output current (bipolar signaling) since
current is pushed and pulled through both current sources.
However, there exist three problems. First, the 4-series transistors in a 1V supply make
such a device very inefficient for high output swing. Second, because the PMOS devices
are used, the input capacitance to the pre-driver stage is inefficient because of the
additional loading of the PMOS. So, power in the pre-driver does not scale well.
Third, because the output impedance of the current source devices is very large, an
explicit 50 Ohm / 50Ohm termination resistance is needed at the source, to reduce any
reflection at the transmitter point. However, adding termination here increases the
b. Voltage-Mode Signaling
We can achieve even another 2x reduction in current consumption using a voltage mode
output driver. The voltage-mode driver also uses bipolar signaling (pushing and pulling
current). However, the other benefit is that the transistors are operating in the triode
region, and hence, can effectively act as 50 Ohm termination resistances for the channel.
This means that the output swing can now be double from what it was for current mode
signaling since there is no explicit 50 Ohm termination resistor here.
Of course, then the impedance matching(and proportional crosstalk ) become worse.
Vcontrol
Dinb
Din
Din
Dinb
Design the voltage-mode output driver as seen above. Assume Vcontrol is created by an
on-chip supply regulator (as seen in the Rambus paper), and we don’t have to create that
here.
Assume for simplicity the 2:1 pre-driver is similar to the pre-driver we have built for our
previous designs.
*) Create the output driver sizes for Vcontrol(and Vswing) equal to: 50mV, 100mV,
200mV, and 400mV.
*) How does the output impedance vary for various values of Vswing? i.e. the
impedance of the NMOSs will remain in the linear/triode regime for smaller swings, but
not for larger swings.
*) Also note that the sizes of the NMOS transistors cannot be changed for varying
amounts of the output swing. To change the output swing, only Vcontrol can be
modified, but then the devices behave more nonlinearly.
This is not the same for current-mode drivers, as increasing the current source value
increases the swing, but the output impedance remains the same.
*) Quickly resimulate again, but add a 10% worst case mismatch between the
devices(due to process mismatch). What happens to the eye diagram symmetry?
*) Quickly resimulate again, but add a 10% voltage supply step to the supply “vcontrol”.
Make the 10% voltage step a fast transient with a 50ps rise time. How does this voltage
step affect the output voltage swing?
*) Essentially, this is showing the “power-supply” sensitivity of this output driver.
Qualitatively, does such a voltage step have the same effect on a current-mode signaling
scheme?
2. Low Power Equalizers
There are easier ways to achieve equalization with little/no power, and we will explore
some possibilities.
First, recall that we have attempted to obtain equalization using 1) transmitter
feedforward, current-summing equalizer, and 2) receiver high-pass source-degenerated
CTLE. Recall that for simple channels, feed-forward transmitter equalization can be
somewhat power hungry, as the 1st postcursor tap must dissipate ~1/2 power of the main
tap, and this doesn’t include the clock power overhead.
a. Feed-forward Capacitive Equalizatoin
*) Attempt simple, zero-power equalization by using a feed-forward capacitor/zero.
(Use either the current-mode or voltage-mode transmitter output drivers)
Vdd
Vdd
50
50
Dinb
Din
Vcur
The values of the series resistance need to be made relatively large, such that they don’t
intereference with the 50 Ohm matched output impedance.
*) How well does such a structure do with equalization?
Equalization pole can be modified by using a “programmable”, digital series resistance.
*) Attempt this simple passive equalizer not only in the transmitter but also in the
continuous-time linear equalizer.
b. Gyrator Structure
Inductors are expensive on-die, but you can make very small, active inductors on-die
using “gyrators”.
Vdd + dV
Vdd
Vdd
Din
Din
CLK
CLKb
Data0
Data1
Classical 2:1 Pre-Amp
Multiplexer
CLK
CLKb
Data0
Data1
Gyrator 2:1 Pre-Amp
*) How does this structure work? (show qualitative proof of why this exhibits a zero)
*) Why does this structure require the DC bias of the gate input to be “Vdd + dV”?
*) Implement this structure, in replace of slow RC pre-amp that you are using now. Size
the NMOS here to give you the same type of swing as before, but not exhibits rise-time
peaking for the output drive.r
*) What is the current/power consumption of this type of gate?