Download TE-MPE-EP : Activities during TS3

TE-MPE Technical Meeting
TE-MPE-EP, VF, 11-Oct-2012
Update on the DQLPU type A
design and general progress.
DQLPU: old configuration
Fip connector
Front view
SYKO
DQQDL#A DQQDL#B DQAMC
TE-MPE-EP, VF, 11-Oct-2012
Rear view
Fip connector
UHDS#1-#4 + Trigger
Vtaps
Current Loop
230VAC
External and mechanical modifications to the enclosure
TE-MPE-EP, VF, 11-Oct-2012
4cm
2 Hinges
No cabling between back panel and motherboard
Harting pins for pcb adapters
TE-MPE,EP, VF, 11-Oct-2012
spacers
Burndy connectors for pcb
Voltages
Vtaps
Internal hardware change after new implementation
Motherboard (viewed from inside)
V taps
TE-MPE-EP, VF, 11-Oct-2012
DQQDL#A
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Voltage power supplies
DQQDL#B
DQHSU Input signals UHDS+trigger and Spare I loop in/out
DQCSU
SPARE
DQHSU
DQAMC
FIP con./PROG.
DQQDL A/B : local redudancy quench detectors.
Harting Han E modules: Vtaps connector.
Harting Han 32 B: Power supplies connector.
DQCSU: Crate supervision unit: to monitor all voltages + test presence of the current in the loop
+ remote power cycling.
Burndy 8 for signals from current transformers.
SPARE: For futur upgrades.
Burndy 12 for UDQHDS and trigger signal + another Burny 8/12 for spare.
DQHSU: Quench heater supervision unit. To record fast current and voltage during a discharge of DQHDS.
Burndy 12 (2x): Input and output current loop.
DQAMC: Communication board to the supervision.
4TE front panel: Fip connector + reprogramming connector for DQAMC and DQCSU.
= Futur emplacement for nanoFip board.
TE-MPE-EP, VF, 11-Oct-2012
Status for boards and connectors:
• Motherboard: to be designed according to a few final decisions to be taken
after some tests are performed.
• DQQDL: re-use all old DQQDL with new firmware. 200 new DQQDL in more
exposed areas received and to be tested.
• DQCSU: prototype for all analog and digital stages done and tested. Quotes
for components requested.
• DQHSU: second prototype with a relay installed on it to monitor the fuse
inside the DQHDS. To be tested (Jens). Still minor modification to be done.
An ultimate prototype will be needed. Most of components ordered.
• DQAMC: re-use of all old DQAMC with new firmware. Spares in the pipeline.
• Harting Han 32B: still waiting for information about adapting the length of
pins and if Harting can produce a complete pcb adapter (set of 32 pins linked
together).
• Harting Han E modules: individual assembling of 6 pins or one set of 6.
• Transmission of signals from current pulse transformers to the motherboard:
tests to be performed to verify the quality of the transmission of signals
before acceptance of a burndy connector. If unsuccessful, BNC connectors
would be the alternative.
What can be re-used
Burndy 12 M-M cable:
For UHDS measurement
and trigger.
TE-MPE-EP, VF, 11-Oct-2012
-Harting Han E module:
Entire cable from Crawford box
Connector from DQLPU:
For Voltage taps.
Syko (trivolt switching mode power supplies):
re-used in DQLPU type B (Quad)
for redundancy (4 x SYKO)
DQQDL (2x), DQAMC
Firmware changes
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3.
TE-MPE-EP, VF, 11-Oct-2012
4.
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Transmission of new signals for quench heater supervision and crate
supervision.
Implementation of additionnal commands sequences for specialists: e.g.
power cycling, device configuration.
Adaption to the new layout of the QPS fieldbus: macro-cycle length
change from 200 ms  100 ms: higher transmission rate but much
higher data volume.
Visibility board A and B, separate post-mortem buffers from board A / B
and quench heater supervision.
Developmnent started as well as integration into QPS high level
supervision.
Homework for the user: development of automatic analysis tools for
quench heater supervision.
Conclusion
Real advantages of this update and new supervision:
TE-MPE-EP, VF, 11-Oct-2012
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Complete redundancy of linear power supplies.
Quick diagnostic if loop interrupted.
Current and voltage discharge  detection of a possible defect in a heater.
Automatised discharge at low voltage after quench or spurious discharge
of DQHDS monitor heater before continuing.
• Much more data due to increase of sampling.
• Time acceptable thanks to the doubling of the wordfip network and a
change in the firmwares (macro-cycle reduced from 200ms100ms).
• Advantage of a completely new hardware design: a lot of time during tests
saved basically due to the process of assembling the motherboard. No
defect due to bad connections possible.
TE-MPE-EP, VF, 11-Oct-2012
Thank you !