Download A Single-Stage Low-Dropout Regulator with a Wide Dynamic Range

A Single-Stage Low-Dropout Regulator with a Wide
Dynamic Range for Generic Applications
Abstract:
Single-stage regulator topologies are often preferred in embedded applications due to their low
power consumption with a single-pole behavior, resulting in easy frequency compensation. Since
the achievable differential gain from a single stage is low, the dc load regulation is poor over a
wide dynamic range. This paper presents a single-stage, adaptively biased, low-dropout regulator
to achieve a comparable dc load regulation similar to multistage topologies. This is achieved
mainly by modifying the adaptive bias loop which amplifies both the common-mode and
differential-mode signals. In addition, as the proposed regulator is stable for a wide range of
output capacitors, including the capacitor-less (on-chip) and with-capacitor (off-chip) conditions,
it is suitable for more generic applications. The proposed regulator is implemented in a standard
0.18-µm CMOS technology. The experimental results show that the regulator is capable of
delivering up to 100 mA with a dc load regulation of 0.140 mV/mA and is stable with Co ≤ 3.3
nF (capacitor-less) and Co ≥ 1 µF (with-capacitor). The proposed architecture of this paper the
area and power consumption are analysis using tanner tools.
Enhancement of the project:
Change the technology and maximize the current efficiency.
Existing System:
Fig. 1 shows the conventional AB-LDO regulator architecture reported. The MFL is a negative
feedback loop consisting of the transistors in the path M2–M4–MP–M3 for both the topologies.
The only difference is in their ABL which is a positive feedback loop. For the topology in Fig.
1(a), the ABL consists of the transistors in the path M2–M4–M6–M7–M1. On the other hand, an
additional path M3–M5–M8–M9 along with M2–M4–M6–M7–M1 forms the ABL in the
topology in Fig. 1(b). How this incremental change affects the various parameters of the
regulator is discussed in the following.
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com
Fig. 1. Conventional, single-stage AB-LDO regulator architectures. (a) Topology-1. (b)
Topology-2.
DC Load Regulation
The dc load regulation of an AB-LDO regulator mainly depends on two factors. As Io changes,
the ABL adjusts the current I1 through M1 under large signal operation, and the value of I1
determines the dynamic range of Io. The differential gain of the MFL is another deciding factor
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com
for improving the dc load regulation mainly under small signal operation. In a single-stage
topology, the MFL has limited differential gain, and hence it has least implication on improving
the dc load regulation. Therefore, it is worth investigating whether/how the ABL can help in
achieving a better load regulation in a single-stage topology.
Slew Rate
Both the topologies in Fig. 1 have a pull-down slew rate with a little difference in their values.
The topology in Fig. 1(a) has a pull-down slew rate of (I1 + If )/Cg, whereas the same is I1/Cg for
the topology in Fig. 1(b). Here, Cg is the equivalent gate capacitance of MP. However, there is no
pull-up slewing path. Whenever Io changes from high to low, the gate of MP needs to be pulled
up to a higher voltage. Due to the absence of the pull-up slewing path, the rising of the gate
voltage solely depends on the pull-up resistor 1/gm,4 and the gate capacitance Cg. More
importantly, as I4 reduces to a very low value at low load condition, the value of 1/gm,4 increases
exponentially. As a result, an exponential rising behavior is expected at the node V1. Needless to
say, it produces a large and prolonged overshoot at the output of the regulator.
Stability
In Fig. 1(a), all the parasitic poles that are created at the internal nodes push out to a very high
frequency. Thus, a small value of an off-chip capacitor at Vo is sufficient to stabilize the loop.
On the other hand, the topology in Fig. 1(b) has a stability issue and it requires an additional
capacitor Cc for improving the same.
Disadvantages:

Current efficiency is less
Proposed System:
Fig. 2(a) shows the proposed regulator architecture. Each of M4 and M5 is segmented into two
parts, such as (M4a, M4b) and (M5a, M5b), respectively. The transistor pair M4b–M5b is connected
in a cross-coupled configuration, as shown in Fig. 2. The width ratios between M4a–M4b and M5a
–M5b pairs are 1:β, where β < 1 for amplifier operation.
The cross-coupled pair is widely used in the multistage comparator design to enhance the
differential gain using a fixed-bias scheme. In a single-stage configuration, when the crosscoupled pair is combined with adaptive biasing, the operation of the later one is uniquely altered.
The proposed ABL offers a few advantages. First, the variables A and β are the width ratios of
the transistors and they are mostly independent of Io. For a low input dc offset, a large size of
M2 (and M3) is always preferred.
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com
Fig. 2. Proposed regulator architecture
Due to these reasons, the proposed topology provides a much better dc load regulation compared
with Topology-1 and Topology-2. Second, the dc operating point of the regulator alters during
large load change as the factor A · I2 changes proportionally with Io. Therefore, this factor is
responsible to maintain the dc accuracy of Vo during a large load change. However, a small error
is always present due to the inequality given in (9). The factor due to differential operation tries
to correct the error around a dc operating point. Therefore, the dc accuracy of the regulator is
greatly increased. Third, as I1 now is the combination of the currents due to the common mode
and differential modes of operation, the magnitude of the latter one need not be very high as
required in Topology-2.A small signal model of the proposed regulator is shown in Fig. 3 to
analyze the stability of the MFL and the ABL.
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com
Advantages:

Current efficiency is maximum
Software implementation:

Tanner tools
Further Details Contact: A Vinay 9030333433, 08772261612, 9014123891 #301, 303 & 304, 3rd
Floor, AVR Buildings, Opp to SV Music College, Balaji Colony, Tirupati - 515702 Email:
[email protected] | www.takeoffprojects.com