Download Interface Between Process Equipment And Process Bus for Light

Interface Between Process Equipment
And Process Bus for Light Weight
Testing Of Protection Functions
KHURRAM, ZEESHAN ALI
Master’s Degree Project
Stockholm, Sweden August 2012
XR-EE-ICS 2012:015
Abstract
The technological advancements in the substation automation give rise to many new
challenges for the engineers. The IEC 61850 standard defines the most advanced techniques towards the digital substation development. It describes the communication
mappings for the substation automation of both conventional and digital substations.
The most important challenge is to replace old successful and reliable protection relays
with the newly born microprocessor based relays called intelligent electronic devices
(IEDs). The IEC 61850 standard gives the novel ideas in its sub-clauses IEC 600448 and IEC 61850-9-2 about digital communication and sampled values transmission
over an Ethernet link called process bus. As this thesis is the Part-A and it is mainly
based on the development of the conventional instrument transformers, analog to digital data converter and a multi-bus power system. The scope of this study contains the
development of current and voltage transformer models in SIMULINK which gives the
ideal behaviour of the conventional instrument transformers for voltage and current
measurements.The methodology of this study is to model the Sigma-Delta analog to
digital converter in the SIMULINK and then simulated results are verified according
to the standard. The 4KHz output (Voltage/Current) signal is obtained in the digital
form with 16-bit resolution. The SNR (Signal to Noise Ratio) and ENOB (Effective
Number of Bits) of the data converter is verified both theoretically and practically.
In the next phase the multi-bus power system is modelled in the SIMULINK using
SimPowerSystems Library to make the final tests on the developed product. Finally
the developed models of Project Part-A have been integrated with the transmission
model developed in the Project Part-B, collectively known as Merging Unit. The
functionality of this complete developed product is to get 3-phase analog signals of
currents and voltages from the instrument transformers, perform signal processing
on these signals and then transmit them on the Ethernet port in the form of SV
(Sampled Value) stream according to the IEC 61850-9-2 standard. The developed
Merging Unit is then connected to the different nodes of the power system to test
the performance and reliability of the Merging Unit. The over current and differential protection functions are tested on the ABB’s RET 670 IED (Protection Relay
for Transformer). In both test cases three phase short circuit fault is applied to the
power system to check the behaviour of the Merging Unit during normal and abnormal conditions. It detects all the values correctly during pre-fault condition, fault
condition and post-fault condition.
I want to dedicate this degree project to my teachers,family and friends.
iii
Acknowledgments
First of all I would like to thank Allah Almighty for the completion of my thesis.
It is pleasure to thank the many people who made this thesis possible.
I would like to express my deep and sincere gratitude to my Supervisor, Mr.Nicholas
Honeth, Ph.D student at the Department of Industrial Information and Communication Systems, The Royal Institute of Technology (KTH). His wide knowledge and his
logical way of thinking have been of great value for me. His encouragement, inspiration and personal advice ensure the progress and quality of this research work. I
would also like to pay my regards to Professor Lars Nordstrom for his kind behaviour
and positive feedback during the substation automation courses and this thesis work.I
can not help mentioning Mr.Mustafa Chenine Ph.D student at Industrial Information
and Control Systems for his fruitful advices during my stay at ICS. I would also like
to mention Dr.Arshad Saleem for his help during the thesis.
At ABB, I would like to express my gratitude to my supervisors Mr.Johan Salj and
Mr.Klas Koppari for their encouragement, guidance and patience towards me during
the whole master thesis. I would also like to thank Dr.Murari Saha for his administrative assistance throughout this project.
I want to thank my seniors and friends in KTH ; Zeeshan Ahmed,Umer Zeeshan,
Shoaib Almas, Zeeshan Talib, Amir Sultan, Naveed Khan,Muhammad Salman, for
their support, kindness and useful advices all the time.
I would like to mention my class fellows; Farhan, Malik Usman, Usman Shaukat, Amit
Kumar, Siaful with whom I spent a wonderful time during entire Master Degree in
Electrical Engineering. I will always miss the movements spent with Farhan while
going back to home after university. I would like to thank Amit Kumar Jha for his
support during entire Master Degree.
Last but not the least,I would like to thank Pencheng Zhao, my fellow thesis worker
and close friend. Without his co-operation, company and invaluable assistance the
work would not have been as enjoyable and successful.
iv
I wish to thank my Peer-o-Murshad Baba Majeed (Babajee) and my best friends
Rana Matloob, Aurangzeb Poomi, Rana Poond, Asad Malhi and Faisal Dev for helping me get through the difficult times, and for all the emotional support, comraderie,
entertainment, and caring they provided.
Furthermore I am thankful to everyone that has participated in any way in my thesis
project.
”Believers pray to God for the protection of faith, But few pray for the gift of his
love. I am ashamed at what they ask for, Even more at what they are willing to yield.
Religion is quite unaware of the spiritual plane, To which love can raise us. O Lord,
keep my love for you ever fresh, Says Bahu: I shall mortgage my religion for it”.
Zeeshan Ali Khurram
Stockholm, 2012
v
Table of Contents
Abstract
i
Dedication
ii
Acknowledgements
iii
List of Acronyms
ix
List of Tables
xi
List of Figures
xii
1 Introduction
1.1 Introduction . . . . . . . . . .
1.2 Project Goals and Objectives
1.3 Scope of the Project . . . . .
1.4 Motivation . . . . . . . . . . .
1.5 General Limitations . . . . . .
1.6 Outline of Report . . . . . . .
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3 Models of CT/PT
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2 Methodology
2.1 Research Method . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 IEC 61850 Standard for Substation Protection and Automation
2.3 Conventional Substation Architecture . . . . . . . . . . . . . . .
2.4 Digital Substation . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Merging Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Merging Unit Related Work . . . . . . . . . . . . . . . . . . . .
2.7 Design of Merging Unit . . . . . . . . . . . . . . . . . . . . . . .
2.7.1 Data Acquisition and Processing Function . . . . . . . .
2.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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3.2
3.3
3.4
3.5
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4 Modelling Of Analog To Digital Converter In SIMULINK
4.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Analog To Digital Conversion . . . . . . . . . . . . .
4.1.2 Steps From Analog To Digital Conversion . . . . . .
4.1.3 Analog Input Signals . . . . . . . . . . . . . . . . . .
4.1.4 Sampling . . . . . . . . . . . . . . . . . . . . . . . .
4.1.5 Aliasing . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Types Of Analog to Digital Conversions . . . . . . . . . . .
4.2.1 Selection Of ADC Type . . . . . . . . . . . . . . . .
4.3 Principle Of Flash ADC . . . . . . . . . . . . . . . . . . . .
4.3.1 Voltage Comparator . . . . . . . . . . . . . . . . . .
4.3.2 Flash ADC Modelling . . . . . . . . . . . . . . . . .
4.3.3 Priority Encoder . . . . . . . . . . . . . . . . . . . .
4.4 Sigma-Delta Analog To Digital Converter . . . . . . . . . . .
4.4.1 Why Sigma-Delta ADC? . . . . . . . . . . . . . . . .
4.4.2 Sigma-Delta Modulator Working . . . . . . . . . . .
4.4.3 Signal Sampling . . . . . . . . . . . . . . . . . . . . .
4.4.4 Quantization Noise . . . . . . . . . . . . . . . . . . .
4.4.5 Sigma-Delta Modulator Quantization Noise . . . . .
4.4.6 Order Of Modulator And Quantization Noise . . . .
4.4.7 SNR Of Sigma-Delta ADC . . . . . . . . . . . . . . .
4.5 Complete SIMULINK Model Of Sigma-Delta ADC . . . . .
4.5.1 Analog Filter Design Block . . . . . . . . . . . . . . .
4.5.2 Integrator Block . . . . . . . . . . . . . . . . . . . . .
4.5.3 Signum Block . . . . . . . . . . . . . . . . . . . . . .
4.5.4 Zero Order Hold Block . . . . . . . . . . . . . . . . .
4.5.5 FIR Decimation Block . . . . . . . . . . . . . . . . .
4.5.6 Transport Delay Block . . . . . . . . . . . . . . . . .
4.6 Comprehensive Sigma-Delta Design Explanation . . . . . . .
4.7 Simulation Results . . . . . . . . . . . . . . . . . . . . . . .
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5 Modelling Of Power System In SIMULINK
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1.1 Power System Modelling . . . . . . . . . . . . . . . . . . . . .
5.1.2 Power System Modelling In SimPowerSystems . . . . . . . . .
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3.6
Instrument Transformers . . . . . . . . . . . . .
Conventional Instrument Transformers VS NCIT
Conventional Instrument Transformers . . . . . .
Non-Conventional Instrument Transformers . . .
3.5.1 General Configuration of ECTs and EVTs
Simulink Model of CT/VT . . . . . . . . . . . . .
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vii
5.2
5.3
List Of SimPowerSystems Blocks Used . . . . . .
5.2.1 Three phase Programmable Voltage Source
5.2.2 Three Phase Transformer . . . . . . . . .
5.2.3 Three Phase PI Section Line . . . . . . . .
5.2.4 Three Phase OLTC . . . . . . . . . . . . .
5.2.5 Three Phase Series RLC Load . . . . . . .
5.2.6 Three Phase Fault . . . . . . . . . . . . .
5.2.7 Metering Blocks . . . . . . . . . . . . . . .
5.2.8 Discrete Three Phase Sequence Analyser .
5.2.9 Power GUI Block . . . . . . . . . . . . . .
Full Modelled Power System . . . . . . . . . . . .
5.3.1 Purpose of Power System . . . . . . . . .
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6 Complete Test Platform
6.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2 Physical Test Platform . . . . . . . . . . . . . . . . . . . . . .
6.3 Protection Function Testing Tools . . . . . . . . . . . . . . . .
6.3.1 Hardware Tools . . . . . . . . . . . . . . . . . . . . . .
6.3.2 Software Tools . . . . . . . . . . . . . . . . . . . . . .
6.4 Lab Setup for the Soft Merging Unit Testing . . . . . . . . . .
6.5 Complete System Integration . . . . . . . . . . . . . . . . . .
6.5.1 Protection Function Testing Scheme . . . . . . . . . .
6.5.2 Description of Hardware and Software . . . . . . . . .
6.6 Over-current Protection Scenario . . . . . . . . . . . . . . . .
6.6.1 Configuring IED RET 670 . . . . . . . . . . . . . . . .
6.6.2 Power System for Steady State Measurements . . . . .
6.6.3 Application Configuration in PCM 600 . . . . . . . . .
6.6.4 Simulation Values at Node 2 . . . . . . . . . . . . . . .
6.6.5 Screenshot of IED RET 670 HMI . . . . . . . . . . . .
6.6.6 Transient State Test and Over-Current Protection . . .
6.6.7 Configuration of Over-Current Protection in PCM 600
6.6.8 Parameter Settings for Over current Protection . . . .
6.6.9 Simulation Values at Node 2 During Fault . . . . . . .
6.6.10 Screenshot of Local HMI of IED RET670 . . . . . . .
6.7 Additional Tests . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.1 Response of MU Under Unsymmetrical Fault . . . . . .
6.7.2 Response of MU Under Harmonic Injection by Source .
6.7.3 Response of MU Under OLTC Operation . . . . . . . .
6.7.4 Simulation Results on Bus 3 and 4 . . . . . . . . . . .
6.8 Transformer Differential Protection Test . . . . . . . . . . . .
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viii
7 Results
7.1 ADC output for Over current Protection . . . . . . . . . . . . . . . .
7.2 ADC Output During Harmonic Injection . . . . . . . . . . . . . . . .
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8 Discussion
82
9 Future Recommendations
9.1 Future work for this thesis . . . . . . . . . . . . . . . . . . . . . . . .
9.2 Future work for the whole project . . . . . . . . . . . . . . . . . . . .
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Bibliography
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A Evaluation Report
1
A.1 Four Steps Phase Overcurrent Protection OC4PTOC with 2nd Harmonics 1
A.2 Two Windings Transformer Differential Protection (T2WPDIF) . . .
7
ix
List of Acronyms
IEC International Electrotechnical Commission
IEEE Institute of Electrical and Electronics Engineers
ABB Asea Brown Boveri
CT Current Transformer
PT Potential Transformer
VT Voltage Transformer
ECT Electronic Current Transformer
EVT Electronic Voltage Transformer
NCIT Non Conventional Instrument Transformer
MU Merging Unit
ADC Analog to Digital Conversion
SAS Substation Automation Systems
HMI Human Machine Interface
IED Intelligent Electronic Device
SNR Signal to Noise Ratio
ENOB Effective Number of Bits
FIR Finite Impulse Response
OSR Oversampling Ratio
SV Sampled Value
GOOSE General Object Oriented Substation Event
OLTC On Load Tap Changer
RAM Random Access Memory
RMS Root Mean Square
BI Binary Input
x
BO Binary Output
BER Bit Error Rate
UDP User Datagram Protocol
FPGA Field Programmable Gate Array
PPS Pulse Per Second
LED Light Emitting Diode
MMS Manufacturing Message Specification
xi
List of Tables
6.1
OC4PTOC parameters . . . . . . . . . . . . . . . . . . . . . . . . . .
71
A.1
A.2
A.3
A.4
A.5
A.6
The map of LED . . . . . . . . . . . . . . . .
OC4PTOC settings for 2nd harmonic restrain
Parameter setting for MU . . . . . . . . . . .
The LED map for T2WPDIF . . . . . . . . .
T2WPDIF settings . . . . . . . . . . . . . . .
The changed parameters for T2WPDIF . . . .
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5
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xii
List of Figures
1.1
Substation Automation With Station and Process Bus . . . . . . . .
3
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Method Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Station Bus and Conventional Wiring to the Process . . . . . . . . .
Station Bus with Ethernet connection to the Process level . . . . . .
Hierarchical Communication Network with Station and Process Bus[1]
Merging Unit defined in IEC 60044-8 . . . . . . . . . . . . . . . . . .
Merging Unit Architecture . . . . . . . . . . . . . . . . . . . . . . . .
Phase Delay in the Signal[2] . . . . . . . . . . . . . . . . . . . . . . .
Design of Merging Unit . . . . . . . . . . . . . . . . . . . . . . . . . .
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3.1
3.2
3.3
3.4
Equivalent Circuit for CT . . . . . . . . .
Equivalent Circuit for VT . . . . . . . . .
Digital Substation Configuration of a Bay
CT/PT Model . . . . . . . . . . . . . . . .
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15
16
4.1
4.2
4.3
ADC flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sampling an analog signal . . . . . . . . . . . . . . . . . . . . . . . .
(a)Spectrum of unsampled waveform (b)Spectrum of sampling function
(c)Spectrum of sampled waveform . . . . . . . . . . . . . . . . . . . .
Aliasing phenomena . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . .
Flash ADC schematic [3] . . . . . . . . . . . . . . . . . . . . . . . .
Priority Encoder SIMULINK model 8-3 bit . . . . . . . . . . . . . . .
Detailed Flash ADC model in SIMULINK . . . . . . . . . . . . . . .
MATLAB/SIMULINK Simscape Toolbox . . . . . . . . . . . . . . .
First order sigma-delta ADC block diagram . . . . . . . . . . . . . .
Under-sampled signal spectrum . . . . . . . . . . . . . . . . . . . . .
Over-sampled signal spectrum . . . . . . . . . . . . . . . . . . . . . .
Code example of a 2-bit A/D converter . . . . . . . . . . . . . . . . .
First order sigma-delta modulator sampled data equivalent block diagram
SNR VS Oversampling ratio for sigma-delta modulators[4] . . . . . .
Frequency Spectrum . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
4.13
4.14
4.15
4.16
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xiii
4.17
4.18
4.19
4.20
4.21
4.22
4.23
4.24
4.25
4.26
4.27
4.28
4.29
Sigma-Delta ADC model in SIMULINK . . .
MATLAB/SIMULINK DSP Toolbox . . . . .
Analog Filter Block Parameter Details . . . .
Integrator Block Parameter Details . . . . . .
Signum Block Parameter Details . . . . . . .
Zero order hold Block Parameter Details . . .
FIR Decimation Block Parameter Details . .
FIR Decimation Block Parameter Details . .
Transport Delay Block Parameter Details . .
Detailed model with explanation . . . . . . .
Simulated Sampled Signal Output . . . . . .
Analog Signal and Simulated Quantized Signal
Final Digital Signal Output . . . . . . . . . .
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5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
5.17
5.18
5.19
5.20
5.21
5.22
5.23
5.24
5.25
Single line diagram of Test System . . . . . . . . . . . . . . . . . .
Three phase Programmable Voltage Source Block . . . . . . . . . .
Three phase Programmable Voltage Source Block Parameter Details
Three phase Two Winding Transformer Block . . . . . . . . . . . .
Three phase Two Winding Advance Parameter Details . . . . . . .
Three phase Two Winding Transformer Parameter Details . . . . .
Three phase Two Winding Transformer Parameter Details . . . . .
Three Phase PI Section Line Block . . . . . . . . . . . . . . . . . .
Three Phase PI Section Line parameter details . . . . . . . . . . . .
Three Phase OLTC Block . . . . . . . . . . . . . . . . . . . . . . .
Three Phase OLTC transformer parameter details . . . . . . . . . .
Three Phase OLTC voltage regulator parameter details . . . . . . .
Three Phase Series RLC Load Block . . . . . . . . . . . . . . . . .
Three Phase Series RLC Load Parameter details . . . . . . . . . . .
Three Phase Fault Block . . . . . . . . . . . . . . . . . . . . . . . .
Three Phase Fault Parameter Details . . . . . . . . . . . . . . . . .
Three Phase VI Measurement Block . . . . . . . . . . . . . . . . . .
Three Phase VI Measurement Parameter Details . . . . . . . . . . .
Discrete Three Phase Sequence Analyser Block . . . . . . . . . . . .
Discrete Three Phase Sequence Analyser Parameter Details . . . . .
Power GUI Block . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power GUI Configuration Settings . . . . . . . . . . . . . . . . . . .
Power GUI Configuration Settings . . . . . . . . . . . . . . . . . . .
Power GUI Analysis Tools . . . . . . . . . . . . . . . . . . . . . . .
Three Phase Power System Modelled in Simulink . . . . . . . . . .
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6.2
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Picture of the test setup for the all-digital over-current protection[5] .
Lab Setup for Soft Merging Unit for Protection Function Testing . .
Lab Setup for Soft Merging Unit for Protection Function Testing . . .
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6.4
6.5
6.6
6.7
6.8
6.9
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6.11
6.12
6.13
6.14
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6.16
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6.18
6.19
Protection Function Testing Scheme . . . . . . . . . . . . . . . . . . .
Protection Function Testing Scheme . . . . . . . . . . . . . . . . . . .
Power System with MUs attached to the Nodes . . . . . . . . . . . .
Application Configuration for Monitoring Function In PCM600 . . . .
Three phase Voltages and Currents at BUS 2 . . . . . . . . . . . . .
Steady State Values . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power System with Three Phase Short Circuit Fault . . . . . . . . .
Four Step Over-current Protection Block OC4PTOC . . . . . . . . .
Three Phase Voltages and Currents at BUS 2 . . . . . . . . . . . . .
Transient State During Three Phase Short Circuit . . . . . . . . . . .
Three Phase Voltages and Currents at BUS 2 During Unsymmetrical
Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Test System for Harmonic Injection . . . . . . . . . . . . . . . . . . .
Three Phase Voltages and Currents at BUS 2 With Harmonic Injection
Voltage Regulation Monitoring Test System . . . . . . . . . . . . . .
Voltage Regulation on Bus 3 and 4 . . . . . . . . . . . . . . . . . . .
Tap Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1
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7.6
ADC
ADC
ADC
ADC
ADC
ADC
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9.1
Interoperability Representation at Process Level . . . . . . . . . . . .
85
Output
Output
Output
Output
Output
Output
of
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Voltage During Steady State . . . .
Current During Steady State . . .
Voltage During Transient State . .
Current During Transient State . .
Voltage During Harmonic Injection
Current During Harmonic Injection
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A.1 The Simulink model of the testing . . . . . . . . . . . . . . .
A.2 The scheme of the testing . . . . . . . . . . . . . . . . . . .
A.3 The application configuration in PCM 600 . . . . . . . . . .
A.4 The results of OC4PTOC with 2nd harmonic . . . . . . . . .
A.5 Schematic of two windings transformer differential protection
A.6 The transformer differential protection provided in RET 670
A.7 The Simulink model for differential protection . . . . . . . .
A.8 The waveforms of primary and secondary sides . . . . . . . .
A.9 The Wireshark capture of sending SVs for two MUs . . . . .
A.10 Application configuration for T2WPDIF . . . . . . . . . . .
A.11 The trips of T2WPDIF . . . . . . . . . . . . . . . . . . . . .
A.12 The trips of T2WPDIF . . . . . . . . . . . . . . . . . . . . .
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1
Chapter 1
Introduction
1.1
Introduction
Generation, transmission, distribution are the main parts of a power system. The
safe operation of power system is vital for the clients satisfaction. For this satisfaction power system protection is an indispensable event for the safety. In the history
different eras have different kind of protection equipment deployed for the protection.
If we talk about the substation automation electromechanical relays were the first to
start with in protection field. As time goes on development had been made towards
the more reliable protection devices. Then the solid state relays came into the application of protection and they were much better than the electromechanical relays in
the sense of their operation functionalities. Furthermore, there came a revolution in
the field of electronics and microprocessor based relays came into being as the state
of art. These microprocessor based relays have lots of advance operating principles
by use of which the highest level of substation automation can be achieved for the
more reliable energy transfer to the customers. The continuous advancements and
reduced costs have made the microprocessor relays the solution of choice. Since the
information processed digitally, a large number of protection functions can be built
on one device [6]. International Electrotechnical Commission (IEC) standard 61850
suggests the Ethernet based communication in the substation automation field. The
successful deployment of this standard in the substation automation will provide both
reliability and efficient cost reduction. In order to the successful deployment of the
process bus and IEC 61850-9-2 sampled measured values lots of time critical tests
have to be made. This report addresses different aspects of the Merging Unit and
the standard IEC 61850-9-2 [7]. As the IEC 61850 communication standard has been
widely accepted and applied in the substation automation it is important that the
testing tools keep up with these developments [8]. Besides all these the Merging Unit
will also be discussed in detail in the report as it is the important part of interfacing
between the high voltages of transmission and the secondary protective devices.
2
1.2
Project Goals and Objectives
The main goal is to develop a light weight Merging Unit in MATLAB/SIMULINK
environment. The objective is to have a soft MU which gives us the opportunity
to make test and run simulations on an ordinary lab computer as compared to any
vendor product which demands a lot of security parameters and license agreements
with a high cost.The final goal of this project is the product development of MU
according to the IEC 61850 standard. Another objective of this project is to develop
a test bed for the testing of different protection functions under different constraints.
1.3
Scope of the Project
The scope of the this Part-A of the project is to parametrize the current and voltage
transformer models developed in the Simulink. The scope also covers the modelling
of ADC’s and multi-bus power system in Simulink. Therefore the Part-A and PartB[9]are integrated and the final developed product is achieved. The scope of this
project is also to provide a test bed for the testing of different protection functions
like over current and differential protections.
1.4
Motivation
• Light Weight 9-2 testing environment
• Quick Configuration
• Demonstration for customers
• Testing of different types of protection Functions
• Interoperability tests for MU and IEDs
The figure 1.1 is the illustration of the whole Project. The red encircled portion of
the figure 1.1 is the main task of research work where MU is an interface between
Instrument transformers and the process bus, and process bus is the interface between
MU and IED.
3
Figure 1.1: Substation Automation With Station and Process Bus
1.5
General Limitations
As a general rule,the time factor, cost, availability of technical apparatus bring constraints to each project which somehow affects the quality of research work. Therefore
the constraints make the expectations of the work more reasonable and close to final
results and findings.
Technical Limitations
This constraint includes the unavailability of real time simulator which restrict this
work to off-line simulations. The unavailability of IEC 61850-9-2 process bus on the
AREVA and SIEMENS could not allow us to perform interoperability tests.
Time Constraint
The time factor plays an important role in any project. Due to this constraint we
could not able to develop the synchronization function. Even though it was not in
the tasks to compete in priority list but it could be the interesting work to add up to
the research work.
1.6
Outline of Report
Chapter 1 summarizes with the introduction and motivation behind this study work.
Chapter 2 provides the purpose of research, literature review and the selected research
4
methodology. Chapter 3 covers the basic theory and modelling of the CT/PT. Chapter 4 covers the theoretical background of signal processing and explains the selection
and modelling of the analog to digital conversion. Chapter 5 presents the modelling
of a power system required for the analysis. Chapter 6 gives the complete test system
evaluation based on different protection functions. Chapter 7 presents the results of
the designed ADC.Chapter 8 is included to present discussion about whole project
and chapter 9 gives future recommendations about this thesis work.
5
Chapter 2
Methodology
This chapter comprises the research methodology for this thesis work. Firstly, an
understanding of the substation automation according to the IEC 61850 is done.
Then the understanding of the latest research going on is also needs to be taken into
account. This was done by reading related literature, reports and previous work.
When a certain level of understanding and knowledge had been achieved then its
time to start working on this research problem.
2.1
Research Method
The following figure 2.1 explains the method used for the research in this study work.
Figure 2.1: Method Steps
6
2.2
IEC 61850 Standard for Substation Protection and Automation
The success of a substation protection and automation system depends on the effectiveness of the communication link to the different devices within an electric power
substation. The important challenge for the substation automation design engineers
is to provide interoperability among devices from different vendors. A large amount
of investment is required to develop costly and complicated protocols and interfaces
for the communication among all the devices in the substation. In order to address
this matter the International Electro technical Commission (IEC) Technical Committee (TC-57) has published IEC 61850 standard titled ”Communication Networks
and Systems in Substation” in 2003[10]. IEC 61850 is the new standard for communication networks and systems in the substations.The transmission and distribution
substation of the future is currently influenced by the future standard IEC 61850.
The standard gives the communication mappings for all the primary and secondary
equipment in the substation automation. This standard will help in eliminating the
most of copper wiring in the substation. These copper wires are used to connect the
process equipment to the bay level. These wires contain analog signals from switchyard, binary status and command signals. This will be the basis for new applications
supporting not only the operation but also the maintenance of the substation [11].
2.3
Conventional Substation Architecture
The conventional substation architecture is shown in the figure below[11].
Figure 2.2: Station Bus and Conventional Wiring to the Process
Figure 2.2 is self explanatory about the architecture of a conventional substation. The conventional transformers are connected through a lot of copper wires to
make connections to the protection system. This is just for the case of one bay. One
7
can imagine easily the complexity level of connections when there are hundreds of
bays to protect. The same architecture is good enough for the IEC 61850 to implement its standards. The first step is to remove the conventional transformers and use
non-conventional transformers and conventional switchgear which will be connected
through serial point-to-point connections according to the standard. In this thesis
the non-conventional transformers are modelled and then IEC 61850-9-2 interface is
implemented. The architecture for IEC 61850 is also given in the figure 2.3 below.
Figure 2.3: Station Bus with Ethernet connection to the Process level
2.4
Digital Substation
The future substations are the digital substations with IEC 61850 implementation.
Digital substations comprise of intelligent primary devices and networking IEDs to
achieve information sharing and inter-operability between different vendor products
based on IEC 61850 protocols e.g MMS, GOOSE and SV. As compared with the
conventional substations, communication interfaces and protocols are different at the
bay level and the station level. However the major difference between the two is the
process bus implemented in the digital substation. The digital substation includes
intelligent primary devices,merging units and optic fiber connections. The fiber connections replace conventional CT/VT, primary devices and conventional cable wiring.
Digital substations has introduced GOOSE scheme which is the replacement of traditional binary inputs and binary outputs. The digital BI and BO are configurable and
can be delivered to Ethernet switch. This helps in reducing the wiring in the substation. The use of the sampled value makes the current/voltage sampling at primary
side easier and more reliable. The voltage and current signals are captured at the
primary side, converted to the optic signals and then transferred to the protection and
control devices via optical fiber [1]. The pictorial comparison between conventional
and digital substation is given in the figure 2.4.
8
Figure 2.4: Hierarchical Communication Network with Station and Process Bus[1]
2.5
Merging Unit
It is an important intelligent electronic device in digital substation. It is the important
part to exchange the messages between ECT/EVT (electronic current and electronic
voltage transformers) process level and the secondary equipment (bay level) of the
substation automation. The function of merging unit is to collect multichannel digital
signals output by electronic current and electronic voltage transformers synchronously
and transmit these signals with the protocol of IEC 61850 to protective devices and
measure control devices [12].
A lot of research is going on by different vendors and researchers on this intelligent device which is the interface between the conventional and non conventional
voltage and current transformers and the process bus. The overall interface is represented in the figure 2.5 which is defined in the IEC 60044-8.
Figure 2.5: Merging Unit defined in IEC 60044-8
9
2.6
Merging Unit Related Work
The suggested design of the Merging Unit is described to have an insight of the
components needed to design a merging unit. The incoming signals are from the
instrument transformers which are fed into the MU. The MU architecture contains
first block with the analog filtering circuits first to process on analog signals to decide
the cut off frequencies for the incoming signals. The second block contains the ADC
to convert analog to digital converter for analog signals conversion to digital form.
The third block contains the digital signal processing block which is used to remove
the noise and to perform digital filtering on the signals. The signal after passing
through all these processing blocks experienced a delay in its phase. This delay can
be compensated by using the synchronization pulse. If the synchronization pulse is
not used then there will always be a delay in the phase of the incoming signal. This
is the one of the related work which gives much clearer insight into the design of the
merging unit. This idea will also be utilized in the design of soft merging unit at ICS
[13] [2]. The figure2.6 explains the idea of merging unit internal components.
Figure 2.6: Merging Unit Architecture
The delay in the phase can be realized in the figure2.7.
Figure 2.7: Phase Delay in the Signal[2]
10
2.7
Design of Merging Unit
According to the recent research works different researchers suggest different designs
for the Merging Unit. The research work in [12] is taken as reference for this thesis
work. The design of MU is comprises of three major parts.
1. Data Acquisition and Processing
2. Packet Transmission
3. Synchronizing Function
The part of Data Acquisition and Processing is done in this Part-A of the Project.
The Part-B [9] of the Project is responsible for the Packet Transmission part. The
third part is Synchronization function and it is not completed for now due to time
constraint.
Figure 2.8: Design of Merging Unit
2.7.1
Data Acquisition and Processing Function
The function of this module is to connect the CT/VT to the secondary equipment.
The merging unit must have the ability to acquire and merge the sampled values
from multichannel electronic transducers and the analog values from the conventional
instrument transformers synchronously . Then the ADC’s convert the incoming 4V
and 4I into the digitized form with a output rate of 4 KHz according to the standard
IEC 61850. Afterwards the packet transmission part does the rest and put this data
to the Ethernet port by making the packets of the digitized data according to the
IEC 61850-9-2 standard.
11
2.8
Summary
These above reference points which are explained thoroughly would be the basic building blocks for the development of merging unit. The merging unit which is developed
in the reference [12] provided above is in the FPGA but the merging unit for this
research work would be developed in the MATLAB/SIMULINK.The models of merging unit and the process bus development will be connected as an interface between
the instrument transformers and the intelligent electronic devices and different kinds
of tests like accuracy of merging unit, correctness, speed and the limitations will be
discussed and a useful finding out of this project will be presented.
12
Chapter 3
Models of CT/PT
3.1
Introduction
This chapter starts with theoretical background about conventional instrument transformers and non-conventional instrument transformers. After the theoretical background the developed models are presented which are continuously providing the
scaled down measured value for currents and voltages. These models are not the real
models for CT/PT but give the ideal realization of CT/PT.
3.2
Instrument Transformers
In order to develop an interface between secondary equipment and process bus another interface between high tension side and merging unit is required. This interface
will transform high voltages and currents to low value voltages and currents. Instrument transformers consists of current transformers and voltage transformers. The
purpose of instrument transformers is to convert the high voltages and currents to
the low values of currents and voltages in a power system. The rapid and reliable
operation of the power system protection and control is dependent on reasonably accurate measurements of electrical signals associated with controlled elements of the
power system. The values of currents and voltages from instrument transformers
during large and small disturbances in the power system are of great importance
with respect to their accuracy of measurement [14]. The protection systems are totally dependent on the measurements from the instrument transformers, so accurate
modelling of CT/PT is of great importance.
3.3
Conventional Instrument Transformers VS NCIT
The current transformers are the key components as they produce the access to the
high currents in a power system through reduced replica on the secondary side. It
enables the protection function to detect the faults within time limits and isolate
13
them. Therefore the protection devices are totally dependent on the measurement
values coming from the instrument transformers. Unfortunately there is a problem of
saturation in the CT core. The CT cores have the problem of non linear excitation
when exposed to high fault currents. Therefore the non linear excitation forces the non
linear saturation in the core material of the current transformer. When the non linear
saturation phenomena occurs the measured value of current on the secondary side is
no more according to the turns ratio which leads to the triggering of wrong event [15].
On the other hand the new replacements for the conventional instrument transformers
is the non conventional instrument transformers also known as electronic current and
voltage transformers.The ECT plays an important part in the smart substation,it uses
the electronic technology to measure the voltage and current of power system and
supplies these data to relay protection and control system. Compared with traditional
electromagnetic current transformer, the ECT has many advantages, such as simple
insulation structure, immunity to electromagnetic interference, no saturation effect,
no flammable materials such as oil [16].
3.4
Conventional Instrument Transformers
Conventional instrument transformers are also known as the electromagnetic transformers. The main purpose of the instrument current transformer is to produce a proportional secondary current from the incoming primary current.Current transformers
are commonly used in metering and protective relaying in the electrical power industry. They facilitate the safe measurement of large current from high tension lines.The
primary winding is connected in series with the source current to be measured. The
secondary winding is normally connected to a meter, relay, or a burden resistor to
develop a low level voltage that is amplified for control purpose. The basic theory
of a current transformer is the same as for any other iron-core type. The primary
is normally a single turn while the secondary has a large number of turns, normally
a turn ratio of 100 or more is common. A high turns ratio generally causes a high
leakage inductances. This causes the secondary output to be less than the predicted
from the primary voltage times the turns ratio. Due to these leakages phenomena the
design of CT is need to be considered very carefully [17]. The circuit diagram of CT
is shown in the figure3.1.
Figure 3.1: Equivalent Circuit for CT
14
The inductive voltage transformers are the dominant sources of the voltage
output signals for measurement and protective devices and relays in medium and high
voltage networks due to their simple construction and low costs.The main purpose
of the instrument voltage transformer is to produce a proportional secondary voltage
from the incoming primary voltage. The secondary winding consists from one to three
windings that are used for measuring, protection purposes or earth fault indication.
Primary winding consists of copper wire usually the conductor of high voltage coming
from transmission line [18]. The equivalent circuit for the voltage transformer is shown
in the figure 3.2.
Figure 3.2: Equivalent Circuit for VT
3.5
Non-Conventional Instrument Transformers
Nowadays NCIT have achieved high performance regarding substation automation.
Due to latest developments in the field of electronics and information technology
substations are becoming more and more compact. The data transmission is becoming digital upto process level. NCIT with compact dimensions and digital outputs
have found a suitable place in the modern digital substation. The performance of
NCIT satisfies the protection and metering requirements under most worst conditions of temperature, mechanical vibrations and electromagnetic compatibility [19].
Non-conventional instrument transformers are also known as electronic current and
voltage transformers. The ECTs and EVTs play a sensing and digitizing role for
current and voltage information with the processing capabilities of digital electronics.
The designs of ECTs and EVTs are based on IEC 60044-8 and IEC 60044-7 respectively. The digital output interface of NCIT is based on IEC 61850-9. The sensed
current and voltage measurements are transmitted to them as optical digital signals.
Therefore the primary equipment and substation system wiring can be simplified due
to extensive use of optical fiber for communication of current and voltage information
and operating commands[20].
3.5.1
General Configuration of ECTs and EVTs
The ECT is based on the principle of a Rogowski coil by taking into account of
saturation free characteristics and economical efficiency. As for the voltage detection
15
sensor of EVT, a capacitive voltage divider of high reliability and simple insulated
construction was applied. The sensing units are arranged near the rogowski coil
and the capacitive voltage divider to each bay and one MU is provided to get the
secondary information. The interface between sensing unit and MU is provided by
the optical fiber connection. The MU is also connected to the process bus via optical
fiber. Redundancy is provided for the sake of reliability of the system. The figure 3.3
gives the clearer idea about it [20].
Figure 3.3: Digital Substation Configuration of a Bay
3.6
Simulink Model of CT/VT
The voltages and currents on the transmission level are very high. These voltages are
stepped down by the instrument transformers for monitoring and protection purposes.
The current and voltage transformers usually transform the high tension side to (0-1
A)or(0-5 A) and (0-110 V) depending on the measuring systems configuration. In
this study work the voltages and currents are stepped down to (0-110 V) and (0-1 A).
After stepping down the voltages and currents the measurements are further scaled
down for the ADC’s to work properly on these measurements. The Simulink model
used for both CT/PT are given in the figure 3.4.
16
Figure 3.4: CT/PT Model
In the figure3.4 there are two gain blocks with one saturation block.
The first gain block is to provide step down ratio to the incoming voltages and
currents from the main transmission line. After the step down block the saturation
block is connected to provide an upper and lower limit to the measured values. The
purpose of putting saturation limits is to block the extra high voltages and currents
during any abnormal or fault condition. At the end the second gain block is connected
which is mainly used for the further scaling down of the input voltages and currents
if required. The model is flexible for any value of the input measurements and can
be parametrize according to the given or required conditions. This final scaled down
output is ready for the ADC as an AC input signal to convert it to digital signal.
17
Chapter 4
Modelling Of Analog To Digital
Converter In SIMULINK
4.1
Background
The modeling of MU (merging unit) requires an important component to model is the
analog to digital converter. The functionality of this converter is to take in the analog
values from the conventional instrument transformers CT/PT and convert them to
the high resolution digital values. According to the IEC 61850 standard the merging
unit will take three phases and neutral current and three phases and neutral voltage
from the conventional instrument transformers. These current and voltage signals
are converted to digital form and after some signal processing are then transferred
to the Ethernet port to the process bus. The two kinds of output resolutions are
required at the process bus for the IEDs. The 16-bit resolution digital signals are
required for the protection functions to work properly and 14-bit resolution signals
are required for the monitoring purposes. The achievements of these two kinds of
signals are explained in the following section.
4.1.1
Analog To Digital Conversion
Analog-to-digital and digital-to-analog converters provide the interface between the
analog signal domain and the binary digital computational domain. The analog signals which are converted to the digital can originate from many types of transducers
that convert physical phenomenon, temperature, pressure, position, motion, sound,
images to electrical signals. The electrical signals from an energized transducer are
either an analog current or voltage whose value is proportional to the physical phenomena being measured [21].
In the development of our application the three phase currents and three phase voltages are taken as the inputs for the analog to digital conversions from the instrument
transformers.
18
4.1.2
Steps From Analog To Digital Conversion
Achieving digital signals from analog signals include the following main steps as shown
in the figure 4.1.
1. Input signal conditioning
2. Sampling
3. Quantization
4. Decimation
Figure 4.1: ADC flow diagram
4.1.3
Analog Input Signals
Analog refers to the physical quantities that vary continuously instead of discretely.
Physical phenomena usually involve analog signals e.g. temperature, pressure, speed,
position, altitude, voltage, current, etc. Microprocessors work with digital quantities.
Therefore for a digital system to interact with an analog system, conversion between
analog and digital values is desired [22].
The signals used for the application will be the current and voltage signals of (01Amp) and (0-110Volts) from the instrument transformers with 50Hz frequency.
4.1.4
Sampling
This is the important step in ADC in order to digitize the signal to be able to convert
it into digital form. The signals we use in the real world, such as our voices, are
called ”analog” signals. To process these signals in computers, we need to convert
the signals to ”digital” form. While an analog signal is continuous in both time and
amplitude, a digital signal is discrete in both time and amplitude. To convert a signal
from continuous time to discrete time, a process called sampling is used [23]. The
figure4.2 is representing the sampling process.
19
Figure 4.2: Sampling an analog signal
The value of the signal is measured at certain intervals in time. Each measurement is referred to as a sample. When the continuous analog signal is sampled at a
frequency F, the resulting discrete signal has more frequency components than did
the analog signal. To be precise, the frequency components of the analog signal are
repeated at the sample rate. That is, in the discrete frequency response they are seen
at their original position, and are also seen centered around +/- F, and around +/2F, etc. If the signal contains high frequency components, we will need to sample at
a higher rate to avoid losing information that is in the signal. In general, to preserve
the full information in the signal, it is necessary to sample at twice the maximum
frequency of the signal. This is known as the Nyquist rate. The frequency spectrum
of a signal sampled at greater than Nyquist rate is shown in the figure 4.3 [23].
Figure 4.3: (a)Spectrum of unsampled waveform (b)Spectrum of sampling function
(c)Spectrum of sampled waveform
The Sampling Theorem states that a signal can be exactly reproduced if it is
sampled at a frequency where F is greater than twice the maximum frequency in the
signal. If the sampling law theorem is not obeyed then if the signal is converted back
into a continuous time signal, it will exhibit a phenomenon called aliasing.
20
4.1.5
Aliasing
Aliasing is the presence of unwanted components in the reconstructed signal. These
components were not present when the original signal was sampled. In addition,
some of the frequencies in the original signal may be lost in the reconstructed signal.
Aliasing occurs because signal frequencies can overlap if the sampling frequency is too
low. Sometimes the maximum frequencies components of a signal are simply noise,
or do not contain useful information. To prevent aliasing of these frequencies, we can
filter out these components before sampling the signal. Because we are filtering out
high frequency components and letting lower frequency components through, this is
known as low-pass filtering [23]. The figure 4.4 shows aliasing phenomena.
Figure 4.4: Aliasing phenomena
4.2
Types Of Analog to Digital Conversions
There are different methods for analog to digital conversion. The choice of method
is fairly dependent on the type of application one needs. Following are some types of
analog to digital converters [22].
1. Flash ADC
2. Dual Slope
3. Successive approximation
4. Sigma delta ADC
The above are the different techniques to get the digitized form of the respective
analog signal. Every technique has different advantages and disadvantages in the
procedure of their selection criteria for a specific application.
4.2.1
Selection Of ADC Type
While selecting a technique for the analog to digital conversion there are different
parameters which are necessary to look at before making the final selection of the
21
converter type for the specific application. According to the specifications of my
application I need to convert an analog signal of 0-1(ampere) and 0-110(volts) signal
with input frequency of 50 Hz to digital form with a high resolution of 14-bit to 16-bit.
4.3
Principle Of Flash ADC
The basic principle of Flash ADC is illustrated for the sake of understanding, that
how it converts an incoming analog signal to the digital form.
4.3.1
Voltage Comparator
In electronics, a comparator is a device which compares two voltages or currents and
switches its output to indicate which is larger. More generally, the term is also used
to refer to a device that compares two items of data. Output voltage will switch
whenever the input voltage (at the inverting input) reaches the reference voltage Vref
(at the non-inverting input). The figure 4.5 shows the schematic for the comparator.
When a comparator performs the function of telling if an input voltage is above
or below a given threshold, it is essentially performing a 1-bit quantization. This
function is used in nearly all analog to digital converters (such as flash, pipeline,
successive approximation, delta-sigma modulation, folding, interpolating, dual-slope
and others) in combination with other devices to achieve a multi-bit quantization
[24].
Figure 4.5: Voltage Comparator
First of all the basic 3-bit resolution is achieved by using the spontaneous
method of analog to digital conversion. The Flash ADC is modeled in the SIMULINK.
4.3.2
Flash ADC Modelling
This is the fastest and spontaneous way of converting the analog signals to digital
signals. It uses the comparator and a bunch of resistors in a characterized way to
perform the desired operation. The Flash ADC is modeled in the SIMULINK using
SimScape and SimPowerSystems libraries. The analog signals from the instrument
transformers are fed to the Flash ADC which are converted to the digital form. After
22
conversion to digital form they are converted to the binary form by applying digital
signals to the priority encoder which actually gives the output into 3-bit stream form
according to the respective active input at that instant of time.
Advantages
1. Flash ADC is very fast and spontaneous.
2. It is simple in order to understand.
Disadvantages
1. It requires a large number of comparators compared to other ADCs, as the
precision increases.
2. Due to the increase in the circuitry components more power is dissipated.
The schematic of Flash ADC is given in the figure 4.6.
Figure 4.6: Flash ADC schematic [3]
4.3.3
Priority Encoder
A priority encoder is a circuit or algorithm that compresses multiple binary inputs
into a smaller number of outputs. The output of a priority encoder is the binary
representation of the ordinal number starting from zero of the most significant input
bit. If two or more inputs are given at the same time, the input having the highest
priority will take precedence [22]. In this case the 3-bit binary stream is the output
from the priority encoder representing the decimal number from 0 to 7. The logical
circuit for the 8-bit to 3-bit encoder is given in figure 4.7.
23
Figure 4.7: Priority Encoder SIMULINK model 8-3 bit
The detailed SIMULINK design model for Flash ADC is given in figure 4.8.
Figure 4.8: Detailed Flash ADC model in SIMULINK
The different blocks and the internal settings for them are described below.
24
MATLAB/SIMULINK Simscape1 toolbox is mainly used to implement this 3-bit
Flash ADC. The main block comprises of Voltage Comparators, Resistors, Physical
signal to Simulink, Logical gates and Voltage sensor.
Figure 4.9: MATLAB/SIMULINK Simscape Toolbox
Description Of SIMULINK Blocks Implemented
1. The PS-Simulink converter block converts a physical signal to a simulink output
signal. This block is used to connect the outputs of a physical network diagram
to Simulink scopes or other Simulink blocks.
2. Each topologically distinct Simscape block diagram requires exactly one Solver
Configuration block to be connected to it. Each physical network represented
by a connected Simscape block diagram requires solver settings information for
simulation. The Solver Configuration block specifies the solver parameters that
the model needs before the simulation is begin.
3. Comparator block is from the integrated circuit library of Simscape toolbox.
This block models the gate output as a voltage source driving a series resistor
and a capacitor that connects to ground. The block models differential inputs
electrically as having infinite resistance and a finite or zero capacitance. If the
difference in the inputs is greater than the input threshold voltage, then the
output is equal to the High level output voltage. Otherwise, the output is equal
to the Low level output voltage.
4. The Voltage Sensor block represents an ideal voltage sensor, that is, a device
that converts voltage measured between two points of an electrical circuit into
a physical signal proportional to the voltage.
1
MATLAB SIMULINK Library
25
5. The last three blocks are logical AND, OR, and NOT gates which behave according to their logical operation defined [25].
4.4
Sigma-Delta Analog To Digital Converter
Sigma-Delta ADCs have been receiving increased attention as an alternative to the
conventional ADCs. The conventional ADCs use precision elements to maintain resolution and accuracy. Whereas Sigma-Delta ADC produces conversions with just
1-bit of resolution at very high sampling rate. Also, Delta-Sigma converters may
be superior for data acquisition because of good overall noise performance[26]. The
Delta-Sigma converter consists of two main components, a Delta-Sigma modulator
and a digital filter. The modulator part consists of an analog filter and a coarse
quantizer enclosed in a feedback loop[27]. The feedback loop and the filter attenuate
the quantization noise at low frequencies while emphasizing the high-frequency noise
(noise shaping). With noise shaping, the quantization noise effects in the band of
interest can be dramatically reduced. The very high sampling rate and noise shaping allow the 1-bit Delta-Sigma to have the same performance as 16-bits or higher
of quantization[28]. The literature study and the requirement of the MU product
development lead to this type of ADC which is quite famous for the high resolution
and as noise shaping modulator.
4.4.1
Why Sigma-Delta ADC?
The sigma-delta ADC is the converter of choice for modern voice band, audio, and
high resolution precision in industrial measurement applications. The digital architecture of sigma-delta is suited for modern fine-line CMOS processes, thereby allowing
easy addition of digital functionality without significantly increasing the cost. The
fundamental concepts of oversampling, quantization noise, digital filtering, and decimation will be discussed later in the chapter [29].In the application development for
this thesis work first order sigma-delta modulator is used. The input signal frequency
of 50 Hz is oversampled to a rate of much larger than the Nyquist rate to achieve the
desired resolution. Oversampling is not the only way to get higher resolution; instead
the decimation is also performed on the digital signal to get the desired resolution of
16-bit and output of 4 kHz data rate.
4.4.2
Sigma-Delta Modulator Working
Figure 4.10 shows the first order sigma delta modulator which is used in this application development of MU. The input signal X comes into the modulator via summing
junction. It then passes through the integrator which feeds a comparator that acts
as a 1-bit quantizer. The comparator output is fed back to the summing junction via
26
1-bit digital to analog converter. It also passes through the digital filter and emerges
at the output of the digital filter [4].
Figure 4.10: First order sigma-delta ADC block diagram
The signal theory concepts will be described below before going deep into the
sigma-delta ADC.
4.4.3
Signal Sampling
The sampling theorem states that the sampling frequency of a signal must be at least
twice the signal frequency in order to recover the sampled signal without distortion.
When a signal is sampled its input spectrum is copied and mirrored at multiples of
the sampling frequency fs. The figure 4.11 depicts the spectrum of a signal when the
sampling theorem is violated [29].
Figure 4.11: Under-sampled signal spectrum
In the figure 4.11 the sampling frequency is less than the twice of input frequency. The shaded area on the plot shows what is commonly referred to as aliasing.
In figure 4.12 shows the spectrum of an oversampled signal. The oversampling process
puts the entire input bandwidth at less than fs/2 and avoids the aliasing trap [4].
27
Figure 4.12: Over-sampled signal spectrum
The one reason of using this technique in our product development is its oversampling techniques which helps in avoiding the aliasing effect and also gives more
relaxation in the selection of analog and digital anti-aliasing filters.
4.4.4
Quantization Noise
Quantization noise (or quantization error) is one limiting factor for the dynamic range
of an ADC. This error is actually the round-off error that occurs when an analog signal
is quantized. For example, Figure 13 shows the output codes and corresponding input
voltages for a 2-bit A/D converter with a 3V full scale value. The figure shows that
input values of 0V, 1V, 2V, and 3V correspond to digital output codes of 00, 01, 10,
and 11 respectively. If an input of 1.75V is applied to this converter, the resulting
output code would be 10 which correspond to a 2V input. The 0.25V error (2V 1.75V) that occurs during the quantization process is called the quantization error.
Assuming the quantization error is random, which is normally true, the quantization
error can be treated as random or white noise. Therefore, the quantization noise
power and RMS quantization voltage for an A/D converter are given by the following
equations [4].
Z q
q2
1 2 2
2
e de =
V2
(4.1)
eRM S =
q −q
12
2
q
eRM S = √
(4.2)
12
A quantized signal sampled at frequency fs has all of its noise power folded into the
Figure 4.13: Code example of a 2-bit A/D converter
28
frequency band of 0 ≤ f ≤ fs /2. Assuming the noise is random, the spectral density
of the noise is given by:
E(f ) = eRM S
2
fs
12
V
√
Hz
(4.3)
By squaring above equation and integrating it the noise power over the band of
interest is given by:
2fo
2
2
no = eRM S
V2
(4.4)
fs
1
2fo 2
no = eRM S
V
(4.5)
fs
Where no is the in-band quantization noise, fo is the input signal bandwidth, and
fs is the sampling frequency. The quantity fs /2fo is generally referred to as the
oversampling ratio or OSR. It is important to note that the oversampling reduces the
in-band quantization noise by the square root of the OSR [4].
4.4.5
Sigma-Delta Modulator Quantization Noise
The results of the above sampling and noise theory can now be used to show how
a sigma-delta modulator shapes quantization noise. The sampled data equivalent
block diagram of the first order sigma delta modulator is shown in the figure 4.14.
The difference equation for the output of the modulator is given below and e is the
quantization noise.
Yi = Xi−1 + (ei − ei−1 )
(4.6)
Figure 4.14: First order sigma-delta modulator sampled data equivalent block diagram
Assuming the input signal is active enough to consider the error as white noise,
the spectral density of the noise can be expressed as given below in mathematical form
29
[4].
N (f ) = E(f )|1 − e
−jω
fs
| = 2eRM S
2
fs
12
sin
ω
2fs
V
√
Hz
The noise power in the bandwidth of interest is given by
π 2 2fo
2
2
no = eRM S
V2
3
fs
(4.7)
(4.8)
Therefore the generalized formula for the Mth order modulator is provided below.
no = eRM S
πM
√
2M + 1
2fo
fs
M + 21
V
(4.9)
If the sampling frequency is doubled the in-band quantization noise will be decreased
by 3(2M+1) dB.
4.4.6
Order Of Modulator And Quantization Noise
As the modulator order is increased from first order to second order the quantization
noise is reduced. Therefore by increasing the order of the sigma delta modulator the
noise can be reduced but at the same time the greater the order of modulator more
unstable the modulator will be. There will be a tradeoff on the order of the modulator
to work it in the stable region. The figure 4.15 showS the relationship between sigma
delta modulator order and quantization noise [4].
Figure 4.15: SNR VS Oversampling ratio for sigma-delta modulators[4]
The first order sigma-delta ADC modulator model is developed and used in
the development of merging unit for this thesis work.
30
4.4.7
SNR Of Sigma-Delta ADC
Signal to noise ratio plays an important role in the strength of the signal to be
measured. The resolution for the protection signal according to standard is 16-bit.In
order to get the 16-bit resolution the SNR of the signal must be greater than 90 dB.
The SNR of the sigma-delta ADC is calculated by using the following equation[30].
fs
(4.10)
SN R = 6.02N + 1.76 + 10log10
2fo
Where N is the number of bits, fs is the sampling frequency and fo is the frequency
of the input signal either current or voltage. According to our requirements the
value of N=16, fs=64 KHz and fo=50 Hz.By putting the values of known variables
in equation (10) the SNR theoretically calculated value is 126.142 dB. Therefore
theoretical value is clearly greater than 90 dB which gives us the output bit resolution
confirmation of 16-bits. The simulated value is calculated in MATLAB and the
graphical representation of SNR and frequency is given in the figure below.
Figure 4.16: Frequency Spectrum
From the figure 4.16 it is clear that the simulated SNR value is a little smaller
than the theoretical value. Even then simulated value is much greater than 90 dB,
which is still approving the requirements needed in the signal strength. When we have
the SNR the term known as effective number of bits (ENOB) can also be calculated
with the following equation.
SN R − 1.76
EN OB =
(4.11)
6.02
31
4.5
Complete SIMULINK Model Of Sigma-Delta ADC
The detailed sigma delta model of ADC developed in SIMULINK is given in figure
4.17 and explained under.
Figure 4.17: Sigma-Delta ADC model in SIMULINK
In SIMULINK the DSP2 System Toolbox is used in the modelling of sigmadelta ADC. The overall blocks which are used are given in the figure 4.18. The main
signal processing blocks are from the DSP Toolbox which is related to the analog
signal processing, sampling, digital signal processing and digital filtering along with
down sampling.
2
MATLAB/SIMULINK Library
32
Figure 4.18: MATLAB/SIMULINK DSP Toolbox
4.5.1
Analog Filter Design Block
The block for analog filter design is given above in the figure16. In this design the
analog filter which is designed is the Butterworth filter used for the analog signal
processing on the incoming current or voltage signal. This filter is used to protect
aliasing in the frequency band of signals.
Details Of Parameters
The details of the analog filter design demands the following values from the user.
33
Figure 4.19: Analog Filter Block Parameter Details
4.5.2
Integrator Block
The block of integrator is shown above in the figure16. The function of this block is
to take the integral of the incoming input.
Details Of Parameters
The detail settings of this block are given below.
Figure 4.20: Integrator Block Parameter Details
34
4.5.3
Signum Block
This block is in the Math Operations library of SIMULINK. It indicates the sign of
the input signal. Here it is used as a1-bit quantizer for the quantization process in
the analog to digital conversion.
Details Of Parameters
The detail settings of this block are given below.
Figure 4.21: Signum Block Parameter Details
This block function is to give a positive 1 if the input is positive and a negative
1 if input is negative and zero if the input is zero.
4.5.4
Zero Order Hold Block
This function block is in the SIMULINK/DISCRETE Library and is shown in the
figure16. It implements a zero order hold of one sample period. In simple words it
converts the continuous time signal to discrete time signal.
Details Of Parameters
Parameter details are given in detail as under.
35
Figure 4.22: Zero order hold Block Parameter Details
4.5.5
FIR Decimation Block
This block is in the DSP Systems Toolbox in Filtering/Multi-rate Filters Library.
The function of this block is to apply digital filtering and down sample the input
digital signal to the desired rate.
Details Of Parameters
Figure 4.23: FIR Decimation Block Parameter Details
36
Figure 4.24: FIR Decimation Block Parameter Details
4.5.6
Transport Delay Block
This block is used to delay the input signal to a certain value. The Transport Delay
block delays the input by a specified amount of time. You can use this block to
simulate a time delay. The input to this block should be a continuous signal.
Details Of Parameters
Figure 4.25: Transport Delay Block Parameter Details
37
4.6
Comprehensive Sigma-Delta Design Explanation
The complete sequence of operations for AD conversion from analog input signal to
the digitized output signal is given in the detailed figure 4.26. For the sake of better
understanding only one phase is considered either it is current or voltage with 50 Hz
frequency normally. Analog signal processing is done first on the input signal then
the ADC modulator converts the processed analog signal to the digital signal which
also contains noise in it. In order to remove the noise and to get back the equivalent
digitized signal at the output digital filtering and down sampling is done in the last
section of the sigma-delta AD converter. According to the standard the 4 KHz data
rate is required at the output with a 16-bit of resolution.
Figure 4.26: Detailed model with explanation
After explaining above all the details of the Simulink modeling and the functionalities of the ADC model it is worth mentioning that the flexibility in this specific
ADC design is of quite big range. Any input analog signal having defined specifications can be converted to the digital form by tuning the input output filters and by
putting the required sampling rate and output data rate.
38
4.7
Simulation Results
The ADC model is simulated and the final step by step results are collected in the
form of Simulink graphs. These results are presented in the sequence as the ADC
model performs the processing on the input signal in the different sections of the ADC
model.
Result Before Modulator Action
Figure 4.27 shows the input signal waveform in the upper part of the graph and
the lower part shows the sampled signal for the equivalent input analog signal. For
all the figures below, the x-axis is the time axis and the y-axis is for the amplitude
representation.
Figure 4.27: Simulated Sampled Signal Output
Result After Modulator Action
In the modulator section of ADC model the sampled signal is 1-bit quantized. In
figure 4.28 upper part of the graph shows the analog input signal and the lower part
of the graph shows the quantized signal with some noise.
Figure 4.28: Analog Signal and Simulated Quantized Signal with error
39
Final Digital Output
The final figure gives the digitized form of the analog input signal. There are three
parts in the figure 4.29, the upper part of the graph shows the analog input signal,
the middle part shows the final digital form of the analog input signal and the lowest
part of the figure gives the total error between the input analog signal and the output
digital signal. The error is approximately ± 5 %.
Figure 4.29: Final Digital Signal Output
40
Chapter 5
Modelling Of Power System In
SIMULINK
5.1
Introduction
This chapter comprises of the modelling of a multi-bus power system in SimPowerSystems for different scenario simulations.
The chapter starts with the introduction to the overall power system with different
components in it. After the power system has been developed the MUs are placed at
the different nodes in the power system to get the three phase voltage and current
measurements. After the measurements have been collected then these measurements
are sent on to the Ethernet port in the form of SV (Sampled Value) stream. The
creation of SV (sampled value) stream of the digitized voltage and current signals is
the part of Project Part-B.
5.1.1
Power System Modelling
In order to test the developed product of MU the next task was to model a power system which can give the simulated values during normal and fault conditions to check
the flexibility and dynamics of the MU. In this task towards the accomplishment of the
thesis was to model a power system with multiple nodes in the MATLAB/SIMULINK
SimPowerSystems Toolbox.The reason for choosing SimPowerSystems Toolbox is because it operates in the Simulink environment and is dedicated tool for modelling
and simulating the generation, transmission, distribution, and utilization of electrical
power. It includes models of three phase electric voltage source, transmission line,
load, transformers. The motivation in using SimPowerSystems is because SimPowerSystems is compatible with the OPAL-RT Real Time Simulator and can be used to
test the overall system in the real time environment.
41
5.1.2
Power System Modelling In SimPowerSystems
The single line diagram of the power system which was modelled in the SimPowerSystems is shown in the figure 5.1.
Figure 5.1: Single line diagram of Test System
The figure shows various power system components connected together to form
a power system model. The details of these components and their respective parameter settings are discussed below.
5.2
List Of SimPowerSystems Blocks Used
The used components are presented in the following list and are explained one by
one.
1. Three phase Programmable Voltage Source
2. Three phase Two Winding Transformer
3. Three phase Pi Model For Transmission Line
4. Three phase OLTC Regulating Transformer
5. Three phase Series RLC Load
6. Three phase Fault
7. Three phase Discrete Sequence Analyser
8. Power GUI Block
5.2.1
Three phase Programmable Voltage Source
In SimPowerSystems library , the electrical sources category contains various voltage
sources which are based on the requirement of the modelling a certain power system.
In this thesis the three phase programmable voltage source is used. The figure 5.2
shows the block used in the model.
42
Figure 5.2: Three phase Programmable Voltage Source Block
Inputs And Outputs Of Block
The left side terminal denoted by ”n” is to connect the source to the ground terminal
externally. The A B and C terminals represents the three phases of voltages with
programmable time variation of amplitude, frequency, phase and harmonics.
Details of Parameters
43
Figure 5.3: Three phase Programmable Voltage Source Block Parameter Details
In this thesis work the programmable source is used to inject 2nd harmonic content
along with fundamental to check the data acquisition property of the MU. Also to
see how the MU behave when sudden changes happen in voltage, frequency during
certain time intervals.
5.2.2
Three Phase Transformer
The power system model shown in the figure 5.1 consists of a three phase transformer.
This transformer is modelled by using three phase transformer block in the elements
category of SimPowerSystems library as shown in the figure 5.4.
44
Figure 5.4: Three phase Two Winding Transformer Block
The block models three phase transformers using three single phase transformers. The model takes into account the winding resistances and inductances along
with the magnetizing characteristics of the core. The transformer between bus 1 and
bus 2 is a step down transformer with primary connected to 100 KV secondary is
connected to 33 KV.
Inputs and Outputs of Block
The terminals A B C represents the primary side of the transformer and the terminals
a b c represents the secondary side of the transformer. Transformer can be used as step
up and step down by using the appropriate voltage levels at primary and secondary
windings of the transformer.
Details of Parameters
Figure 5.5: Three phase Two Winding Advance Parameter Details
45
Figure 5.6: Three phase Two Winding Transformer Parameter Details
Figure 5.7: Three phase Two Winding Transformer Parameter Details
46
5.2.3
Three Phase PI Section Line
The transmission line between bus 2 to bus 3 is modelled by using three phase PI
section linie block available in the elements category of the SimPowerSystems library
as shown in the figure 5.8.
Figure 5.8: Three Phase PI Section Line Block
This blocks implements a balanced three phase transmission line with parameters lumped in a PI section line.
Inputs and Outputs of Block
The terminals on both sides of the block represent the two ends of a transmission
line. The parameters provided for the transmission line will implement a Pi section
line within these two terminals of a block.
Figure 5.9: Three Phase PI Section Line parameter details
47
5.2.4
Three Phase OLTC
The three phase OLTC transformer block available in the transformer category of the
application library of SimPowerSystems is phasor type. However the aim is to model
this system in discrete mode. This phasor block can not be used in discrete mode.
The OLTC block thus used for this purpose is available in the demo OLTC Regulating
Transformer(Phasor Model). This demo contains simple three phase OLTC regulating
transformer and it is used here in our power system model for voltage regulation on
bus 4.
Figure 5.10: Three Phase OLTC Block
This block models a three phase two winding transformer with on load tap
changer to regulate the voltage on the transmission or distribution network. This
model basically provides 17 taps i.e. +8 to -8 and tap position 0 represents nominal
voltage ratio.
Inputs and Outputs of Block
The terminals A B C represents three input terminals connected to winding 1.Terminals a b c represents the three terminals connected to winding 2. Vm is the voltage
which is to be controlled. In this system model the 10 MW load is attached to the
Bus no 4 whose voltage is to be regulated. So we are feeding this Vm input with a
voltage magnitude at Bus 4, ”m” ia an output which provides the metering facilities for various signals which can be chosen with the help of ”bus selector” block of
Simulink.
Parameter Details
48
Figure 5.11: Three Phase OLTC transformer parameter details
49
Figure 5.12: Three Phase OLTC voltage regulator parameter details
5.2.5
Three Phase Series RLC Load
This block implements three phase balanced load as a series combination of resistance,
inductance and capacitance. The load provides a constant impedance. The block
diagram is shown in the figure 5.13.
Figure 5.13: Three Phase Series RLC Load Block
Parameter Details
50
Figure 5.14: Three Phase Series RLC Load Parameter details
5.2.6
Three Phase Fault
As this model is also designed to study dynamics of power system i.e transient stability, voltage stability in a sense to observe the behaviour of ADC and the packet
transmission during different system conditions or to see the performance of the MU.In
that sense a provision is given to the user to apply a three phase fault at the transmission line between the nodes 2 and 3 to check the system behaviour and at the
same time to check whether the developed product MU work with required accuracy
or not. The three phase fault is applied by using the three phase fault block available
in the elements category of SimPowerSystems library.
Figure 5.15: Three Phase Fault Block
51
Inputs and Outputs of Block
The terminals A B C represents the three breakers inside the block which are connected to the ground through an internal ground resistance.
Parameter Details
Figure 5.16: Three Phase Fault Parameter Details
5.2.7
Metering Blocks
In order to monitor the voltages and currents in the system the three phase VI
measurement block is available in the measurement category of SimPowerSystems
library.
52
Figure 5.17: Three Phase VI Measurement Block
This block measures the three phase instantaneous currents and voltages in a
circuit.Either phase to phase or phase to ground can be measured with the help of
three phase VI measurement block.
Inputs and Outputs of Block
Vabc and Iabc are the outputs containing three phase currents and voltages measurements. Terminals A B C are the input terminals and a b c are the output terminals.
This block is often used as a bus in the model and gives output same as the input to
the bus.
Parameter Details
53
Figure 5.18: Three Phase VI Measurement Parameter Details
5.2.8
Discrete Three Phase Sequence Analyser
Another metering block used is discrete three phase sequence analyser.As the signals
from the three phase measurement blocks are the three phase voltages and currents in
per unit, so these signals are fed to the sequence analyser to get the positive sequence
voltages and currents in per unit which are then monitored with the help of scope.
It is available in discrete measurement subcategory of the measurements category in
SimPowerSystems libraary.
54
Figure 5.19: Discrete Three Phase Sequence Analyser Block
Inputs and Outputs of Block
The input abc can be either Voltage Vabc OR Iabc generated by the three phase VI
measurement block. The output magnitude and phase is the value of the positive
sequence voltage or current.
Parameter Details
Figure 5.20: Discrete Three Phase Sequence Analyser Parameter Details
However all the signal monitoring is done through the scope block present in
the commonly used blocks category of Simulink.
5.2.9
Power GUI Block
It is the environment block for the SimPowerSystems models and provides multiple
functions. This block is present in the main library of SimPowerSystems. The details
of this block are explained below.
55
Figure 5.21: Power GUI Block
Details of Power GUI Block
Figure 5.22: Power GUI Configuration Settings
56
Figure 5.23: Power GUI Configuration Settings
57
Figure 5.24: Power GUI Analysis Tools
5.3
Full Modelled Power System
Power system model comprises of 100 KV programmable voltage source, 1-100/33
KV step down transformer, 4-buses, 10 Km transmission line, 10 MW load attached
to the bus 4. A OLTC voltage regulator 33/33 KV is placed between bus 3 and bus
4 to stabilise the voltage on the bus 4 and keep it to the nominal value.
Figure 5.25: Three Phase Power System Modelled in Simulink
58
5.3.1
Purpose of Power System
The main reasons behind the modelling of power system in this study work is to test
the developed MU for different scenarios. The scenarios which will be produced by
simulating the above power system under different parameter settings. Once these
scenarios have been developed then the performance of the modelled MU can be
tested. These scenarios are listed below, but the details of these scenarios will be
explained in the next chapter.
1. Executing Three Phase Symmetrical Fault near Bus2 for Over current Protection Function Testing of RET 670 IED
2. Executing Single Phase to Ground Fault For Unsymmetrical Faults of RET 670
IED
3. Injection of 2nd Harmonic Content to Test Harmonic Restrain Function of RET
670 IED
4. Voltage Stability Test
5. Testing of Transformer Differential Protection Function
The MU can be connected to any of the bus or at all buses to get values
and transmit them to the IED. However the power system will be simulated under
different parameter conditions to test the MU performance.
59
Chapter 6
Complete Test Platform
6.1
Background
This chapter comprises of scenarios listed in the previous chapter for the testing of
the developed models. First of all the full testing scheme will be presented. The
introduction of the hardware and the software used to accomplish the testing of
Merging Unit will be given before the testing function details.
6.2
Physical Test Platform
There are quite a few test schemes already existed and used for the testing of Merging
Unit. One of these test platform is presented here in order to support the test setup
designed for the testing of soft Merging Unit in this thesis work. This test comprises
of all the physical models of all the participating devices but the test setup used in this
thesis work is comprises of all the components modelled in Simulink. In order to test
the digital protection system using optical instrument transformers interconnected
by an IEC 61850-9-2 process bus, Arizona State University (ASU) has developed a
dedicated test facility. The major components in the system are, the current generator
of the test set up, NxtPhase optical current transformer (OCT), with Merging Unit
(MU), AREVA digital relay and a computer. The over current protection function is
tested in this setup. The SV traffic stream is sent to the digital relay and the relay
sends the trip message after detecting the over current fault [5]. The test facility is
presented in the figure 6.1.
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Figure 6.1: Picture of the test setup for the all-digital over-current protection[5]
6.3
Protection Function Testing Tools
The testing of different protection functions is done through the following testing
scheme. Testing scheme consists of the following hardware and software tools.
6.3.1
Hardware Tools
As the motivation behind this thesis work is to develop a soft Merging Unit which
can be used and simulate on a student MATLAB/SIMULINK environment where
you can have the opportunity to work on such an advance device without any access
issues which surely lies with the vendor manufactured Merging Units.
1. Ordinary Lab Computer
2. RuggedSwitch RS900
3. IED RET 670
61
6.3.2
Software Tools
As we have developed the soft Merging Unit consists of the parts which are modelled
in a working environment which is easily accessible by activating student license
requirements.
1. MATLAB/SIMULINK
2. C language
3. PCM 600
4. Wireshark
6.4
Lab Setup for the Soft Merging Unit Testing
The figures 6.2 and 6.3 show the setup in the lab for the testing of protection functions
by soft Merging Unit.
Figure 6.2: Lab Setup for Soft Merging Unit for Protection Function Testing
62
Figure 6.3: Lab Setup for Soft Merging Unit for Protection Function Testing
6.5
Complete System Integration
The procedure for the testing of different protection functions includes the integration
of all the developed models. In first step the CT/PT models are connected to the
different nodes of developed power system in order to convert the higher voltages and
currents to the level of low voltages and currents. In the second step the ADC models
are connected to the outputs of the CT/PT to convert analog signals to the digital
form.In the third step the transmission part is attached to transmit the digitized data
to the Ethernet port according to the IEC 61850-9-2 Sampled Value protocol. In the
fourth step the SV stream is fed to the ABB IED RET 670 through a Ruggedcom
Switch to operate the IED for the desired protection.
63
Figure 6.4: Protection Function Testing Scheme
6.5.1
Protection Function Testing Scheme
The pictorial representation of the test scheme is given in figure6.5.
Figure 6.5: Protection Function Testing Scheme
64
All kinds of scenario testing will be done with this basic testing scheme. The
only constraint which will be changing for each scenario is the parametrization of the
power system components to check the performance of developed components.
6.5.2
Description of Hardware and Software
A personal computer with MATLAB/SIMULINK software tool installed on it provides the dynamic and flexible environment to model any type of system. In our
project the specifications of the computer are 2.00 GB of memory (RAM) and Intel
Core 2 DUO CPU of 2.53 GHz. An Ethernet switch is required to send the data from
the sending end to the destination address. In our case the RuggedSwitch RS900 is
used for the sending of SV stream to the IED RET 670. The RuggedSwitch RS900 is
a 9 port industrially hardened, fully managed , Ethernet switch specifically designed
to operate reliably in electrically harsh and climatically demanding environments. It
provides a high level of immunity to electromagnetic interference and heavy electrical
surges[31]. As this research study is collaborated with ABB so we are provided with
RET 670 IED which is a differential protection relay for transformers. The software
tool PCM 600 is used to configure the RET 670 for over current and differential
protection of transformer.
6.6
Over-current Protection Scenario
The purpose of this scenario is to test the working of the Merging Unit during normal
and fault condition measurements received from the power system.
Power transformers can have large inrush currents in the energizing process.
This is due to the saturation of the transformer core.The inrush current has a large
content of 2nd harmonic. Due to these inrush currents there is a risk that these
currents will reach the level above the pick up current of the phase over current
protection. This gives the risk of an unwanted trip. In order to get rid of this
unwanted trip there is a 2nd harmonic restrain blocking function. This component
can be used to create a restrain signal to prevent this unwanted trip[32].
It would be interesting here to first analyse whether the RET 670 recognises
the transmission of data by the Merging Unit or not and then to test the over current
protection function for the 2 winding transformer.
6.6.1
Configuring IED RET 670
In order to make any kind of test on the MU it is necessary to configure the IED for
the MU. The software which is used to configure RET 670 is the PCM 600. The IED
can be configured according to the functionalities already defined in the package of
that IED. The model which is used in the study is basically a differential protection
65
relay for the transformer. It has main protection blocks for the configuration of 2winding transformer protection, 3-winding transformer protection. There are lots of
other protection function blocks related to the internal protection of the transformer.
There is also an over current protection block which will be used to configure the IED
RET 670 for the protection of 2-winding transformer from the over-currents due to
the large faults on the system.
6.6.2
Power System for Steady State Measurements
The complete system used for the measurements during the steady state is a 3-bus
power system which is comprises of a three phase source, a 2-winding step down
transformer, 10 Km long transmission line and a 10MW load. The values from any
node of the power system can be taken and send to the IED. As the values from the
sending end are known and can be verified by reading on the HMI screen of the RET
670 IED. System for steady state test is shown in the figure 6.6.
Figure 6.6: Power System with MUs attached to the Nodes
It is very important to brief about the .mat files which are saving data from
the power system during off-line simulations. These files are then directly read by
the Part-B of the Project and the SV stream is sent to the IED, which explains the
whole purpose of this project.
66
6.6.3
Application Configuration in PCM 600
Before going to check complex functions on the Merging Unit the first test is to
approve that the MU is working properly and sending the data according to the
IEC 61850-9-2 standard. However to check and confirm the steady state process the
sending end values from the power system developed in the Simulink can be checked
on the local HMI of the IED after configuring it for the MU and SV stream.The
blocks which are configured in the PCM 600 for steady state measurement of the SV
stream are shown in the figure6.7.
Figure 6.7: Application Configuration for Monitoring Function In PCM600
The block named ”VMMXU” and ”CMMXU” are used to configure the monitoring functions for the measured values of voltages and currents. Now the values
which are sent by the MU can be seen on the IED HMI. When these values were
checked, the sending end values and the values which appeared on the HMI of IED
were same. These values are the RMS 3-phase voltages and currents.
6.6.4
Simulation Values at Node 2
The steady state values of 3-phase voltages and currents on the secondary side of
the transformer is shown in the scope. The figure 6.8 shows the steady state values
captured in off-line simulations.
67
Figure 6.8: Three phase Voltages and Currents at BUS 2
6.6.5
Screenshot of IED RET 670 HMI
The SV stream read by the IED is shown on the HMI. The 4I and 4V are being
monitored by the IED. All these values are RMS values of currents and voltages.
Screen shot of IED HMI is shown in the figure 6.9.
68
Figure 6.9: Steady State Values
6.6.6
Transient State Test and Over-Current Protection
In order to analyse the behaviour of the MU during the transient state the power
system is subjected to the sever short circuit fault. A three phase to ground symmetrical fault is applied on the secondary side of the 2-winding transformer to create the
transient scenario. The transient case scenario also gives the opportunity to test the
over current protection function. The system used for this test is shown in the figure
6.10.
69
Figure 6.10: Power System with Three Phase Short Circuit Fault
The interesting point about the testing of MU involves how it responds to the
transient values produced by the three phase to ground short circuit fault. It will be
analysed that whether the correct values are shown on the IED HMI or not. In order
to test the over current protection function the instant the fault current crosses the
set threshold value of the current the IED must give a trip signal to confirm that the
everything responded to the abnormal condition.
6.6.7
Configuration of Over-Current Protection in PCM 600
The application configuration includes the configuration of Four step phase overcurrent protection block named ”OC4PTOC”. The four step over-current protection
function has an inverse or definite time delay independent for each step separately.
The protection design can be divided in four steps[32].
• The direction element
• The harmonic restraint blocking function
• The four step over current function
• The mode selection
70
From the above four parts the simple four step over current and harmonic restraint
blocking function are configured in application and parameter settings. The more
details about the parameter settings are attached in the appendix for the better
understanding of reader. The block used for configuring the over-current protection
is shown in the figure6.11.
Figure 6.11: Four Step Over-current Protection Block OC4PTOC
The different trip signals are assigned to different LED’s on the local HMI
of the IED RET 670 to visualise the protection function working properly. For the
case of over-current protection each phase current values area compared with the set
operation current values in a comparator block. If the values of phase currents for
some reason exceeds the set operation values the trip will be activated.
6.6.8
Parameter Settings for Over current Protection
The Table 6.1 shows the Parameter settings of 4 step over current protection function.
In the following table the four step over current protection function parameters are
set to test the over current protection. There are four steps each step can be set with
different threshold values of current and the time to activate the trip. Similarly there
are four pickup currents for each step. In the following parameter settings the first
step will be activated when the pick up current will rise up to 175% of the base value
of the current which is set to 170 amperes. This trip will be activated after waiting
for 5 seconds. The second step will be activated when the pick up current will rise
up to 250% of the base value of the current which is set to 170 amperes. This trip
will be activated after waiting for 2.5 seconds seconds.The third step will be activated
when the pick up current will rise up to 500% of the base value of the current which
71
is set to 170 amperes. This trip will be activated after waiting for 1 second. The
fourth step will be activated when the pick up current will rise up to 1000% of the
base value of the current which is set to 170 amperes. This trip will be activated
simultaneously due to too high short circuit currents which probably gives the dead
short circuit condition. For more details on the overcurrent test which includes the
parameter and application configurations of the digital relay (ABB RET 670 IED)
are presented in the appendix A.
General
Parameters
Values
Ibase
170A
StartPhSel
3 out of 3
Step 1
Step 2
Parameters Values Parameters Values
I1>
175%
I2>
250%
t1>
5s
t2>
2.5s
Step 3
Step 4
I3>
500%
I4>
1000%
t3>
1s
t4>
0s
Table 6.1: OC4PTOC parameters
6.6.9
Simulation Values at Node 2 During Fault
Three phase voltages and currents values for off line simulations when a three phase
to ground short circuit fault is applied on the secondary side of the 2 winding transformer. The simulated values on the BUS 2 are shown in the figure 6.12.
72
Figure 6.12: Three Phase Voltages and Currents at BUS 2
6.6.10
Screenshot of Local HMI of IED RET670
The figure 6.13 shows the transient state values of 4I and 4V during the three phase
short circuit state. The trip command is activated by the IED RET 670 in order to
protect the transformer from over current fault.
Figure 6.13: Transient State During Three Phase Short Circuit
73
6.7
Additional Tests
The test platform is available along with complete test setup. The developed product
is available to test for different functionalities. The additional tests like injection of
additional harmonics along with fundamental frequency, putting an unsymmetrical
fault would be quite interesting to see the response of MU.
6.7.1
Response of MU Under Unsymmetrical Fault
This test is performed to check if the MU work properly during unsymmetrical faults
or breaks down. For this test one phase to ground fault was applied to the secondary
side of the power system. The measurements are collected by the MU attached at
bus 2. This measurement of three phase currents and voltages due to unsymmetrical
fault is transferred to IED RET670 according to the IEC 61850-9-2 SV stream. The
local HMI of IED can be visualised to verify the values from both ends, values at
simulation and the values picked up by the IED from the MU. The same system as in
the figure 6.10 is used with different set of parameters to apply unsymmetrical fault.
The simulation results obtained from the power system are in figure6.14 and the IED
RET 670 local HMI Snapshot is also shown.
Figure 6.14: Three Phase Voltages and Currents at BUS 2 During Unsymmetrical
Fault
6.7.2
Response of MU Under Harmonic Injection by Source
This test is simulate to expose the MU under another different condition to analyse
the behaviour of the MU. In this test besides fundamental harmonic two additional
harmonics are injected and in the similar way the measurement are taken at the bus
74
2 and then checked at the local HMI of the IED for verification. The test system used
is shown in the figure6.15.
Figure 6.15: Test System for Harmonic Injection
The power system simulation results at bus 2 with the injection of 3rd and 5th
harmonic is shown in the figure6.16.
75
Figure 6.16: Three Phase Voltages and Currents at BUS 2 With Harmonic Injection
6.7.3
Response of MU Under OLTC Operation
In this test the OLTC voltage regulator is used as to regulate the voltage on the bus
4. The voltage magnitude is fed as input to the OLTC to keep the continuous track
of the voltage on the bus 4. If for some reason the voltage on the bus 4 drops down
it will operate and keep the voltage to the nominal 1 p.u. according to the control
settings in the OLTC. While voltage regulation process is working continuously it is
quite interesting to see how the MU give response and transmit the value to the IED.
In order to monitor the measurements at the buses 3 and 4 each bus is connected
with the MU. Also these measured values are verified on the local HMI of IED.The
system used for this test is shown in the figure 6.17.
76
Figure 6.17: Voltage Regulation Monitoring Test System
For this test two MUs are subscribed and configured in the IED by PCM600.
First the offline simulations are run and the data is stored in the .mat files. These
stored data files are then read by the transmitting part of MU and SV stream is transferred to the IED via Ethernet port according to IEC 61850-9-2 protocol. As both
the MUs are sending data from the same Computer they are not exact synchronised.
The synchronization part is left to the future work.
6.7.4
Simulation Results on Bus 3 and 4
The voltage regulation on the bus 3 and bus 4 are shown in the scope in the figure6.18.
The voltage value is shown in the p.u. value.
77
Figure 6.18: Voltage Regulation on Bus 3 and 4
The voltage is at its nominal 1.0 on both the buses. The tap changing is also
shown in the figure 6.19.
Figure 6.19: Tap Position
The tap position changes according to the feedback given to the OLTC control
as Vm from the Bus 4. When the voltage magnitude at Bus 4 decreases or increases
the tap adjusts its position by increasing or decreasing the number of windings.
6.8
Transformer Differential Protection Test
This test is explained in detail and is appended in the appendix A.
78
Chapter 7
Results
This chapter presents the results of all the test cases. This section mainly shows the
results of all the cases after passing through the developed ADC model. Once the
analog waveforms are produced by the power system then these waveforms are fed to
ADC to convert them to digital form.
7.1
ADC output for Over current Protection
The ADC converts the analog input to digital form at 4KHz. The figures7.1,7.2 gives
the simulation results for over current protection case to show the ADC behaviour
during the steady state and the figures 7.3 7.4 shows transient state when three phase
to ground short circuit fault occurs.
Figure 7.1: ADC Output of Voltage During Steady State
79
Figure 7.2: ADC Output of Current During Steady State
Figure 7.3: ADC Output of Voltage During Transient State
80
Figure 7.4: ADC Output of Current During Transient State
The simulation results and the IED local HMI results during the off line testing
verify the measured values by the power system and the visual result on the IED lacal
HMI, as both have the same values.During fault the voltage goes to zero that is what
the ADC is showing in the voltage output scope. when three phase short circuit fault
occurred the value of current goes 10-12 times to the nominal and the saturation
occurred in the CT which leads to the ADC, that is what ADC showing the transient
in the current scope.
7.2
ADC Output During Harmonic Injection
Thus result presents the simulated output of ADC when the additional harmonics
are also added to the fundamental signal. The figures7.5,7.6 shows both three phase
voltages and currents in the scope.
81
Figure 7.5: ADC Output of Voltage During Harmonic Injection
Figure 7.6: ADC Output of Current During Harmonic Injection
The output digitized signal is of 16-bit resolution and 4KHz of data rate which
is the requirement of this study work. The values shown in the scopes are scaled
down for signal processing. The ADC is flexible in converting the analog signals to
digital signals in its range. There is not any exact upper and lower limit of scaled
down data that can be converted to the digital form by the modelled ADC. Basically
the tuning of filters define the limit of a scaled down signal that can be converted to
digital form with minimum error between the original and digitized signal.
82
Chapter 8
Discussion
This thesis is the Part-A of the Project named development of a soft Merging Unit. In
Part-A the instrumentation and signal processing modules are modelled in Simulink.
The transmitter module in Part-B of the Project [9] is programmed in C language.
Combining all the three modules gives us the developed model of a soft Merging
Unit. The discussion includes the reliability, validity and evaluation of the whole soft
Merging Unit.
The idea behind the development of the soft merging unit is to have such a test
scheme setup where you could easily attach your device to perform different kinds of
functionalities in order to test the reliability, validity and evaluation of that device.
There are two interfaces between the 3 phase high voltage incoming conductors and
the protection relay (IED) in a substation.
The most important thing which is needed to mention here is the synchronization module of the MU. The SV messages are the time critical messages. The time
stamp is needed when you have more than one MU in your test system. The synchronization part of this Project is in the pipeline and is recommended as the future
work due to the time constraint.
The first interface is to step down the high voltages and currents to the level
of monitoring and control. The second interface is the conversion of this step down
measurement to the standardised form. The scaled down measurements are converted
to digital form upto 16-bit of resolution. The first interface is modelled in Simulink
which gives the realization of a conventional CT/PT. The CT/PT is used to step
down the high voltages and currents to the 120V and 1A respectively. These step
down analog values are further scaled down for the second interface to work properly.
The second interface is modelled as an analog to digital converter with a working
range of values from -1 to 1. Now the Part-B of the Project is used to transmit
these measured values from the power system to the ethernet cable connecting to the
83
protection relay (IED) according to the IEC 61850-9-2 standard.
The idea was to integrate both the interfaces with the transmission part developed in Part-B of the Project [9] by creating a S-function and connecting it directly
to the Part-A of the Project. We tried to run the whole simulation online but due to
the large number of computations in the ADCs and also due to the slow processing by
S-function it was not appropriate to wait for a simulation which is actually run for 30
seconds but in real time it was taking almost 1 hour so we leave this idea for further
research due to the time constraint. We are aiming to try this out by using the UDP
send and UDP receive techniques to get the online realization of this simulation of
soft MU.
In order to evaluate the soft MU the off-line testing is performed and the
protection relay successfully recognised the MU according to the IEC 61850-9-2 standard.Then the on-line simulation is performed to check the response off IED to the
SV stream send by the computer. The Part-B of the Project [9] use the reading of
.mat files and replaying that data to the IED. Over current protection and differential
protection for transformer is also configured and successfully implemented by using
the soft MU. During off-line testing the digitized data is stored into the .mat files.
The advantage of this soft MU is that the utility persons and the academic
researchers can easily connect this MU to any of the modelled system without any
hesitation to test different scenarios according to the customer requirements. In contrast if you need to connect a 1000 real MUs it could be extremely hard and costly
to set such a setup which could be of a huge price. Also the danger of loosing costly
equipment if any kind of disturbance occurs. Whereas with the facility of soft MU
we can test any kind of scenario depending on the demand from the utility.
Finally the soft MU is available to make a lot of tests on it. In order to investigate soft MU more accurately we need to have more advanced networking tools. By
using those software tools we can check the data rate, bit error rate (BER), packet
loss, delay between two consecutive samples and total network traffic. The reliability of the MU can be checked by loading the network heavily and lightly to analyse
the background traffic impact on the soft MU. These tests and analysis will be more
helpful in the validation and reliability of soft MU.
84
Chapter 9
Future Recommendations
This chapter gives future recommendations about this thesis and also about the developed soft Merging Unit.
9.1
Future work for this thesis
This thesis work comprises of models of CT/PT, ADCs and power system modelling.
The recommended future work about all of theses individual components is listed
below.
1. CT/PT models developed here are the ideal models which are giving the exact
transformation of currents and voltages at any condition. In the future work
it is recommended that the CT/PT models should be of real kind which could
give the realization of saturation effects due to core saturation during transients.
This will help in more detailed analysis of the ADCs. It is recommended that
for the modelling of CT the right choice of CT type must be considered because
it affects the performance of relay with respect to time. The accuracy class
and burden load should also be taken care of in the future design of the CT
model[33].
2. In this thesis work one kind of ADC model is developed called Sigma-Delta
which is considered for its cheapness and oversampling ration advantages. But
it would be quite interesting if we develop the ADC models with successive approximation or dual slope types to also have a nice comparison among different
ADC types. In this thesis work the first order sigma delta model is used. The
analysis can be done by developing a second order Sigma-Delta ADC model.
3. In this study the simple power system is used to have a set of nice data of
voltages and currents to feed MU under different scenarios. In future the more
complexed power system can be developed with large number of buses having
MU attached to more than three buses. This will increase the analysis range
85
of the developed project. This power system is only used to test the Process
Bus. If the loop of the setup is completed by giving GOOSE trip message back
to the breaker in the modelled power system then both the process and station
buses can be seen working together.
9.2
Future work for the whole project
As the output of the Project is the soft Merging Unit. Some recommendations about
the future work On this developed product is listed.
1. The application of MU is to fulfil the IEC 61850-9-2 standard in the modern
digital substation. The sampled value messages are time critical and also needs
to be synchronised. So the synchronization part of this MU is missing due to
time constraint. It is recommended that the synchronization part should also
be developed according to the IEEE 1588, a precision clock synchronization
protocol.
2. The third application is to test the interoperability between the developed MU
and different kind of IEDs manufactured by different vendors. The setup will
have all the three IEDs from ABB, AREVA and SIEMENS connected all together and the MUs through a switch. The SV stream send to the ABB IED
and the trip command send by ABB IED to other IEDs will be interesting to
analyse. The figure 9.1 explains the idea of interoperability.
Figure 9.1: Interoperability Representation at Process Level
86
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[4] D. Jarman, “A brief introduction to sigma delta conversion,” Application Note
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1
Appendix A
Evaluation Report
A.1
Four Steps Phase Overcurrent Protection OC4PTOC
with 2nd Harmonics
The OC4PTOC without 2nd Harmonics is already discussed in Chapter ?? so only
the principle of harmonic restrain blocking function is introduced in next section.
Principle of the harmonic restrain blocking function
Over excitations of a transformer can cause unnecessary operation of transformer differential relays. These over excitations can also be caused by the inrush currents or
by sudden voltage rise. One condition might be the loss of a big load connected to
the secondary of transformer and the primary is still energized. When the primary
winding of a transformer is overexcited and driven into saturation as a result more
power appears to be flowing in than flowing out of the secondary winding. As over excitation phenomena is developed due to some internal dynamics caused in the power
system it also generates some of the other harmonics with the fundamental [34]. This
situation causes the relay towards wrong trip condition which is not acceptable at
any cost. Now it is necessary to have a algorithm in the relay to clearly discriminate
between the over excitation and the faulty states. Therefore the relay we are using in
our testing facility is RET 670 which is equipped with second harmonic restrain function. This function will not allow the trip due to inrush currents in the transformer.
Power transformers can have a large inrush current, when being energized. This phenomenon is due to saturation of the transformer magnetic core during parts of the
period. There is a risk that inrush current will reach levels above the pick-up current
of the phase over current protection. The inrush current has a large 2nd harmonic
content. This can be used to avoid unwanted operation of the protection. Therefore,
OC4PTOC have a possibility of 2nd harmonic restrain if the level of this harmonic
current reaches a value above a set percentage of the fundamental current.[35]
If a power transformer is energized there is a risk that the transformer core will
2
saturate during part of the period, resulting in an inrush transformer current. This
will give a declining residual current in the network, as the inrush current is deviating
between the phases. There is a risk that the phase over current function will give
an unwanted trip. The inrush current has a relatively large ratio of 2nd harmonic
component. This component can be used to create a restrain signal to prevent this
unwanted function.[35]
To avoid unwanted trip due to inrush current in the transformer, 2nd harmonic
current is monitored. The 2nd harmonic current is compared to a pre-set restrain
current level. If 2nd harmonic current exceeds the set level, the over current trip from
all steps will be blocked.
Testing setup
1. Simulink power system model which is used to generate testing data.
Figure A.1: The Simulink model of the testing
As shown in Figure A.1, the red rectangle marks the block which can inject 2nd
harmonic into the system. The fault is still the three-phase to ground fault.
The time line of the simulation is shown in Figure A.2 below.
3
Figure A.2: The scheme of the testing
To test the 2nd harmonic restrain in OC4PTOC function, the 2nd harmonic is
introduced with fault during 20-25s. The OC4PTOC function should not trip
during that period. The OC4PTOC function will trip after 25s when the 2nd
harmonic is removed.
2. The application configuration is shown in Figure A.3 below.
4
Figure A.3: The application configuration in PCM 600
The mapping of the LED is listed in Table A.1.
Signals
General Trip
Trip for Step 1
Trip for Step 2
Trip for Step 3
Trip for Step 4
Trip signal
from phase L3
LEDs
RED1
RED2
RED3
RED4
RED5
RED6
Signals
General Start
Start signal from step1 phase
Start signal from step2 phase
Start signal from step3 phase
Start signal from step4 phase
Block from
2nd harmonic detection
L2
L2
L2
L2
LEDs
YELLOW7
YELLOW8
YELLOW9
YELLOW10
YELLOW11
YELLOW12
Table A.1: The map of LED
3. Parameter configuration of OC4PTOC is listed in Table A.2.
5
General
Parameters
Values
Ibase
170A(RMS)
StartPhSel
3 out of 3
2ndHarmStab
50%IB
Step 1
Step 2
Parameters
Values
Parameters
Values
I1>
150%IB
I2>
250%IB
t1>
5s
t2>
2.5s
HarmRestrain1
On
HarmRestrain2
On
Step 3
Step 4
I3>
500%IB
I4>
1000%IB
t3>
1s
t4>
0s
HarmRestrain3
On
HarmRestrain4
On
Table A.2: OC4PTOC settings for 2nd harmonic restrain
6
Results
(a) Normal condition during 0-15s
(b) The 2nd harmonic is introduced at 15s
(c) The fault is injected after 20s but no trip
(d) The 2nd harmonic is removed and Step 3
is trip
Figure A.4: The results of OC4PTOC with 2nd harmonic
7
A.2
Two Windings Transformer Differential Protection (T2WPDIF)
Principle of Transformer Differential Protection
Differential relays are often used as main protection for all important elements of the
power system such as generators, transformers, buses, cables and overhead lines. The
protected zone is clearly defined by the positioning of the main current transformers
to which the differential relay is connected [36].
The principle of transformer differential operation is the comparison of value
of current on both primary and secondary sides of the transformer. Under normal
conditions I1 and I2 are equal and opposite such that the resultant current through
the relay is zero. If the difference between the two currents is greater than the set
threshold value the relay will detect the fault [36].
Figure A.5: Schematic of two windings transformer differential protection
Principle of T2WPDIF
As we are using ABB RET 670 differential protection relay for the transformer. RET
670 has both two winding and three winding differential protection functions which
is shown in Figure A.6. In this evaluation work we used the two winding transformer
protection block. The brief introduction about T2WPDIF is provided here for better
understanding of the differential protection function of RET 670.
8
Figure A.6: The transformer differential protection provided in RET 670
A transformer differential protection compares the current flowing into the
transformer with the current leaving the transformer. A correct analysis of fault
conditions by the differential protection must take into consideration changes due to
voltages, currents and phase angle changes caused by protected transformer. Traditional transformer differential protection functions required auxiliary transformers
for correction of the phase shift and ratio. The numerical microprocessor based differential algorithm as implemented in the IED compensate for both the turns-ratio
and the phase shift internally in the software. No auxiliary current transformers are
necessary. [35]
Testing Setup
1. Set up the offline testing model for differential protection
9
Figure A.7: The Simulink model for differential protection
As shown in Figure A.7 above, the power system comprises of a voltage source,
two winding power transformer, a transmission line and a load. The transformer
winding ratio is 1:1. The model is simulated in offline mode for 30 seconds to
collect the measurements. The three phase short circuit fault is applied on the
primary side of the transformer from 16 to 25 seconds. The Merging Unit 1
and Merging Unit 2 named ”KTH ICS SV1” and ”KTH ICS SV2” respectively
are connected to the CT1 and CT2. After the simulation, the waveforms of the
primary and secondary sides are shown in Figure A.8 below.
10
Figure A.8: The waveforms of primary and secondary sides
Druing the normal operation, the current on both sides is around 500A at
peak. During the fault, the primary side current increases to approximately
700A at peak and the secondary side current goes to almost zero. As shown
in Figure A.7, the three-phase to ground fault happens in the primary side of
11
the transformer, all the current comes into the primary side will go to ground
during the fault. There will be no current on the secondary side during the fault.
During the fault, the current difference between primary side and secondary side
is about 500A.
2. Set up the process bus communication interface. In this test, the process bus
interface should read measurement from both primary and secondary sides of
transformer and send both of them out.
Figure A.9: The Wireshark capture of sending SVs for two MUs
3. To subscribe two measurement data sets, set up the ”svID” for RET 670 to
”KTH ICS SV1” and ”KTH ICS SV2”.
12
Parameter
MU1
SVId
MU2
SVId
Value
4I 4U 921
KTH ICS SV1
4I 4U 921
KTH ICS SV2
Table A.3: Parameter setting for MU
4. Connect the T2WPDIF function block in application configuration
Figure A.10: Application configuration for T2WPDIF
The LED mapping for T2WPDIF is listed below in Table A.4.
13
Signals
General Trip
Trip from restrained function
Trip from
unrestrained function
Common start
LEDs
RED1
RED2
RED3
Signals
2nd harmonic block
5th harmonic block
Alarm from
sustained diff current
LEDs
RED5
RED6
YELLOW7
RED4
Table A.4: The LED map for T2WPDIF
5. Parameter setting of the T2WPDIF
Parameters
Values
T2WPDIF:1
RatedVoltageW1
100kV
RatedVoltageW2
100kV
RatedCurrentW1
350A(RMS)
RatedCurrentW2
350A(RMS)
ConnectionTypeW1
WYE(Y)
ConnectionTypeW2
WYE(Y)
Setting Group1
Operation
On
SOFTMode
Off
IDiffAlarm
0.1 IB
Parameters
Values
ClockNumberW2 6[180deg]
ZSCurrSubtrW1
on
ZSCurrSubtrW2
on
TconfigForW1
no
TconfigForW2
no
LocationOLTC1 Not Used
tAlarmDelay
IdMin
IdUnre
10s
0.3 IB
10 IB
Table A.5: T2WPDIF settings
As shown in Table A.5, the rated current of winding 1 (W1) and winding 2 (W2)
are set to the same value which indicates the ratio of the primary and secondary
side is 1. The ”IdMin” is the threshold current. When the current difference
between primary and secondary sides exceeds ”IdMin”, the restrained protection
will trip. In this case, the ”IdMin” is 0.3*IB=0.3*350=105A(RMS). When the
current difference exceeds ”IdUnre” which is set to 10*IB, the unrestrained
protection will trip.
Results
Normal Setting
Firstly, the setting as listed in Table A.5 is written to RET 670. Since the three-phase
to ground fault happens in the primary side of the transformer, all the current comes
into the primary side will go to ground during the fault. There will be no current
on the secondary side during the fault. The current difference between primary and
14
secondary sides is around 500A which already exceeds the threshold 105A. The RET
670 trips normally and the results are shown in Figure A.11 below.
15
(a) The normal readings from MU1
(b) Readings from MU1 during trip
(c) Readings from MU2 during trip
(d) After fault readings from MU2
Figure A.11: The trips of T2WPDIF
16
High Threshold Setting
In this setting, most of the parameter settings are the same as that in Table A.5. The
parameter changed are listed in Table A.6 below.
Parameters
Values
T2WPDIF:1
RatedCurrentW1 1000A(RMS)
RatedCurrentW2 1000A(RMS)
Setting Group1
IdMin
0.6 IB
Table A.6: The changed parameters for T2WPDIF
It can be calculated, the threshold ”IdMin” is 0.6*1000=600A in this case.
Since the current difference during the fault is around 500A in the simulation, the
T2WPDIF will not trip. The results are shown in Figure A.12.
17
(a) The normal readings from MU1
(b) Readings from MU1 during fault but no
trip
(c) Readings from MU2 during fault but no
trip
(d) After fault readings from MU2
Figure A.12: The trips of T2WPDIF