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been increased woth the applicatoon of transiStor suuotures
based on GaAs or related compounds. Using ()-2pm GaAs
MESFETs (I) and ()-25pm on,erted AIGaAs HEMTs (2],
operating frequencies or 26·5 GHz have been presented for
dynamic frequency dividers Stauc dividers based on AIGaAsGaAs-HBTs (3) and AllnAs-GalnAs-H8Ts (4] achieved frequency limits of 34-8 and 39·~GHz, respectively.
The design and performance or 3 dynamic frequency divider
operating in the 18 34 Gilt range based on AIGaAs/GaAs
AIGaAs quantum well uansostors was presented in Reference
5. As far as we know this was the best result ever reported for
HEMT circuits and similar to the frequency limit achie'ed by
usc of AIGaAs- GaAs·H BTs.
A further performance enhancement up to 51 GHz operation by the use of pseudomorphic AIGaAs/ lnGaAs
MODF£Ts will be presented here.
Al0 ,Ga0 •1 As/ l110 .uCia0.,As MODFF.T process : We have
developed a mix and match technology combining e-bcaon
with optical lithography whereby the e-bcam is used for
writing the gatc:s only. Mushroom-shaped gates were used to
reduce the resistance or O· IS1•m gates. The layer structure
including n '·cap, delta doped GaAs supply layer, AIGaAs
spacer and p~udomorphic lnGaAs channel was grown by
M BE [6]. Precise control of the threshold voltage was guar·
antccd by an AIGaAs etch stop u>ing a dry etch process. In
our process sequence we have !:!-type MODFETs, NiCr thin
film resistors, MIM capacitors. and two layers for intercon·
nections. The top layer can be fabricated as air bridges thus
reducing the capacitance.
COFC'Uit dtsogn · Fig. I sebematocally depocts the dynamic frc·
quency divoder. T"'o rong oscillators each consisting of one
•
SFV~
i ,~
I>.Jt~·
""'
fliB
f"ia. I C'lrru1t diagram ofd)MrrtJt frtqutrtl') d1lfdtr
2S--61 GHz DYNAMIC FREQUENCY DIVIDER
BASED ON 0·16,um T- GATE
AI 0 ., Ga0 •0 As/ln 0 .. .Ga0 .. . As MODFETs
f•troductro•. Very hogh speed frequenC} di•iders are of
oncreasong importance in a large number of system applications. The frequency limits or frequency divider circuits ha,·e
13th May 1993
Jr.,.r'
RtSults: Measurements carried out on the dynamic frequency
divider ga•e a lower limit for stable operation of 28GHz and
Srm.Jt"i)ll·
The dcsop and performance of a 23-SI GHz dynanllt frequctlt)'
dl\ldcr
based
on
ps<udomorphit
AI. 1Ga01Asln0 ,Ga• .,As MODFETs ,.;th 6-ISpm
mushroom·shaped gates are: pre2nted. n.e cirtun has 3
po"t:r con,umpuon of -440mW and a chip area of
'200 x 220pm 1•
ELECTRONICS LETTERS
•v + 6r.,) - ' </<(r,,v •
(2t 1
where 1 1 ~, and r., are the propagatoon delays of the inverter
and the source follower. respectively.
A. Thiede, P. Tasker, A. Hiilsmann, K. Kohler,
W. Bronner, M. Schlechtwcg, M. Betroth,
J. Braunstein and U. Nowotny
lndtxl"ffltrnu . Fitld-#.ft"Ct transistors. Tran..tisuws.
dut10f dh..ns ond mattrials
push pull onvcrter and three source followers were fed back
by transfer gates. A memory type Hipftop was used for data
storage during the period when the lransfer gates show high
resistance due to the low voltage applied to the clock input.
The inverter stages were built up in OCFL with passive
resistor load<, and push pull and soun.-e follower buffers were
realised by enhancement type MODFETs.
The circuit design was optimised by SPICE simulation
based on an 'in house' developed F'ET network model [71.
The operating frequency runge of the divider is gi'·en by
Vol. 29 No 10
a value of 51 GHz for the maximum input frequency. Fig. 2
shows the pulse diagram of the 51 GHz input and the
25 5GHz output. To the best of our knowledge this is the
highest input frequency ever reported for frequency divider
circuits on &n) technology.
The divider can operate ~Noth songle phase input. Both single
phase and doiTer<ntoal outputs are available.
The circuli runs at a pO"er supply of V00 = + J·S V and
Vss - -o-sV The required input •oltage swing tt less than
800mV at 28GH> and decreases as the frequency increases. A
power consumption of -440mW was measured for the
divider oncluding the output buffers. The chip size was
-200"
m,,m•.
933
Swnnulry: The design and performance of a dynamic frequency divider were presented. This digital IC demonstrates
;n
r-- -- r-- / ~
L~
v
v
-·- -- 1- --
""'·
-
-
Lb-. / 0..
../
--. -- -·-·
-'
out
~ -- ~
--- f-- -
~
'"
v
-- -- . -
f- ·-
--
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I=-
SAITO, T., 11\JJISHIRO, H. 1.. ICH IOKA, T.. TANAKA, K., N~HI, $., an<J
SANO. Y.: '0·251'm &ate inverttd HEMT• for an ult~•-·high speed
DCFL dynamic frequency divider'. IEEE.GaAs-lC-Symp., 1989.
San Diego, USA. pp. 117- 120
YA.MAUCHl, Y .• NA KAJIMA, 0., NA(iATA, K., ITO, HIROSHI, and ISH!~
'A 34·8GHz 1/4 Sialic frequency divider U$ing AIGaAs/
GaAs HBTs'. IEEE-GaAs-IC-Symp, San Diego. USA. 1989. pp.
121-124
JIJ:N:Sf....;, J. f •. HAt"tZI. M.. STANCHI NA, W , £.. METWEJI., R. A ., and
A.F.NSCH. o. &: '39·SGHz static frequency divider implemented in
AllnAs/GalnAS HBT technology'. IEEE-GaAs-IC-Symp.. Miamt
-ch, USA. 1992. pp. 101- t04
IIASHI, T.:
llUfDE. A., B.ERROTH, M.. NOWOTNY, V., S£18£1.. J.,. BOSCH, R., K0 HL£R,
K., RAYNOR. 8., and SCHNEIOEK. J.: 'An 18- 34GHz. d)·namic rre QUtnty divider based on o-21•m AJGaAS/GaAs/AlGaAs quanlumwetl transistors•. Int. Solid State Circuits Conf.. San Francisco.
USA, 1993, pp. 176 177
BRAUZio'STEIN, J., TASKER. P-. KOHI. ER. K. , SCIIWF.I ZF.R, T., H0LS.\(ANN,
lOps/diVISIOn
,. .. SCHLECHTW£0, M.. and KAUiliL. a.: ·rnvesrigat1on of transpott
Fig. 2 Measured pulse diag·ram ()/51 Gl-fz input ond appropriaJe Otdptlt
ofdynamicfrrquency divider
the ability of our pseudomorphic A10 . 1Ga... As/ ln0 .,.
Ga 0 .,.As MODFETs with 0·151tm mushroom-shaped gates.
phenome.na in p!<udomorphic MOOFETs', Int. Symp. GaAs and
Rclattd Compound•. Seattl<. 1991. pp. 161-166
8£R.Rorn. M.: ·circuit simulator for heteros:lructure fic:ld effect transislors'. PhD Thesis, Ruhr-Uni\'tt"Sily 8ochum, 1991
Stable operation was achieved in the frequency range 2851 GHz with a power consumption of440mW.
Acknowledgments: This work was a group effort and the
authors are grateful to the entire staff of the laboratory. We
especially want to thank H. S. Rupprecht for his directing and
continuous encouragement, and T. Jakobus for his expert
technology management. The German Federal Ministry of
Research and Technology is acknowledged for the financial
support through the DFE-project TK357/9.
<!:) lEE 1993
AL·ALAOUI, M. A. :
'Novel digital integrator and diffcrcntiator',
Efectro11. Lett., 1993. 29, (4), pp. 376- 378
1tod Apnl /993
A. Thiede. P. Ta~br, A. HU.lsmann. K. KOhler. W. Bronner, M. Schle·
chtweg. M. Bcrroth, J. Braunstein and U. Nowotny (Fraunhbftr•ln.fti·
turt for Applitd Solid Start Physics. Tullastr. 71. D-78(}(1 Frelburg.
Gtrmany)
References
JENSE.N, J. F., 5..\I.MON, L. C .. D£AK1K 0. S., and DELANEY, M. J, :
'26 0Hz GaAs room-temperature dynam•c dovidcr circuit'. IEEEGaAs-lC-Symp, Portland. USA. 1987. pp. 201 - 203
934
ERRATA
Authors ' corrections
The third and founh subcap1ions to Fig. 1 should read:
0 rectangular
• trape-toidal
ELECTRONICS LETTERS
13th May 1993
Vol. 29 No. 10