Download The Effect of Short Channel on Nanoscale SOI MOSFETs

African Physical Review (2008) 2 Special Issue (Microelectronics): 0038
80
The Effect of Short Channel on Nanoscale SOI MOSFETs
D. Rechem and S. Latreche
Laboratoire Hyperfréquence et Semi-conducteur (L.H.S), Département d’Electronique,
Faculté des Sciences de l’ingénieur, Université Mentouri de Constantine, Algérie
2.
10
3
10
2
10
1
10
0
Results
Vds=0.6V
10
-1
10
-2
10
-3
10
-4
L CH=6nm
L CH=8nm
L CH=10nm
L CH=12nm
L CH=14nm
L CH=16nm
L CH=18nm
L CH=20nm
L CH
0,0
0,1
0,2
0,3
0,4
0,5
0,6
Vgs [Volt]
Fig.1: Ids vs. Vgs for Vds=0.6V
with different channel lengths.
Leakage current (I-off) [A/m]
Double gate silicon-on-insulator (DG SOI) devices
have recently been of great interest, particularly for
the investigation of sub-10nm field-effect transistor
[1]-[3]. As the channel length is reduced from one
transistor generation to the next, the susceptibility
of the transistor to short-channel effects (SCE) is
monitored in several ways such as threshold
voltage (VTH) roll-off, sub-threshold voltage swing,
and the drain induced barrier low, the channel
length decreases and becomes crucial in deep-submicrometer technologies. As an indicator of these
short channel effects, the threshold voltage and
sub-threshold voltage swing has been extensively
investigated [4]-[7].
In order to maintain a tolerable degree of short
channel effect [8], it becomes necessary to reduce
the SOI film thickness. Reducing the SOI film
thickness causes a high electric field in the
perpendicular direction to the Si/SiO2 interface,
strongly confining charge carriers in the channel.
Several interesting models have been proposed for
the classical (i.e., without quantum effects) drain
current [9]-[11]. Carrier quantization effects have
been considered for the first time in [12].
Therefore, classical models that disregard these
effects are no longer suitable for describing sub
10nm MOSFETs. Therefore, we use quantum
mechanical transport models for n-channel
MOSFETs based on the self-consistent Schrödinger
and Poisson equations for the simulation of short
channel effects on the performance of DGMOSFET. In addition to it, the model is continuous
over all gate and drain bias ranges, which makes it
very suitable to simulate novel silicon transistor
structures.
Drain current Ids [A/m]
Introduction
Vds=0.6 V
Vgs=0 V
0,1
0,01
1E-3
1E-4
4
6
8
10
12
14
16
18
20
22
L CH [nm]
Fig.2: Leakage current Ioff vs. different
channel lengths.
0,25
Vds=0.6 V
Threshold voltage (VTH) [Volt]
1.
0,20
0,15
0,10
0,05
0,00
6
8
10
12
14
16
18
L CH [nm]
Fig.3: Threshold voltage vs. different
channel lengths.
20
African Physical Review (2008) 2 Special Issue (Microelectronics): 0038
Subthreshold swing (S) [Volt/decad]
0,090
Vds=0.6 V
0,085
0,080
0,075
0,070
0,065
0,060
ideal slope
0,055
4
6
8
10
12
14
16
18
20
22
LCH [nm]
Fig.4: Sub-threshold swing vs. different
Channel lengths.
3.
Conclusion
A two dimensional self consistent Poisson
Schrödinger model is used with appropriate
boundary conditions to explore the short channel
effect in double gate MOSFET as channel length
varied in the range of 20nm down to 6nm. The
model is particularly dedicated to ultra-scaled
devices. The short channel behaviour of the double
gate MOSFET is evaluated based on the threshold
voltage, sub-threshold swing and leakage current
variation with channel length. It is found that those
parameters, which characterize SCE, present a
significant degradation when decreasing the
channel length.
References
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