Download VLSI Design Homework 2

VLSI Design Homework #3
Issue Date: 04/19/2002
Due Date: 05/03/2002
【Target: Layout practice with more complicated circuits】
【Description】: In Homework 2, you have learned the basic layout skills, and several
simple logical gates are drawn with their netlists being extracted for simulation. In
Homework 3, more complicated circuits are drawn with the concept of module
reusing. Likewise, the SPICE simulation is required to prove the correctness of the
drawn circuit.
【Objective】:
1. A modular layout circuit design and reusing it for a hierarchical design.
2. Rise time, fall time, and delay time observation
3. SPICE simulation with transient analysis
【Homework content】:
1. Draw the layout of the 1-bit full adder circuit with Cadence Virtuoso. Make sure
there is no DRC error. Color page plate 7 of the textbook could be referred.
2. There are two outputs of the full adder, the Sum and Carry-out. Extracted the
netlist of the 1-bit full adder and conduct the SPICE simulation to find the Rise
Time and Fall Time of these two outputs of the 1-bit full adder. Also calculate
the Rising Delay Time and Falling Delay Time related to the Rise Time and Fall
Time, respectively.
3. Make your 1-bit full adder a basic module to construct a 4-bit ripple adder.
Please open another view and instance the 1-bit full adder 4 times. Additional
interconnections are needed drawing to connect the inputs and outputs of the
instances.
4. Make one input vector as 4’b0001 and the other vector as 4’b1111 for the 4-bit
ripple adder. Use the transient analysis mode of the SPICE simulator to
determine the delay time (also the worst-case delay along the critical path) of the
4-bit ripple adder. Is the delay time 4 times of that calculated from the 1-bit full
adder? Discuss it briefly.
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【Checklist】:
1. Layout view of the 1-bit full adder.
2. The rise time, fall time, rising delay time, falling delay time of the output nodes of
the 1-bit full adder — Sum and Carry-out. SPICE simulation results must be
provided.
3. Layout view of the 4-bit ripple adder.
4. The delay time of the 4-bit ripple adder. SPICE simulation result must be
provided.
【Hint】
1. For the SPICE transient analysis, one may refer to the SIMetrix User Manual.
2. Piece-wise linear voltage source and pulse voltage source may be used in the
SPICE simulation.
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