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PRESENTED BY:
ADITYA DAYAL
M-Tech Student
ITM University, Gwalior
Contents 1. Introduction
2. Basic building block
3. Ripple Carry Adder
4. Application
5. Advantages
6. Disadvantages
7. Conclusion
8. References
Introduction  Carry Select adder is a way to implement an
adder.
It is a logic element that computes (n+1) bit
sum of two n- bit number.
 It is a simple implementation.
 Carry Select adder consists of –
- Ripple carry adder
- Multiplexer
Basic building block –
The basic building block of a carry-select adder,
where the block size is 4. Two 4-bit ripple carry adders
are multiplexed together.
Adding two n- bit no. with CSA is done with two
adders.
Cont.......
To perform calculation, twice two ripple carry adders
are used.
 One time with assumption of carry being zero and
the other assuming one.
The resulting carry and sum bits are selected by the
carry-in.
After the two results are calculated, the correct sum,
as well as the correct carry, is then selected with the
multiplexer once the correct carry is known.
Ripple Carry Adder -
The ripple carry adder is constructed by cascading each
single-bit full-adder.
In the ripple carry adder, each full-adder starts its
computation till previous carry-out signal is ready.
Cont. The delay of adder increases linearly with increase in
number of bits.
the critical path delay in a carry ripple adder is
determined by its carry-out propagation path.
the CSA is not area efficient because it uses multiple
pairs of Ripple Carry Adders (RCA) to generate partial
sum and carry by considering carry input Cin=0 and
Cin=1, then the final sum and carry are selected by the
multiplexers.
Application CSA is used in many data-processing
processors to perform fast arithmetic functions
 The CSA is used in many computational systems to
alleviate the problem of carry propagation delay by
independently generating multiple carries and then select
a carry to generate the sum.
Advantages  Carry select adder is very fast, being able to
calculate all the input bits nearly simultaneously.
 In digital adders, the speed of addition is limited
by the time required to propagate a carry through
the adder.
Disadvantages  More costly than other adders .
 Designing is complex than simple adders.
Conclusion  The reduced number of transistors of this work offers
the great advantage in the reduction of area and also
the total power.
 The area of the 8-bit and16-b modified CSA are
significantly reduced by 9.7% and 15.56%
respectively.
 The total power consumption is reduced by 7.6% and
10.5% respectively.
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References –
[1]B. Ramkumar and Harish M Kittur, “Low-Power and Area-Efficient
Carry Select Adder” IEEE TRANSACTIONS ON VERY LARGE
SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 2,
FEBRUARY 2012
[2]Padma Devi, Ashima Girdher, Balwinder Singh, “Improved Carry
Select Adder with Reduced Area and Low Power Consumption”
International Journal of Computer Applications (0975 – 8887)Volume 3 –
No.4, June 2010
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