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Solving Op Amp Stability Issues Part 3 (For Voltage Feedback Op Amps) Tim Green & Collin Wells Precision Analog Linear Applications 1 Appendix Index Appendix No. Title 1 Op Amp Output Impedance Pole and Zero: 2 Magnitude and Phase on Bode Plots 3 Dual Feedback Paths and 1/β 4 Non-Loop Stability Problems Description/Stability Technique Zo vs Zout difference and datasheet curves Closed loop magnitude and phase shifts of a signal frequency due to poles and zeroes on a Bode Plot How to avoid problems when using dual feedback paths for stability compensation Oscillations and causes not seen in loop gain stability simulations 5 Riso (Output Cload) Stability: Isolation resistor with feedback at op amp 6 High Gain and CF (Output Cload) Stability : High gain circuits and a feedback capacitor 7 CF Non-Inverting (Input Cload) Stability : Non-inverting gain and feedback capacitor Output Cload, closed loop gain >20dB Input Cload, non-inverting gain, large value input resistor Stability: Inverting gain and feedback capacitor Input Cload, non-inverting gain, large value input resistor, photodiode type circuits 8 When to use the Stability Technique Zo is a key parameter for stability analysis Magnitude and phase shift at a frequency of interest for closed loop poles and zeroes Key tool in analyzing op amp circuits that use dual feedback for stability Check all designs to avoid oscillations that do not show up in SPICE simulation Output Cload, Note: accuracy of output is dependent upon load current 9 CF Inverting (Input Cload) Noise Gain Inverting and Non-Inverting (Output Cload) 10 Noise Gain and CF (Output Cload) Stability: Noise Gain added by input R-C network Stability: Noise Gain (input R-C) and feedback capacitor 11 13 Output Pin Compensation (Output Cload) Riso w/Dual Feedback (Output Cload) - Zo, 1/β, Aol Technique Riso w/Dual Feedback (Output Cload) - 1/β, Loaded Aol Technique Stability: Series R-C on op amp output to ground Stability: Isolation resistor with two feedback paths analysis by Zo, 1/β, and Aol technique Stability: Isolation resistor with two feedback paths analysis by 1/β, and Loaded Aol technique 14 Riso w/Dual Feedback plus RFx (Output Cload) Stability: Isolation resistor with two feedback paths - 1/β, Loaded Aol Technique analysis by 1/β, and Loaded Aol technique Output Cload, closed loop gain <20dB Output Cload, Loaded Aol has a second pole located >20dB Output Cload, no access to -input, monolithic, integrated difference amplifiers, complex feedback where not practical to use -input Output Cload, some additional Vdrop across isolation resistor is okay, accurate Vout at load Output Cload, some additional Vdrop across isolation resistor is okay, accurate Vout at load Output Cload, some additional Vdrop across isolation resistor is okay, accurate Vout at load. RFx can provide wider BW control at output load. 15 Discrete Difference Amplifier (Output Cload) Output Cload, difference amp configuration, 2 any closed loop gain 12 Stability: Balanced use of noise gain (series R-C) 4) Non-Loop Stability Problems Non-Loop Stability • Loop Frequencies • RB+ • PCB Traces • Supply Bypass • Ground Loops • Output Stage Oscillations Non-Loop Stability Oscillations NOT predicted by Loop Gain (Aolb) Analysis or SPICE Simulations 4 Non-Loop Stability: Loop Frequency Definitions fcl: Where Loop Gain (Aolβ) = 1 Aol 100 fGBW: Where Op Amp Aol Curve crosses 0dB (Unity Gain Bandwidth) A (dB) 80 fGBW fcl 60 b 40 VOUT/VIN 20 SSBW (Small Signal BandWidth) 0 1 10 100 1k 10k 100k 1M 10M Frequency (Hz) 5 Non-Loop Stability: ? Diagnostic Questions ? Frequency of oscillation (fosc)? When does the oscillation occur? Oscillates Unloaded? Oscillates with VIN=0? 6 Non-Loop Stability: RB+ Resistor fosc < fGBW oscillates unloaded? -- may or may not oscillates with VIN=0? -- may or may not RF 100k RI 100k RB+ is Ib current match resistor to reduce Vos errors due to Ib. Ib - + VIN - VOUT Ib + RB+ 49.9k RB+ can create high impedance node acting as antenna pickup for unwanted positive feedback. + VNOISE PROBLEM RF - 100k RI 100k RF - 100k SOLUTION RI 100k VOUT + VIN - + RB+ 49.9k CB+ 0.01F or 0.1F If you use RB+ bypass it in parallel with 0.1μF capacitor. + VIN - - VOUT + RB+ SOLUTION Many Op Amps have low Ib so error is small. Evaluate DC errors w/o RB+. 7 Non-Loop Stability: PCB Traces fosc < fGBW oscillates unloaded? -- may or may not oscillates with VIN=0? -- may or may not RI RF + + Rs VIN - VOUT GND DO NOT route high current, low impedance output traces near high impedance input traces. Unwanted positive feedback path. DO route high current output traces adjacent to each other (on top of each other in a multi-layer PCB) to form a twisted pair for EMI cancellation. 8 Non-Loop Stability: Supply Lines fosc < fGBW oscillates unloaded? -- no oscillates with VIN=0? -- may or may not Ls PROBLEM Gain Stage PROBLEM Power Stage +vs RL IL - Rs + CL -vs Load current, IL, flows through power supply resistance, Rs, due to PCB trace or wiring. Modulated supply voltages appear at Op Amp Power pins. Modulated signal couples into amplifier which relies on supply pins as AC Ground. Power supply lead inductance, Ls, interacts with a capacitive load, CL, to form an oscillatory LC, high Q, tank circuit. 9 Non-Loop Stability: Proper Supply Line Decouple CLF SOLUTION CLF: Low Frequency Bypass < 4 in <10 cm RHF 10μF / Amp Out (peak) Aluminum Electrolytic or Tantalum CHF +VS < 4 in (10cm) from Op Amp - CHF: High Frequency Bypass + 0.1μF Ceramic -VS < 4 in <10 cm Directly at Op Amp Power Supply Pins CHF RHF RHF: Provisional Series CHF Resistance 1Ω < RHF < 10Ω CLF Highly Inductive Supply Lines 10 Non-Loop Stability: Ground Loops RI fosc < fGBW oscillates unloaded? -- no oscillates with VIN=0? -- yes RI RF RF + - - +VS VOUT VIN + -VS - RGw RL IL RGx + RGy “Ground” Ground loops are created from load current flowing through parasitic resistances. If part of VOUT is fed back to Op Amp +input, positive feedback and oscillations can occur. SOLUTION VIN PROBLEM RGv “Star” Ground Point - +VS VOUT + -VS RL RG Parasitic resistances can be made to look like a common mode input by using a “Single-Point” or “Star” ground connection. 11 Non-Loop Stability: Output Stages fosc > fGBW oscillates unloaded? -- no oscillates with VIN=0? -- no RF 100k L O A D RI 100k + VIN VOUT + RSN 10 to 100 - CSN F to 1F -VS PROBLEM Some Op Amps use composite output stages, usually on the negative output, that contain local feedback paths. Under reactive loads these output stages can oscillate. SOLUTION The Output R-C Snubber Network lowers the high frequency gain of the output stage preventing unwanted oscillations under reactive loads. 12 5) Riso (Output Cload) VFB 353.900776nV Loaded Aol CT 1TF LT 1TH + V+ T 140 Vtest V+ 15V - -20dB/decade 120 VOUT 353.900776nV Loaded Aol = VOUT / VFB For AC Test VFB = Vtest Loaded Aol = VOUT V- 15V fp1 Aol Pole Low Frequency 100 80 fp2 Loaded Aol Additional Pole 40 1/ 20 + + U1 OPA627E CLoad 1uF V+ V- 60 Gain (dB) V- Loaded Aol due to CLoad -40dB/decade Rate-of-Closure 40dB/decade 0 -20 STABLE fcl -40 -60 -80 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 14 Loaded Aol Model CT 1T V+ LT 1T Vtest V+ 15 VFB + + Ro 54 V- Loaded Aol Aol - VOUT + V- 15 + U1 OPA627E CLoad 1u CLoad 1u V+ VLoaded Aol = VOUT / VFB For AC Test VFB = Vtest Loaded Aol = VOUT LT Open - - + + + CT Short Vtest Ro 54 Loaded Aol Aol 1M CLoad 1u 15 Loaded Aol Model T fp2 0 0.00 Ro 54 Aol Loaded Aol GainGain(dB) (dB) + -20 -20.00 -40 -40.00 CLoad 1u Loaded AOL Pole -60 -60.00 -80 -80.00 0 0.00 Phase (degrees) Phase [deg] Loaded Aol Pole Equation 1 fp 2 2 Ro CLoad -45.00 -45 -90.00 -90 1.00 1 10.00 10 100.00 100 1.00k 1k 10.00k 100.00k 10k 100k Frequency (Hz) Frequency (Hz) 1.00M 1M 10.00M 10M 100.00M 100M 16 Loaded Aol Model fp2 120 100 100.00 T 120.00 Aol 20 0 0.00 -20 -20.00 -40 -40.00 20.00 -60 -60.00 + 135.00 135 -80 -80.00 0 0.00 -45.00 -45 90 90.00 45 45.00 0 1.00 1 Aol Load -40 -40.00 180.00 180 Phase (degrees) Phase [deg] -20 -20.00 GainGain(dB) (dB) GainGain(dB) (dB) fp1 60.00 0 0.00 PhasePhase(degrees) [deg] 80 60 40 40.00 80.00 T 0.00 10.00 10 100.00 100 1.00k 1k 10.00k 100.00k 10k 100k Frequency (Hz) 1.00M 1M Frequency (Hz) 120 120 100 100 10.00M 10M 100.00M 100M -90.00 -90 1.00 1 10.00 10 100.00 100 1.00k 1k 10.00k 100.00k 10k 100k Frequency (Hz) Frequency (Hz) 1.00M 1M 10.00M 10M fp1 80 80 60 60 40 40 Loaded Aol fp2 20 20 00 -20 -20 -40 -40 180.00 180 PhaseVoltage (degrees) (V) = GainVoltage (dB) (V) T 135.00 135 90 90.00 45 45.00 0 0.00 1.00 1 10.00 10 100.00 100 1.00k 1k 10.00k 100.00k 10k 100k Frequency (Hz) Frequency (Hz) Note: Addition on Bode Plots = Linear Multiplication 1.00M 1M 10.00M 10M 100.00M 100M 17 100.00M 100M VFB LT 1TH + Loaded Aol – Loop Gain & Phase CT 1TF V+ Vtest V+ 15V V- VOUT Loop Gain (Aol ) = VOUT V- 15V + + U1 OPA627E CLoad 1uF V+ V- STABLE Phase Margin at fcl 18 Riso Compensation Riso will add a zero in the Loaded Aol Curve V+ VV+ 15V Riso 6Ohm - + U1 OPA627E VIN V- 15V VOUT + + CLoad 1uF V+ VOA V- 19 Riso Compensation Results T CT 1TF + V- Vtest V+ 15V Riso 6Ohm - 140 U1 OPA627E Loaded Aol with Riso Compensation Loaded Aol = VOA fp1 Aol Pole Low Frequency 80 V+ VOA V- -40dB/decade 60 fp2 Loaded Aol Additional Pole 40 1/ 20 + CLoad 1uF V- 15V 100 VOUT + -20dB/decade 120 Gain (dB) LT 1TH V+ fz1 Loaded Aol Riso Compensation Additional Zero -20dB/decade Rate-of-Closure 20dB/decade 0 -20 fcl STABLE -40 -60 -80 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 20 Riso Compensation Theory V+ VOA V- V+ 15 LT 1T - Riso 6 VOUT + V- 15 + U1 OPA627E CLoad 1u V+ Vtest V- Ro 54 + + CT 1T Loaded Aol Aol Riso 6 CLoad 1u LT Open Loaded Aol - - + + + CT Short Vtest Ro 54 Riso 6 VOUT Aol 1M CLoad 1u 21 Riso Compensation Theory T 0 0.00 fp2 Loaded Aol Aol Riso 6 fz1 GainGain(dB) (dB) + Ro 54 -20.00 -20 -40 -40.00 CLoad 1u Loaded Aol (s) 1 CLoad Riso s 1 (Ro Riso) CLoad s -45.00 -45 -90.00 -90 1.00 1 Pole : fp2 Phase (degrees) Phase [deg] Transfer Function 0 0.00 1 2(Ro Riso) CLoad 10.00 10 100.00 100 1.00k 1k 10.00k 100.00k 10k 100k Frequency (Hz) Frequency (Hz) 1.00M 1M 10.00M 10M 100.00M 100M Zero : fz1 1 2 Riso CLoad 22 Riso Compensation Theory 120 100 100.00 T 120.00 Aol Aol Load -40 -40.00 180.00 180 Phase (degrees) Phase [deg] fz1 -20.00 -20 20 0 0.00 -20 -20.00 -40 -40.00 20.00 + 135.00 135 90 90.00 45 45.00 0 1.00 1 fp2 GainGain(dB) (dB) GainGain(dB) (dB) fp1 0 0.00 0 0.00 Phase (degrees) Phase [deg] 80 60 60.00 40 40.00 80.00 T -90.00 -90 1.00 1 0.00 10.00 10 100.00 100 1.00k 1k 10.00k 100.00k 10k 100k Frequency (Hz) Frequency (Hz) 120 100.00 100 1.00M 1M 10.00M 10M -45.00 -45 100.00M 100M 10.00 10 100.00 100 1.00k 1k 10.00k 100.00k 10k 100k Frequency (Hz) Frequency (Hz) 1.00M 1M 10.00M 10M T 120.00 fp1 80 60.00 60 40.00 40 Loaded Aol GainGain(dB) (dB) 80.00 20 0.00 0 -20.00 -20 -40.00 -40 20.00 180.00 180 PhasePhase(degrees) [deg] = fz1 fp2 135.00 135 90.00 90 45.00 45 0.00 0 1.00 1 10.00 10 100.00 100 1.00k 1k 10.00k 10k Frequency (Hz) 100.00k 100k Frequency (Hz) Note: Addition on Bode Plots = Linear Multiplication 1.00M 1M 10.00M 10M 100.00M 100M 23 100.00M 100M Riso Compensation Design Steps 1) Determine fp2 in Loaded Aol due to CLoad A) Measure in SPICE with CLoad on Op Amp Output 2) Plot fp2 on original Aol to create new Loaded Aol 3) Add Desired fz2 on to Loaded Aol Plot for Riso Compensation A) Keep fz1 < 10*fp2 (Case A) B) Or keep the Loaded Aol Magnitude at fz1 > 0dB (Case B) (fz1>10dB will allow for Aol variation of ½ Decade in Unity Gain Bandwidth) 4) Compute value for Riso based on plotted fz1 5) SPICE simulation with Riso for Loop Gain (Aolb) Magnitude and Phase 6) Adjust Riso Compensation if greater Loop Gain (Aolb) phase margin desired 7) Check closed loop AC response for VOUT/VIN A) Look for peaking which indicates marginal stability B) Check if closed AC response is acceptable for end application 8) Check Transient response for VOUT/VIN A) Overshoot and ringing in the time domain indicates marginal stability B) Determine if settling time is acceptable for end application 24 CT 1TF 1),2) Loaded Aol and fp2 LT 1TH + V+ V- Vtest V+ 15V Riso 0Ohm - U1 OPA627E VOUT + + CLoad 2.9nF V- 15V Loaded Aol = VOA V+ VOA V- 25 Case A, CLoad=1uF, fp2=2.98kHz Case B, CLoad=2.9nF, fp2=983.37kHz 3) Add fz1 on Loaded Aol T 140 120 100 Loaded Aol Add Riso Compensation 2.98kHz 80 Voltage (V) 60 fp2 Case B 983.37kHz CLoad=2.9nF fp2 Case A CLoad=1uF 40 20 fz1 29.8kHz Case A CLoad=1uF 0 4.07MHz fz1 Case B CLoad=2.9nF -20 -40 -60 -80 1 10 100 Case A, CLoad=1uF, fz1=29.8kHz Case B, CLoad=2.9nF, fz1=4.07MHz 1k 10k Frequency (Hz) 100k 1M 10M 26 4) Compute Value for Riso Case A, CLoad=1uF, fz1=29.8kHz Case B, CLoad=2.9nF, fz1=4.07MHz Zero : Zero, Case A, CLoad 1F, fz1 29.8kHz : 1 2 Riso CLoad 1 Riso 2 fz1 CLoad 1 2 Riso CLoad 1 Riso 5.34 use 5.36Ω 2 29.8kHz 1F fz1 fz1 Zero, Case B, CLoad 2.9nF, fz1 4.07MHz : 1 fz1 2 Riso CLoad 1 Riso 13.48 use 13.7Ω 2 4.07MHz 2.9nF 27 CT 1TF 5),6) Loop Gain, Case A LT 1TH + V+ V- Vtest V+ 15V Riso 5.36Ohm - U1 OPA627E VOUT + + CLoad 1uF V- 15V V+ VOA Loop Gain (Aol ) = VOA V- Phase Margin at fcl = 87.5 degrees 28 CT 1TF 5),6) Loop Gain, Case B LT 1TH + V+ V- Vtest V+ 15V Riso 13.7Ohm - U1 OPA627E VOUT + + CLoad 2.9nF V- 15V V+ VOA Loop Gain (Aol ) = VOA V- Phase Margin at fcl = 54 degrees 29 V+ 7) AC VOUT/VIN, Case A VV+ 15V Riso 5.36Ohm - U1 OPA627E VOUT + + + CLoad 1uF V- 15V VIN V+ VOA VT 20 VOA -3dB=1.58MHz Gain (dB) 0 VOUT/VIN Riso Compensation Case A, CLoad=1uF -20 VOUT -3dB=30.44kHz -40 -60 -80 0 Phase [deg] -45 -90 -135 -180 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 30 V+ 8) Transient Analysis, Case A VV+ 15V Riso 5.36Ohm - U1 OPA627E T VOUT + + 10.00m + VIN CLoad 1uF V- 15V VOUT / VIN Transient Analysis Case A, CLoad=1uF VIN V+ VOA V- -10.00m 10.27m VOA -10.27m 10.01m VOUT -10.01m 0 500u 1m Time (s) 2m 2m 31 Riso Compensation: Key Design Consideration Accuracy of VOUT depends on Load Current Light Load Current V+ VOA 5V V- ILoad 4.970179mA V+ 15V - + Riso 6Ohm + U1 OPA627E VIN 5V + A CLoad 1uF V+ V2 15V VOUT 4.970179V RLoad 1kOhm V- V+ Heavy Load Current VOA 5V V- ILoad 24.271845mA - V+ 15V + VIN 5V Riso 6Ohm + U1 OPA627E V+ + A CLoad 1uF VOUT 4.854369V RLoad 200Ohm V2 15V V32 6) High Gain and CF (Output Cload) 33 Original Circuit: Transient Response V+ RI 499 RF 49.9k V- C2 1u V1 15 - V2 15 + C3 1u Vo + + U1 OPA627E CLoad 1u VG1 V+ V- 20.00m Voltage (V) T Vin Vo 0.00 0.00 100.00u Time (s) 200.00u 34 High-Gain and CF Compensation Design Steps 1) Break the loop and plot Aol and 1/Beta A. Determine fp2 in Loaded Aol due to Cload B. Determine fcl of original Aol and 1/Beta C. Determine f(Aol=0dB) f(Aol=0dB): the frequency where the Loaded Aol Magnitude = 0dB 2) Add Desired fp3 to 1/Beta for CF compensation (fz1 will occur when 1/Beta = 0dB) A) Keep fp3 < *fcl and fz1 < f(Aol=0dB) B) To prevent AolB phase dip, Keep fp3 < 10*fp2 3) Select value for CF based fp3, fcl, and f(Aol=0dB) 4) SPICE simulation with Riso for Loop Gain (Aolb) Magnitude and Phase 5) Adjust CF if greater Loop Gain (Aolb) phase margin desired 6) Check closed loop AC response for VOUT/VIN A) Look for peaking which indicates marginal stability B) Check if closed AC response is acceptable for end application 7) Check Transient response for VOUT/VIN A) Overshoot and ringing in the time domain indicates marginal stability 35 1) Original Circuit: Break the Loop Vfb RI 499 RF 49k C1 1T + V+ C2 1u VV1 15 Vo + C3 1u Vin - U1 OPA627E V2 15 L1 1T + CLoad 1u V+ V- 36 2) Compensate with 1/Beta Pole (CF) 37 3) 1/Beta Pole/Zero Equations Vout 1/Beta Transfer Function: Vout(s) = RI+CF RI RF s + Vfb(s) RF+RI+(CI+CF) RI RF s DC 1/Beta: RF CF Vout Vout(s) RF s=0, = 1+ Vfb(s) RI Vfb RI 1/Beta Pole Frequency: fp3 = 1 2 pi RF CF CI => Solve for CF 1 C F= 2 pi RF fp3 CI is the equivalent input capacitance of the op amp. (See Appendix #7) 1/Beta Zero Frequency: 1 fz1= 2 pi (RI ll RF) (CF+CI) => Solve for CF C F= 2 1 (RI ll RF) fz1 -CI 38 V1 15 From Step 1: fp2 = 2.98 kHz fcl = 22.67 kHz f(Aol=0dB) = 222.7 kHz V2 15 VCF 141p For stability: A) Keep fp3 < *fcl and fz1 < f(Aol=0dB) RI 499 RF 49.9k Calculate CF(min) from fp3 < *fcl : V- 1 - 49.9k 22.67kHz = 141pF Vo + CFmin= 2 1 = RF fp3 2 + + U1 OPA627E VG1 V+ Calculate CF(max) from fz1 < f(Aol=0dB) : CFmax= 2 C3 1u 3) Select CF to Compensate Circuit C2 1u V+ 1 -C = = (RI ll RF) fz1 I 2 1 (49.9k ll 499 ) 222.7kHz -10pF = 1.44nF B) To prevent AolB phase dip, Keep fp3 < 10*fp2 CLoad 1u 4),5) Plot Aol and 1/Beta for Compensated Circuit 40 6) Plot Compensated Closed-Loop Gain CF 1.44n RI 499 RF 49.9k V- + Vo + + U1 OPA627E CLoad 1u VG1 V+ C2 1u V+ C3 1u V1 15 V2 15 V- 41 7) Plot Compensated Transient Response CF 1.44n C2 1u V+ V1 15 RI 499 RF 49.9k C3 1u V- Vo + V2 15 V- + + U1 OPA627E VG1 CLoad 1u V+ 42 High Gain and CF Summary 1) Select CF between CF(min) and CF(max) for stability 2) CF(min) and CF(max) produce similar phase-margins 3) CF(min) will have the largest closed-loop bandwidth and fastest transient response 4) CF(max) will produce the smallest closed-loop BW and the slowest transient response 5) Selecting a value between CF(min) and CF(max) will produce the most robust design 43 7) CF Non-Inverting (Input Cload) 44 Op Amp Input Capacitance VEE 18V INCcm- 7pF Cdiff 10pF IN+ + U1 OPA140 VOUT + Ccm+ 7pF OPA140 - Input Capacitance VCC 18V 45 RI 90kOhm RF 180kOhm Op Amp Input Capacitance VFB VOUT 1 VOUT b VFB b V1 18V Ccm- 7pF Cdiff 10pF + VOUT + U2 OPA140 VOUT RF 180kOhm VFB + V2 18V Ccm+ 7pF Cin_eq 17pF VIN RI 90kOhm VFB RI 90kOhm RF 180kOhm Cin_eq 17pF V3 18V + VOUT + U3 OPA140 V4 18V 46 Equivalent Input Capacitance and b VOUT (Set to 1V) RF 180kOhm 1/β Computation : 1 RF (RI // X ) β RI // X Cin_eq b VFB Cin_eq 17pF RI 90kOhm Cin_eq 1 s Cin _ eq RF RI RF RI Cin _ eq 1 RF RI (after simplification) β RI 1 RF RI RF 180k DC 1 1 3 9.54dB β RI RI 90k 1 1 1 zero: fz1 156kHz β 2π Cin_eq (RF // RI) 2π 17pF (180k // 90k) 47 CF Compensation Design Steps 1) Determine fz1 in 1/b due to Cin_eq A) Measure in SPICE OR B) Compute by Datasheet CDIFF and CCM and Circuit RF and RI 2) Plot 1/b with fz1 on original Aol 3) Add Desired fp1 on 1/b for CF Compensation A) Keep fp < 10*fz B) Keep fp < 1/10 * fcl 4) Compute value for CF based on plotted fp 5) Check CF Compensation by 1/β plot on Aol 6) SPICE simulation with CF for Loop Gain (Aolb) Magnitude and Phase 7) Adjust CF Compensation if greater Loop Gain (Aolb) phase margin desired 8) Check closed loop AC response for VOUT/VIN A) Look for peaking which indicates marginal stability B) Check if closed AC response is acceptable for end application 9) Check Transient response for VOUT/VIN A) Overshoot and ringing in the time domain indicates marginal stability 48 VFB 1),2),3) Plot Aol, 1/b, Add fp in 1/b for Stability T Aol = Vout/VFB 1/ = 1/VFB Loop Gain = Vout 140 CT 1TF RF 180kOhm + LT 1TH RI 90kOhm V2 18V Aol 120 + Vout + 100 V1 18V 80 Gain (dB) U1 OPA140 OPA140 Aol and 1/ for High Value RF & RI 60 fz 156kHz +3dB 40 1/ [A] 20 STABLE fcl [B] 0 -20 1/ Add fp here? A:(128.264983; 9.542429) B:(156k; 12.552628) -40 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 49 VG1 4) Compute Value for CF based on location of fp CF 8.5pF 1/β Computation : 1 (RF // X ) (RI // X β RI // X VFB CF RI 90kOhm RF 180kOhm Cin_eq V3 18V Cin_eq 17pF - VOUT + + + U3 OPA140 V4 18V VIN CF 8.5pF VFB RI 90kOhm RF 180kOhm Cin_eq 17pF VOUT Cin_eq ) Note: Location of fz changes when CF is added 1 (Cin _ eq CF) s RI RF Cin _ eq CF 1 RF RI after simplification b CF s 1 RF CF 1 RF RI RF 180k DC 1 1 3 9.54dB β RI RI 90k 1 1 zero: fz β 2π (Cin_eq // CF)(RF // RI) 1 1 zero:fz 104kHz β 2π (25.5pF)(180k // 90k) 1 1 pole: fp β 2π CF RF 1 1 pole: fp 104kHz β 2π 8.5pF 180k 50 4) Compute Value for CF based on location of fp Maximum Bandwidth CF Compensation for Cin For maximum Closed Loop Bandwidth for VOUT / VIN: 1) CF needs to compensate input capacitance of Ccm- only since gain effects of Cdiff are nulled out (Similar to Non-Inverting Noise Gain op amp configuration) 2) Stability and phase margin are still determined by Cin_eq (Cdiff // Ccm-) Complete Circuit Loop Gain Model Closed Loop VOUT / VIN Model CF 3.5pF CF 3.5pF VFB RI 90kOhm RF 180kOhm VFB RI 90kOhm RI 90kOhm RF 180kOhm V1 18V Ccm- 7pF + VOUT + V3 18V Cin_eq 17pF - - U2 OPA140 V2 18V + + + VG1 + VOUT + VOUT + U3 OPA140 + - VIN V3 18V Ccm- 7pF Cdiff 10pF Ccm+ 7pF RF 180kOhm U3 OPA140 VIN V4 18V V4 18V 51 CF 8.5pF VFB 5) Check CF Compensation by 1/β on Aol Aol = Vout/VFB 1/ = 1/VFB Loop Gain = Vout Aol + Voltage (V) Vout + CF Compensation for Cin 1/ and Aol for OPA140 80 CF (pF) 1.7 3.5 8.5 170 60 40 20 VG1 V2 18V - 100 + 140 120 CT 1TF RF 180kOhm LT 1TH T RI 90kOhm U1 OPA140 V1 18V Maximum Closed Loop BW Cin_eq (1/b) Cin (VOUT/VIN) (pF) (pF) 17 7 17 7 17 7 17 7 1/ @ CF=3.5pF 1/ @ CF=1.7pF 0 1/ @ CF=170pF 1/ @ CF=8.5pF -20 -40 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 52 6),7) Loop Gain Check CF (pF) 1.7 3.5 8.5 170 T 140 120 100 Loop Gain Phase Margin at fcl Voltage (V) 80 60 40 Cin_eq (1/b) Cin (VOUT/VIN) (pF) (pF) 17 7 17 7 17 7 17 7 Vout[1] 1.7p[F] A:(994.855658k; -8.354428f) Vout[1] 1.7p[F] A:(994.855658k; 59.254896) 20 Vout[2] 3.5p[F] A:(1.548148M; -9.769963f) Vout[2] 3.5p[F] A:(1.548148M; 73.969004) 0 -20 Maximum Closed Loop BW Vout[3] 8.5p[F] A:(2.730131M; -13.322676f) Vout[3] 8.5p[F] A:(2.730131M; 80.688797) -40 -60 Vout[4] 170p[F] A:(6.997683M; 6.092349f) Vout[4] 170p[F] A:(6.997683M; 85.056643) Voltage (V) 180 135 90 45 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 53 CF 8.5pF RI 90kOhm 8) AC Closed Loop Vout/Vin RF 180kOhm V2 18V - T 20.00 U1 OPA140 Vout[1]: 1.7p[F] + + Vout + Gain (dB) Vin V1 18V Closed Loop Response VOUT / VIN Vout[4]: 170p[F] 0.00 CF (pF) 1.7 3.5 8.5 170 -20.00 Cin_eq (1/b) Cin (VOUT/VIN) (pF) (pF) 17 7 17 7 17 7 17 7 Vout[3]: 8.5p[F] Vout[2]: 3.5p[F] Maximum Closed Loop BW 45 Vout[1]: 1.7p[F] Vout[4]: 170p[F] Phase [deg] 0 -45 Maximum Closed Loop BW Vout[2]: 3.5p[F] -90 Vout[3]: 8.5p[F] -135 1 10 100 1k 10k Frequency (Hz) 100k 1M 10M 54 CF 8.5pF 9) Transient Analysis RI 90kOhm RF 180kOhm V2 18V T 5.00m - Transient Analysis VG1 + + U1 OPA140 + -5.00m 32.60m Vout Vin V1 18V Vout[1] Vout[1]: 1.7p[F] -32.42m 18.26m Vout[2] Vout[2]: 3.5p[F] -18.10m 15.09m Vout[3] Vout[3]: 8.5p[F] -14.91m 15.09m Vout[4] Vout[4]: 170p[F] -14.91m 0 550u Time (s) 1m 55 9) Transient Analysis T 5.00m Transient Analysis: Zoom Falling Edge VG1 -5.00m 15.09m Vout[4] Vout[4]: 170p[F] -14.91m 15.09m Vout[3] Vout[3]: 8.5p[F] -14.91m 18.26m Vout[2] Vout[2]: 3.5p[F] -18.10m 32.60m Vout[1] Vout[1]: 1.7p[F] -32.42m 487.62u 507.98u Time (s) 528.33u 56 9) Transient Analysis T 5.00m VG1 Transient Analysis: Zoom Rising Edge -5.00m 32.60m Vout[1] Vout[1]: 1.7p[F] -32.42m 18.26m Vout[2] Vout[2]: 3.5p[F] -18.10m 15.09m Vout[3] Vout[3]: 8.5p[F] -14.91m 15.09m Vout[4] Vout[4]: 170p[F] -14.91m 987.38u 1.01m Time (s) 1.03m 57