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SOLUTIONS - SEMESTER TWO - 2008
MODULE:
Digital Circuits and Systems (EE201)
COURSE:
B.Eng. in Mechatronic Engineering
YEARS:
3 (three)
EXAMINERS:
Mr. David Bermingham
Dr. R. Millar
Dr. F. Devitt
Dr. F. Owens
TIME ALLOWED: 2 hours
INSTRUCTIONS:
Answer FOUR questions. All questions carry equal marks
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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QUESTION 1
A) Describe, using a diagram, the structure and operation of a CMOS
NOR gate
Answer:
CMOS NOR Gates are built using 2 NMOS and 2 PMOS Circuits
A
0
0
1
1
B
0
1
0
1
F
1
0
0
0
From the truth table of a NOR gate we can see that only when both inputs are
logic zero will the output be high. From this we can derive that the PMOS
transistors must be in series, as only when both are ON (A=0, B=0) will
current pass through the PMOS transistors. When either input is high, a path
to GND must be created, the NMOS FETs are therefore arranged in parallel.
3 Marks
VDD
A
B
P0
S
P1 N0 N1 F
0V 0V ON ON OFF OFF 1
0V VDD ON OFF OFF ON 0
VDD 0V OFF ON ON OFF 0
VDD VDD OFF OFF ON ON 0
A
G
P0
D
S
B
G
P1
D
F
G
D
D
N0
N1
S
S
G
5 Marks
TOTAL : 8 Marks
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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b) Describe the three components of CMOS power dissipation. Name 3
methods of reducing power consumption within CMOS circuits?
CMOS Power is derived from 3 components:
A) Dynamic Power
Dynamic Power is due to the constant charging and discharging of the gate
capacitance. The insulator between the Gate and MOSFET create a small dielectric
capacitance at the gate. To switch the gate ON and OFF requires charge to be either
added or removed from this capacitance. The dynamic power of a CMOS circuit is
calculated using the equation
PDYNAMIC  1 / 2 * f *Vdd *  Ag .C LG
gC
Where f is the operating frequency of the CMOS circuit, Vdd is the supply voltage of
the circuit, Ag is the switching activity of the CMOS gate and CGL is the average gate
load capacitance
3 Marks
B) Static Power
Static Power within CMOS circuit is due to leakage between both the gate to substrate
(IGS) and the drain to source leakage (IDS). As MOSFET technology advances, the
need for smaller MOSFET requires components such as a gate width or insulator
width to be correspondingly reduced. Reductions in parameters such as gate width
will in turn increase the leakage through the MOSFET
GATE
SOURCE
OXIDE (SiO2)
IGS
N-
DRAIN
N-
IDS
CONTACT
3 Marks
C) Short Circuit Power
The final and smallest component of CMOS power is the short circuit dissipation seen
during CMOS transition. Since NMOS and PMOS circuits will typically have
differing switching times, there is a small period when switching state that both
transistor may be on. For a small period of time, this situation creates a short circuit
between VDD and GND.
Overall, the power consumption in a CMOS circuit is calculated using the equation
PTOTAL= PSTATIC + PSHORT + PDYNAMIC
Where PSHORT is negligible, PSTATIC is determined by the technology utilized and
PDYNAMIC can be estimated using a typically circuit load
3 Marks
Within a CMOS circuit, Power can be reduced by either
A) Reducing the Supply Voltage
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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B) Reducing the frequency of the device
C) Reducing the average switching load (how often the CMOS gate switches)
D) Utilize a technology which reduces static power consumption
a. Better Insulator
b. Larger gate width
3 Marks
TOTAL : 12
Marks
C) Which of the two circuits shown in table 1 has the lowest power
consumption? You can assume all MOSFET are identical and switch the
same amount of times.
Circuit A =>
PTOTAL= PSTATIC + PSHORT + PDYNAMIC
Where PSHORT
=0
PSTATIC
=1
PYNAMIC = ½ * 100.106 * 3.3 * (0.5 * 2.10-12)
= 0.165 mW
PTOTAL
= 1.165 mW
Circuit B =>
PTOTAL= PSTATIC + PSHORT + PDYNAMIC
Where PSHORT
=0
PSTATIC
=1
PYNAMIC = ½ * 500.106 * 1.8 * (0.5 * 2.10-12)
= 0.45 mW
PTOTAL
= 1.45 mW
TOTAL:5 Marks
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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Question 2
A)
Using a 2-1 Line multiplexer only, generate the following function:
F  A.B.C.D  BCD  ABCD  ABC
Answer
Factorize using C
F  C ( A.B.D  ABD )  C ( BD  AB)
Factorize both sub functions using B
F0  B( A.D)  B( AD)
F1  B(D)  B( A)
The sub functions of F00 are expanded out to full form
F00  A.D  A.0
F01  A.D  A.0
6 Marks
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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0
Multiplexer
D
A
Multiplexer
0
Multiplexer
Multiplexer
/D
B
A
C
D
Multiplexer
A
B
B)
only.
4 Marks
TOTAL: 10 Marks
Design a 2-channel 2-bit Multiplexer using 2-to-1 line Multiplexers
Answer
I0
Select Output
S
O0 O1
I0 I1
0
J2 J1
1
I1
O0
Multiplexer
J0
O1
J1
2 Marks
2-Channel 2-Bit MUX requires single select line which is used to route either
the I or J inputs to the output bits.
The Boolean equations for this truth table are
O0 = I./S + J0.S
O1 = I1./S + J1.S
2 Marks
These equations match the Boolean equation for a 2-1 MUX and a 2-channel
2-bit MUX can be implemented by placing 2 2-1 MUXs in parallel
S0
I0
I1
J0
J1
2- channel
MUX
O0
2- channel
MUX
O1
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
S
page 6/17
3 Marks
Total: 7 Marks
C)
How would this function be implemented within an FPGA Logic
Slice?
Answer
An FPGA would typically implement such a function using a Lookup
table. Xilinx Logic Slices (or Logic Blocks) comprise 2 4-input LUTs along
with some carry & control logic, with Flip Flops at the output allowing the
combinational result to be register or latched
In the case of function F, the LUT would be programmed with the precomputed solutions for all possible input combinations
3 Marks
Expanding F out to its full form:
F  A.B.C.D  ( ABCD  ABCD)  ABCD  ( ABCD  ABC D)
when the input bits are 0000, 1011, 0011, 0101, 1111 OR 1110 the output is
ONE, for all other input combinations the output is zero. The LUT would
therefore be programmed
3 Marks
Address (A->D)
LUT Result
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
1
0
0
1
0
1
0
0
0
0
0
1
0
0
1
1
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The control logic of the MUX would be programmed to allow the LUT output
to propagate to the output, with the final control MUX determining if a
registered output is required
2 Marks
TOTAL: 8 Marks
Question 3
Describe an algorithm for multiplying 2 floating point numbers
stored using the IEEE 754 Single Precision Format.
A)
Answer
Using floating point system, numbers are represented in the form A * 2a
For IEEE 754 single precision, 32-bits are utilized to store such numbers
S
E
E
E
E
E
E
E
E
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
M
Where S is the sign bit, E represent the biased exponent and the M bits store the
floating point Mantissa
Any real number is converted to IEEE format by
Converting the number to its binary equivalent
Shifting the number either left of right until only the implied 1 is left of the decimal
point
The exponent is created by adding 127 to the number of shifts (exponent biasing)
All digits right of the decimal point are stored in the mantissa while the sign bit is
used
To multiply, a similar method to decimal floating point is used:
Multiplication Algorithm:
Lets assume that A*2a and B*2b will be multiplied
The multiplication result will have:
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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Mantissa resulted from the multiplication of the two mantissas (C = A*B)
Exponent resulted from the addition of the two exponents (c = a+b)
Therefore,
C = (A*B). 2(a+b)
Using this algorithm, show the steps required to multiply:
8 * 10.5
Step 1: Convert 8 and 10.5 to binary
8
=> 1000.0
Normalising would require three shifts right
=>
A = 1.0.23
B)
10.5
=> 1010.1
Normalising would require three shifts right
=>
A = 1.0101.23
3 Marks
Step 2:
Result Mantissa C is created
C = (A*B)
=>
C = (1.0 * 1.0101) => 1.0101
Result Exponent c is created
c = (a+b)
=>
c=3+3
Step 3:
=> 6
1.0101.26
Result
3 Marks
6
Check 1.0101.2
=> 1010100 = 84
Using IEEE, result would be stored as:
Decimal
Sign bit
=0
Exponent = 6+ 127
=133
Mantissa bits = 01010000000000000…etc
Binary
0
10000101
2 Marks
TOTAL:8 Marks
C)
Outline 3 issues which should be considered when utilizing
floating point numbers?
Any 3 of these design considerations
 Round off Error
 Limited space in which to store recurring fractions
 Must chop or round at some point
 Underflow
 Result is too small for FP representation
 Division of small numbers
 Overflow
 Result is too large for FP representation
 Large multiplications can result in overflow
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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 NUM Divide by Zero
 IEEE754 FP System should return +infinity when NUM>0 & -infinity
when NUM<0
 Zero Divide by Zero
 IEEE754 FP System should return NaN
TOTAL: 5 Marks
Question 4
A)
Design an 8-bit barrel shifter capable of performing arbitrary
Arithmetic Shift Right (ASR), Logical Shift Right (LSR), Logical
Shift Left (LSL) and rotate right (ROR)
Answer
In total we have 4 different shift methods, requiring 2 control signals for the output
MUX.
To be able to shift anywhere between 0 and 7-bits we require 3 shift amount bits.
The barrel shifter is comprised of 4 parallel hardwired cascading shifters, where each
shifter is built using the following circuit.
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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Data OUT
8-bit 2-1 MUX
4-Bit SHIFT
8-bit 2-1 MUX
2-Bit SHIFT
8-bit 2-1 MUX
1-Bit SHIFT
Data IN
32
3-Bit
Control
Signals
The bit shifting hardware is built using a re-wiring of the data input from each stage.
As the data traverses the MUXs, we can select either the previous input or a shifted
(or rotated) version of the stage input. I.E, to shift one time we would select the
shifted input via MUX 1, while allowing this value to pass unmodified through the
remaining 2 MUXs
Data IN
Shift
Amount
ASL
LSL
Shift
Type
LSR
ROR
4:1 8-BIT MUX
Data OUT
B)
TOTAL: 12 Marks
How is the rotate function extended to allow rotate with carry
(RRX) to be carried out?
Normal rotate functions (without carry) will attempt to feed the shift out bits
into the Most Significant bits of the result.
A
B
C
D
E
F
LSB
MSB
Rotate Right (no carry)
G
H
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H
A
B
C
D
E
F
G
EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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However sometimes a previous result will generate a result larger than the
CPUs native word size, i.e a carry was generated. By extending the rotate
registers from 8-bits to 9-bits we can feed a carry in(X) into the result, while at
the same time catching the LSB as the carry out (Y)
4 Marks
LSB
MSB
Rotate Right (with carry)
A
B
C
D
E
F
G
H
X
X
A
B
C
D
E
F
G
Y
In this way the CPU can handle word sizes larger than it native bus width.
Since the rotate function operates in 2 modes now, an additional shifter +
MUX is required. Overall, a carry in, carry out and rotate select signal are
needed.
4 Marks
TOTAL: 8 Marks
C)
How does placing the barrel shifter on one of the ALU input bus
improve the performance of an ARM microprocessor? What is the
major disadvantage with this placement?
ALU
Register File
16 x 32-bit
B BUS
Barrel
Shifter
TOTAL: 5 Marks
A BUS
ALU BUS
By placing the barrel shifter on the B BUS, between the register file and ALU, the
ARM microprocessor allows fast generation of shift + arithmetic results. This is
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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particularly useful in functions such as bit masking or address generation. For
example, say we wanted to compute the address:
Z = Y + (X<<4)
Within an ARM CPU, this instruction would require only one clock cycle. The B bus
is loaded with X, which is shifted in the barrel shifter before being added to Y in the
ALU.
Another advantage would be within bit masking operations. For example, say we
wanted to extract bit 4 of X and bit 7 of Y. With the barrel shifter in this position we
can complete these operations without having to store the bit mask. Assuming one
register (T) contains the number 1, the operations are:
Z1 = (X & (T<<3))
Z2 = (Y & (Y<<7))
4 Marks
The major disadvantage of placing the barrel shifter in this position is that it is
comprise of a large number of cascading MUXs. When compared to the ALU critical
path it will typically be a longer delay, by placing them is series the delay is summed
between the ALU and barrel shifter.
1 Mark
TOTAL: 5 Marks
Question 5
A)
Answer
Briefly describe the dynamic RAM cell and its operation. How
does it compare with a single static RAM cell in terms of area,
speed, control circuitry and power?
X
Row select
Y
Storage Column select Data I/O
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Cell- 2007/2008
EE201 - Digital Circuits and Systems - Semester Two
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DRAM utilises MOSFET capacitance to store data bit
 Transistor per bit cost is approx 1
 Si02 insulates gate and substrate
 Creating dielectric capacitor between gate and substrate
 Data bit is stored in this capacitance
3 Marks
To write the memory cell, the bit line is charged to logic 1 or 0 while the row
and column select lines are asserted. This enables the access transistor,
making it possible to charge up the storage capacitor with the desired logic
voltage.
The read operation takes place by asserting the word line. The access
transistor is turned on, sharing the voltage on the capacitor with the bit line.
Sensitive amplifier circuits detect small changes on the bit line to determine
whether a 1 or 0 was stored in the selected memory element.
The destructiveness of the read operation makes DRAMs complex. To read
the contents of the storage capacitor, we must discharge it across the bit line.
Thus, external circuitry in the DRAM must buffer the values that have been
read out and then write them right back.
The second problem with DRAMs, and the most significant one is that their
contents decay over time. Every once in a while (measured in milliseconds),
the charge on the storage capacitors leaks off. To counteract this, the DRAM
must be refreshed. Periodically, the memory elements must be read and
written back to their storage locations.
3 Marks
Comparison to SRAM
 Advantages of DRAM
o Denser : Smaller Area required
o Cheaper: Cost per bit is less
o Power: More power efficient than high speed SRAM
 However SRAM can be designed to consume little
power

Disadvantages of DRAM
o Control Logic : Requires memory controller to ensure
data is refreshed automatically unlike SRAM
o Interface: Much more complicated to interface than
simple address/data bus structure of SRAM
o Speed: Difficult to scale DRAM to ultra high performance
without long latencies, errors, etc. High speed memory
like processor cache uses SRAM cells
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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o Power: Power consumption analysis must include
additional control circuitry in calculations.
 PD(SRAM) = Power dissipated by SRAM cells at
freq f
 PD(SRAM) = Power dissipated by DRAM cells at
freq f + Power dissipated by DRAM controller
6 Marks
TOTAL: 12 Marks
B)
Design an 8-bit wide * 64 work DRAM using 1-bit * 64 word DRAM
arrays? Indicate all control signals.
Each 1-bit * 64 word DRAM is comprise the following structure (diagram not
needed). The 64 locations are divided into 8 rows and 8 columns, in order to
address each row/column the column and row address decoders use a 3-bit
input which is decoded into an 8-bit (single bit high) output code.
2 Marks
Column Address (CAS)
Row Address (RAS)
To create an 8-bit * 64-word we chain 8 of these modules in parallel. The
same 6-bit address is used (3-row and 3-column).
6-Bit Address
64 x 1
64 x 1
64 x 1
64 x 1
64 x 1
64 x 1
64 x 1
64 x 1
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LSB
EE201MSB
- Digital Circuits and Systems - Semester Two - 2007/2008
Data I/0
page 15/17
Signals missing from diagram
Output Enable
Write Enable
Clock
3 Marks
TOTAL: 5 Marks
C)
Describe how multiplexed addressing is used within DRAM
memory? What additional signals are needed when using such a
scheme?
 Multiplexed Address Lines
 To further reduce cost, DRAM uses multiplexed address
 4K x 1 = 12 Address lines
 16M x 1 = 24 Address lines
 Since column address is independent of row address
 We can provide row address and then column address
 If 12-bit address bus is multiplexed we can address 16M DRAM with only 2
additional lines (RAS and CAS)
 RAS : Row Address Strobe
 CAS : Column Address Strobe
 Multiplexed Address, Step by Step:
Step 1: Latch out 12 row address bits
Step 2: Strobe RAS line which causes DRAM to latch in row address
Step 3: Wait until you are sure it has been registered and latch out column
address bits
Step 4: Strobe CAS line which causes DRAM to latch in column address
Step 5: Wait some period of time and read/write to data bus
3 Marks
Sys Clock
RAS
RAS
CAS
CAS
ADDR
ROW ADDR
COL ADDR
WE
D BUS
Data Out
Undefined
2 Marks
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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When compared to DRAM designed in part B, a multiplexed scheme would require 2
additional signals to assert when a row address and column address had been placed
on the CPU address bus. These signals are typically called /RAS and /CAS, with the
time between asserted a RAS and CAS referred to as the RAS-to-CAS delay.
Along with these signals, a register to store the Row Address and a register to store
the Column Address is required. These registers are enabled by the RAS and CAS
signals. A timing register is also required to synchronize these operations.
3 Marks
TOTAL: 8 Marks
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EE201 - Digital Circuits and Systems - Semester Two - 2007/2008
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