Download SR Latch Circuit

5-1 Sequential Circuits

Unlike combinational logic circuits, the output of a sequential logic circuit depends
not only on the current inputs but also on the current state of memory elements in the
circuit.

The binary information stored in the memory elements determines the state of the
circuit at any given time.

A typical sequential circuit consists of some combinational logic circuitry combined
with memory elements to store the state of the circuit.

The current state of the circuit is fed back to the combinational logic and can be
considered as additional inputs to the circuit. This is called feedback.

There are two types of sequential logic circuits, synchronous and asynchronous.

A synchronous sequential circuit is a circuit that changes state only at discrete
instants of time. The most frequently encountered is the clocked sequential circuit.
Typically, synchronization is achieved by a timing device called a master-clock
generator.

Asynchronous sequential circuits can change state independently of time.

The memory elements in clocked sequential circuits are called flip-flops.
5-2 Latches

A flip-flop circuit has two outputs, Q and Q’.

There are a variety of different flip-flop variations.

A flip-flop can maintain a binary state indefinitely (unless the power is turned off),
even after the input that resulted in its current state is removed.

The most basic types of flip-flops operate with signal levels and are referred to as
latchs.
SR Latch Circuit
 A latch can be constructed from two NAND or two NOR gates.
R
S
Q
Q'
S
R
Q
Q'
SR Latches

These basic SR latches are asynchronous flip-flops.

Each circuit forms a basic latch upon which other more complicated types of flipflops can be built.

Set state: Q = 1,
Q’ = 0
Clear state: Q = 0,
S
1
0
0
0
1
R
0
0
1
0
1
NOR Gate SR Latch
Q
Q’
1
0
(after S=1, R=0)
1
0
0
1
(after S=0, R=1)
0
1
undefined
0
0
S
1
1
0
1
0
R
0
1
1
1
0
NAND Gate SR Latch
Q
Q’
0
1
(after S=1, R=0)
0
1
1
0
(after S=0, R=1)
1
0
undefined
1
1
Q’ = 1
SR Latch With Control Input
 The operation of the basic latch can be modified by providing an additional control
input that determines when the state of the circuit is to be changed.

Q(t),

Q(t + 1),
or just Q, is referred to as the present state, and represents the binary state of the
latch before application of the clock pulse.
referred to as the next state, represents the binary state after the clock
pulse.

The state of the latch is free to change as long as CP is equal to 1.
S
Q
CP
Q'
R
SR Latch With Control Input
CP
0
1
1
1
1
SR Latch With Control
S
R
Q(t + 1)
X
X
no Change
0
0
no Change
0
1
Q=0 (Reset)
1
0
Q=1 (Set)
1
1
indeterminate
D Latch
 One way to eliminate the undesirable condition of the indeterminate state in the SR
latch is to ensure that the inputs S and R never equal 1 at the same time.

The D latch has only two inputs: D and CP.

The ‘D’ stands for “data”.

The state of the latch is free to change as long as CP is equal to 1.
D
Q
CP
Q'
D Latch
5-3 Flip-Flops

The state of a latch or flip-flop is switched by a change in the control input. This
momentary change is called a trigger and the transition it causes is said to trigger the flipflop.

In circuits with feedback, there are serious drawbacks to the use of latches as storage
elements.

The problem is that the latch responds to the level of the clock pulse and therefor is free
to change state as long as the clock input is high.

The key to proper operation of a flip-flop is to trigger it only during a signal transition.

A clock pulse goes through two transitions. One transition is from low to high and the
other is from high to low.

There are two ways that a latch can be modified to form a flip-flop.

One way is to employ two latches in a special configuration that isolates the output of the
flip-flop from being affected while its input is changing.

Another way is to produce a flip-flop that triggers only during a signal transition and is
disabled during the rest of the clock pulse duration.
Edge-Triggered D Flip-Flop
 Edge triggered flip-flops respond only to a clock pulse edge and not to the level of the
of the clock pulse.

Edge-triggered flip-flops can be either positive or negative edge sensitive.

One type of edge-triggered flip-flop is the master-slave flip-flop. It is constructed
from two separate flip-flops and an inverter.

The master latch is triggered on the leading edge of the clock pulse and the slave on
the trailing edge.

Only one latch is enabled at a time.

The master latch is enabled when the clock input is high and the slave is enabled
when it is low. This behavior could be reversed with the addition of an inverter on
the clock input.

In a master-slave flip-flop, it is possible to switch the output of the flip-flop and its
input information with the same clock pulse.

The master-slave combination can be constructed for any type of flip-flop by adding a
clocked SR latch with an inverted clock to form the slave.

A more efficient construction of an edge-triggered D flip-flop uses three SR latches.

In this design, two latches respond to the external data and clock inputs. The third latch
provides the outputs for the flip-flop.

The S and R inputs of the output latch are maintained at a logic 1 level when CLK = 0.
This causes the output to remain in its present state.

If D = 0 when CLK becomes 1, R changes to 0, resetting the output latch (Q = 0). If
there is a change in D while CLK = 1, R remains 0, locking out further change.

When CLK returns to 0, R changes to 1, placing the output latch in the quiescent state
without changing its output.

Setup time is the time period the input must be held stable before the clock edge occurs.

Hold time is the time period the input must be held stable after the clock edge occurs.
JK Flip-Flops
 A JK flip-flop is a refinement of the SR latch in that the indeterminate state of the SR
type is defined in the JK type.

Inputs J and K behave like inputs S and R to set and clear the flip-flop, respectively.

When both inputs J and K are equal to 1, the flip-flop switches to its complement
state, i.e., if Q = 1 it switches to Q = 0, and vice versa.

The plain JK flip-flop has a serious drawback.
T Flip-Flops
 The T flip-flop is a single input version of the JK flip-flop.

The T flip-flop is obtained from the JK flip-flop by connecting the J and K inputs
together.

The ‘T’ stands for “toggle”, because when the T input is equal to 1, the output will
switch to its complement state.

T flip-flops have the same drawback alluded to earlier with the JK flip-flops.
Direct Inputs
 The preset input sets the flip-flop asynchronously.

The clear input clears the flip-flop asynchronously.

They are usually employed to guarantee that the circuit starts in a know state at power
up.
Graphic Symbols
SET
SET
S
Q
J
Q
R
~Q
K
~Q
RESET
RESET
SET
SET
Q
D
~Q
RESET
Q
T
~Q
RESET
Characteristic Tables and Equations
Q
0
0
0
0
1
1
1
1
J
0
0
1
1
0
0
1
1
JK Flip-Flop
K
Q(t + 1)
0
0
1
0
0
1
1
1
0
1
1
0
0
1
1
0
Q\JK
Q’
Q
J’K’
0
1
JK Flip-Flop
K
Q(t + 1)
0
Q
1
0
0
1
1
Q’
J
0
0
1
1
J’K
0
0
JK
1
0
JK’
1
1
Q(t + 1) = JQ’ + K’Q
Q
0
0
1
1
T Flip-Flop
T
Q(t + 1)
0
0
1
1
0
1
1
0
T Flip-Flop
T
Q(t + 1)
0
Q(t)
1
Q(t)’
Q(t + 1) = TQ’ + T’Q
Q(t)
0
0
1
 1
D Flip-Flop
D
Q(t + 1)
0
0
1
1
0
0
1
1
Q\D
Q’
Q
D
0
1
D’
0
0
Q(t + 1) = D
D
1
1
D Flip-Flop
Q(t + 1)
0
1