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Frequency Detection of CDRs (1)
Recall that faster PLL locking can be accomplished by use of a phase-frequency detector (PFD):
Vin
Vup -Vdn
Vup
4p
2p
+2
+4
p
Vdn
Vf
K pd =
Vswing
p
fin - fout
2Vswing
2p
Unfortunately this PFD does not work for the case where Vin is a random data sequence, i.e., in a CDR.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
1
Frequency Detection of CDRs (2)
In general, conventional CDR PDs do not make good frequency
detectors. There are three general techniques to increase frequency
acquisition range:
1. A separate frequency acquisition loop with a reference clock.
2. Quadricorrelator.
3. Rotational frequency detector.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
2
Frequency Detection of CDRs (3)
1. Frequency acquisition loop with a reference clock
Freq. Acquisition Loop
(CMU)
lock
detect
clock
divider
phasefrequency
detector
charge
pump
Ref. Clock
Multiplexer
Input Data
CDR
phase
detector
VCO
trans.
block
Recovered Clock
D
Q
EECS 270C / Winter 2016
Retimed Data
CDR Loop
Prof. M. Green / U.C. Irvine
J. Cao et al., “OC-192 transmitter
and receiver in 0.18m CMOS,”
JSSC. vol. 37, pp. 1768-1780, Dec.
2002.
3
Frequency Detection of CDRs (4)
2. Quadricorrelator (referenceless)
Figures from:
H. Ransijn and P. O’Connor, “A PLL-based 2.5-Gb/s
GaAs clock and data regenerator IC,” IEEE J. SolidState Circuits, vol. 26, Oct. 1992, pp. 1345-1353.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
4
Frequency Detection of CDRs (5)
3. Rotational Frequency Divider (referenceless)
Figures from:
D. Dalton et al., “A 12.5-Mb/s to 2.7-Gb/s continuousrate CDR with automatic frequency acquisition and
data-rate feedback,” IEEE J. Solid-State Circuits, vol.
40, Dec. 2005, pp. 2713-2725.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
5
Advantages of Using CMOS
• Compact (shared diffusion regions)
• Very low static power dissipation
• High noise margin (nearly ideal inverter voltage transfer characteristic)
• Very well modeled and characterized
• Mechanically robust
• Lends itself very well to high integration levels
• “Analog” CMOS process usually includes non-salicided poly layer for
linear resistors.
• SiGe BiCMOS is very useful but is generations behind currently
available standard CMOS
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
6
Transistor fT Calculation
VDD
ig
id
vgs
fT is the frequency at which
gm = mCox
Cgs
W
VGS -Vt
L
(
)
Cgs = gWLCox
VGS
id
gm
=
becomes
i g 2pfTCgs
wT = 2pfT =
1.
m
V -Vt )
2 ( GS
gL
fT gives a fundamental speed measure of a technology.
0.25 µm CMOS: fT ~ 23GHz (VDD = 2.5V)
0.18 µm CMOS: fT ~ 57GHz (VDD = 1.8V)
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
7
Static CMOS propagation delay:
Wp
Lp
Vout
Vin
Wn
Ln
Wp
Lp
Wn
Ln
t fall »
CL
W
mnCox n (VDD -Vt )
Ln
t rise »
CL
W
m pCox p (VDD -Vt )
Lp
Assume: Wp = 3Wn for optimum noise margin.
Lp = Ln = Lmin
t rise = t fall =
gLmin (Wp +Wn )Cox
mnCox
gL2min
=
mn
Wn
(VDD -Vt )
Lmin
æ W ö
1
4
=
çç1+ p ÷÷
è Wn ø VDD -Vt wT
Operation is 4X slower than theoretical
maximum due to n-channel & p-channel
gates connected in parallel.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
(Actual  values will be higher
due to high diffusion
capacitances present in submicron transistors.)
8
Verifying with simulation:
n-channel ac simulation
to determine fT:
CMOS inverter transient simulation:
IG
Vin
Vout
ID
fT = 57GHz
EECS 270C / Winter 2016
t = 18ps »
Prof. M. Green / U.C. Irvine
6.4
wT
9
Single-Ended Signaling in CMOS
VDD
Vin
IDD
Vin
Vout
Vout
ISS
ISS
sub
IDD
VSS
Series R & L cause supply/ground bounce.
Resulting modulation of transistor Vt’s result in pattern-dependent jitter.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
10
Effect of Supply/Ground Bounce on Jitter
VDD
¢
data in
data out
clock in
clock out
VSS
¢
Rs = 5 Ls = 5nH
VDD
¢
clock out
Rs = 0
Ls = 0
VSS
¢
clock out
Rs = 5
Ls = 5nH
EECS 270C / Winter 2016
data out
Prof. M. Green / U.C. Irvine
11
Summary of CMOS Gate Performance
Advantages of static CMOS gates:
1.
2.
3.
Simple & straightforward design.
Robust operation.
Nearly zero static power dissipation.
Disdvantages of static CMOS gates:
1.
2.
3.
Full speed of transistors not exploited due to n-channel & pchannel gate in parallel at load.
Single-ended operation causes current spikes leading to
VDD/VSS bounce.
Single-ended operation also highly sensitive to VDD/VSS bounce
leading to jitter.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
12
Current-Mode Logic (CML)
CML inverter:
VDD
R
R
Vout+
• Based on conventional differential pair
Vout-
CL
• Differential operation
CL
Vin+
Vin-
ISS
EECS 270C / Winter 2016
• Inherent common-mode rejection
• Very robust in the presence of commonmode disturbances (e.g., VDD / VSS bounce)
Prof. M. Green / U.C. Irvine
13
DC Biasing of CML Inverter
VDD
1
ISS R
2_
1
ISS R
2 _
VOUT(DC )
VOUT(DC )
R
VIN(DC )
+
W
L
VGS _
1
Vin(DC ) =Vout (DC ) =VDD - ISS R
2
+
+
W
L
VS
_
ISS
VBIAS
EECS 270C / Winter 2016
R
To keep current source transistor in saturation:
VIN(DC )
+
VGS
VS > VBIAS -Vt
VS =Vin(DC ) -VGS
Vin(DC) > VBIAS + (VGS -Vt )
Prof. M. Green / U.C. Irvine
14
Logic Swing & Gain of CML Inverter
Vhigh =VDD
Vlow =VDD - ISS R
VDD
R
R
VDD-ISSR
ISS
VDD
CL
Vswing = ISS R
VDD
0
CL
W
L
W
L
ISS
To achieve full current switching:
VDD-ISSR
(
Vswing ³ VGS -Vt
Vswing
Vmin
Vswing
Vmin
EECS 270C / Winter 2016
=R
)
|I D =ISS
=
2ISS
mnC
W
ox L
ºVmin
1
W
mCox ISS
2
L
> 1 for correct operation
Prof. M. Green / U.C. Irvine
15
Small-Signal Behavior of CML Inverter
Small-signal voltage gain:
Av = gm R = R mCox
Recall
Vswing
Vswing
Vmin
Vmin
=
=R
Av
2
EECS 270C / Winter 2016
rise/fall time constant:
W
L SS
I
1
W
mCox ISS > 1
2
L
t = RCL (Assuming fanout of 1)
CL = gCoxWL
t = R(gWLCox )
Av ³ 2
for full switching
Note: rising & falling
time constants are the same
Prof. M. Green / U.C. Irvine
16
Speed vs. Gain in Logic Circuits
fast input transition:
step response determined by 
slow input transition:
step response determined by Av
Largest possible gain-bandwidth product is desirable.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
17
Relationship between Av ,  , and Vswing
Av = R mnCox
Av2 = mnCox
W
L SS
I
W
m
ISSR2 = n2 × RgWLCox × ISSR
L
gL
(
)(
t
mn
= 2 Vswing
t
gL
Av2
)
Vswing
mn
A = 2 × t × Vswing
gL
2
v
“large-signal” gain-bandwidth product
Larger logic swing preferred for higher gain-bandwidth product
Larger Vswing  Larger Vmin  smaller W/L  larger current density
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
18
Thought Experiment
R
R
R
R
W
L
W
L
W
L
W
L
ISS
ISS
Suppose we decrease current density by increasing W/L:
W
1
´ 2 Þ Vmin ´
, CL ´ 2
L
2
R´
1
t = RC ´ 2
Slower!
2
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
19
Note that the load is only one gate capacitance:
t = RCL = R
gm
wT
=
Av
wT
»
2
CML speed ~ 2.5 times faster than static CMOS
wT
n-channel ac simulation
to determine fT:
CML buffer transient simulation:
IG
ID
t = 8ps »
2.9
wT
fT = 57GHz
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
20
Typical Vswing: 0.3 ×VDD
• Should be large enough to allow sufficient gain-bandwidth product.
• Should be small enough to prevent transistors from going into triode.
* CML will still work in triode (unlike BJT), but there is no additional
speed benefit.
Vswing = ISS R
Once Vswing has been chosen, designer can trade off between gain &
bandwidth by parameterizing between R & ISS:
t = R(gWLCox )
Higher speed: ISS
R
Av = R mCox
Higher gain:
R
EECS 270C / Winter 2016
W
L SS
I
Prof. M. Green / U.C. Irvine
ISS
21
Other Benefits of CML Gates
1.
Constant current bias  VDD / VSS bounce greatly reduced
ISS
KCL sets this current to be nearly constant.
ISS
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
22
VDD
¢
data in
data out
clock in
clock out
VSS
¢
Rs = 5 Ls = 5nH
clock out
VDD
¢
Rs = 0
Ls = 0
VSS
¢
clock out
Rs = 5
Ls = 5nH
EECS 270C / Winter 2016
data out
Prof. M. Green / U.C. Irvine
23
2. Non-inverting buffer available without additional delay:
CMOS:
tp
2tp
inverter
buffer
CML:
Vout+
Vout -
Vout- Vout+
Vin-
Vin+
buffer
inverter
EECS 270C / Winter 2016
Vin-
Vin+
Prof. M. Green / U.C. Irvine
24
Fanout & Scaling of CML Gates
R
Vout-
1x
=
Vin+
W
L
R
Vout+
W
L
Vin-
ISS
R/n
Vout-
R/n
Vout+
W
L
W
n´
L
nx
=
Vin+
n´
Vin-
All voltages unchanged from unit-sized buffer.
Currents & power increase by factor of n.
nISS
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
25
For fanout of n:
t = nCL R
mn
=
V
2 swing
t ng L
Av2
 increases linearly with fanout.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
26
From interconnect, etc.; assumed not to scale with buffer sizes
æ C ö
t = nCL +Cp × R / n = gWLCox R × çç1+ p ÷÷
è nCL ø
(
)(
A = m nC
nW
ox L
2
v
)
( nISS ) × ( R / n)
2
= mnCox WL I SS R2
-1
æ
Cp ö
A
mn
= 2 Vswing × ç1+
÷
t gL
è nCL ø
2
v
(
)
Should set n » 0.1× Cp / CL to minimize
degradation due to interconnect capacitance
Power (proportional to n) determined primarily by interconnect capacitance!
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
27
Sub-micron MOSFETs obey square-law characteristics only in a limited region!
ID
ID
Mobility reduction (linear)
+
VGS _
Square-law behavior
Weak inversion (exponential)
VGS
CML buffer design procedure:
1.
Determine largest allowable ISS (usually limited by electromigration constraints)
2.
Choose “unit-sized” n-channel transistor (typically W/L=20)
3.
Run a series of simulations to determine optimum value of R:
R too small: full current switching not achieved
R too large: slower than necessary
4.
Choose minimum scaling factor after laying out some test buffers of various
sizes and determining approximate value of interconnect capacitance Cp.
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
28
1. Determine largest allowable ISS
standard layout
shared drain
(1/2 diffusion capacitance)
ID £ I max
Imax independent of W
determined by electromigration limits
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
29
CML Design Procedure
Example
Choose: ISS = 400mA
R = 900
ISSR = 360mV
tp = 10ps
R too small
W
4 mm
=
L 0.18 mm
R = 1200
ISSR = 480mV
tp = 12ps
*R optimum*
R = 1500
ISSR = 600mV
tp = 14ps
R too large
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
30
Parameterizing Between Gain & Bandwidth
ISS = 100 µA
R = 4.8 k
Av = 9.3 dB
BW = 2.6 GHz
ISS = 200 µA
R = 2.4 k
Av = 7.1 dB
BW = 5.5 GHz
ISS = 400 µA
R = 1.2 k
Av = 3.9 dB
BW = 11.5 GHz
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
31
Parameterized CML Buffer
R·
GBW
GSCALE · MSCALE
W
· GSCALE · MSCALE
L
ISS ·
GSCALE · MSCALE
GBW
GSCALE: Global scaling parameter
(depends on Cp)
MSCALE: Local scaling parameter
(depends on fanout or bit rate)
GBW:
Gain-bandwidth parameter
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
32
CML with p-channel Active Load
Can be used if linear resistors
are not available.
p-channel load transistors operates in triode region:
Increased capacitance and mismatch result
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
33
Capacitance Comparison (1)
Poly resistor:
p-channel MOSFET:
1
C » Cpoly -sub
2
1
C » Cdepletion + Cchannel -gate + Cchannel -sub
2
(
)
gate
channel
sub
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
34
Capacitance Comparison (2)
(Numbers based on TSMC 180nm CMOS process)
Cpoly-sub  Cchannel-sub : 0.13 fF/ m2
Cdepletion : 1.20 fF/ m2
Cchannel-gate : 7.80 fF/ m2
1
C » Cpoly -sub
2
= 0.1 fF
Poly resistor: Wpoly = 0.6
Lpoly = 2.5
p-channel MOSFET:
Wchannel = Wdiff = 2.5 µm
Lchannel = 0.18 µm
Ldiff = 0.3 µm
C » Cdepletion +
=
EECS 270C / Winter 2016
0.9 fF
(
)
1
Cchannel -gate + Cchannel -sub
2
+ 1.8 fF + .03 fF
= 2.8 fF
Prof. M. Green / U.C. Irvine
35
Capacitance Comparison (3)
R = 1.2 k
s = 235  
Wr = 0.6 µm
Lr = 2.5 µm
Cres = 0.1 fF
M1
Wp = 2.5 µm
Ldiff = 0.3 µm
Cd2 = 2.8 fF
M1
M2
M2
M1
M1
Cd1 = 3.7 fF
Cg1 = 5.8 fF
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
36
Pulse Response Comparison
PWin = 100ps
resistor load
R = 1.2 k
td = 16 ps; PWout = 100 ps
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
p-channel load
(W/L)p = 2.5 µm / 0.18 µm
td = 20 ps; PWout = 98 ps
37
Eye Diagram Comparison
including mismatch effects
resistor load
sR
R
p-channel load
s ID
= 1.5% mismatch
ID
= 4% mismatch
160mV gate-referred mismatch
DCD
ISI
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
38
Series-Gated CML Topology
XOR gate:
MA
MA
MA
MB
MA
MB
Common-mode voltage of BP/N critical:
• Too low  current source transistor biased in triode
• Too high  Transistors MB biased in triode
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
39
Series-Gated CML (2)
VS
I1
BP
I2
BN
VBP -VBN
I1 - I2
ISS
Transistors should be biased in saturation
to realize maximum gm .
VBP -VBN
Slope = gm
Especially important when gate voltages exhibit
slow slew rates
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
-ISS
40
IBP - IBN
VB(cm) = 1.0
VB(cm) = 1.3
VB(cm) = 1.6
DC current:
IBP - IBN
VB(cm) = 1.3
VB(cm) = 1.0
VBP -VBN
Transient response:
(400mV amplitude sine
wave applied to BP/BN)
VB(cm) = 1.6
t
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
41
Level-Shifting CML Buffer
Used to drive clock inputs
of series-gated CML gates
VDD
Output levels:
+
ISS Rcm
_
Vlow
R
(
= (V
)
) -I
Vhigh = VDD - ISSRcm
Rcm
DD
- ISSRcm
SS
R
Vswing = ISSR
ISS
• DC levels shifted down by ISSRcm
• Vswing unchanged
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
42
R
CML Select Circuit
Be reassigning the inputs, the XOR can be transformed into a Select
circuit. Used in a 2:1 multiplexer.
R
SELA
R
OUTP
OUTN
AP
AN
BP
SELA
BN
SELB
ISS
EECS 270C / Winter 2016
AP/N
BP/N
OUTP/N
Prof. M. Green / U.C. Irvine
43
CML Latch
By setting BP/N = OUTP/N, we can construct a CML latch:
OUTP
OUTN
DP
DN
CKP
CKN
ISS
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
44
CML D Flip-Flop
XP
OUTP
XN
OUTN
DP
DN
CKP
XP
CKN
XN
CKN
CKP
CKP/N
Output OUTP/N is synchronized with
CKP/N falling edge.
DP/N
OUTP/N
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
45
CML Latch Design Considerations
IGG
R
R
slope=1/rgg
VGG
1
ISS
2
dc operating points
VGG
Necessary criterion for bistability:
IGG
rgg =
2
2R
=
<0
1/ R - gm 1- gm R
at middle operating point
(Equivalent to loop gain = gmR > 1)
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
46
Avoiding Latch Transparency
gm R > 1
XP/N
gm R » 1
gm R £ 1
“transparent” latch
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
47
QIN
XN
DP
XP
QIP
OUTP
OUTN
DN
CKP
XP
QIP
CKN
QIN
XN
CKN
CKP
GBW parameter
can be increased to
ensure bistability.
R=1000
gmR > 1
R=800
gmR » 1
R=600
gmR < 1
EECS 270C / Winter 2016
Prof. M. Green / U.C. Irvine
48