Download Chapter 5: The Multi

Chapter 5: The Multi-Stage Amplifiers
Section 5.1 The DC Voltage in the Output
Let us consider a typical amplifier shown in Fig. 5.1-1(a).
line are shown in Fig. 5.1-1(b).
Its I-V curve and its load
VDD
RL
IDS
VGS
D
G
S
vin
Q1
vout
VGS
Vop
(a) A typical NMOS amplifier
VDS
(b) The DC output voltage
Fig. 5.1-1 An amplifier with its operating point
As shown in Fig. 5.1-1, the small signal output vout will be on top of a DC
voltage V DS which is usually larger than VGS . Now, consider the two-stage
VDS1 will now become the VGS 2 in the next stage.
amplifier shown in Fig. 5.1-2.
Since VDS1 is usually high, it is not appropriate for it to act as VGS 2 .
5-1
VDD
VDD
RL2
RL1
Q2
D
G
vin
D
S
S
Q1
VDS1
VGS
Fig. 5.1-2 A two-stage amplifier
One possible solution is to introduce a coupling capacitor between these two
amplifiers. The coupling capacitor will filter out VDS1 . That is, whatever VDS1 is,
it will not appear at the gate of the M2. But, we need an appropriate bias voltage for
the second stage transistor. This is done by having a voltage divider consisting of R2
R3
and R3. As shown in Fig. 5.1-3, the gate bias voltage of M2 is now
VDD .
R2  R3
VDD
VDD
R1
VDD
R2
R4
4
3
1
vin
M1
NMOS
C2
M2
NMOS
vout
R3
0.65V
Fig. 5.1-3
Experiment 5.1-1:
A two-stage amplifier with a coupling capacitor in between
A Two-stage Amplifier Coupled by a Capacitor
5-2
In this experiment, we tested the circuit in Fig. 5.1-3. The program is in Table
5.1-1 and the results are in Fig. 5.1-4. The gain was found to be 40.
Table 5.1-1 Program for Experiment 5.1-1
Ex5.1-1
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VDD
vdd! 0
3.3v
R1
vdd!
1
10k
R2 vdd! 3
160k
R3 3
0
40k
R4 vdd! 4
70k
.param W1=5u
M1 1
2
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
.param W1=5u
M2 4
3
0
0
+nch L=0.35u
W='W1' m=1
+AD='0.95u*W1' PD='2*(0.95u+W1)'
+AS='0.95u*W1' PS='2*(0.95u+W1)'
C2 1
3
0.01nF
VGS1
vi+ 0
0.65v
Vin vi+ 2
SIN(0 0.001v
.tran 0.001us 10us
.end
1Meg)
5-3
vin
t
vout
t
Fig. 5.1-4 The gain for Experiment 5.1-1
But a capacitor is by no means easy to fabricate in integrated circuits.
Therefore, some other solution is needed. One possible solution is to introduce a
PMOS transistor in the second stage, as shown in Fig. 5.1-5.
VDD
VDD
RL1
G
G
vin
Q1
D
S
S
D
NMOS
PMOS
Q2
RL2
VGS
Fig. 5.1-5 A two-stage amplifier with a PMOS in the second stage
5-4
Suppose that Vout1 is high. Since VSG 2  VDD  Vout1 , a high Vout1 will mean a
low VSG 2 which is appropriate for Q2. But, it is very hard to have an ideal case.
That is, Vout1 is seldom appropriate to be a proper VSG 2 . A further trick is to have
an active load to replace RL2, as shown in Fig.. 5.1-6.
VDD
VDD
R1
M2
PMOS
V2
M1
NMOS
V3
M3
NMOS
vin
Fig. 5.1-6 A two-stage amplifier with a CMOS circuit in the second stage
Since an NMOS M3 is the load of M2, although Vout1 may not be ideal for M2,
we can still adjust the widths and lengths of the gates of M2 and M3 in such a way
that there is an appropriate operating point for M2. This is demonstrated in the
following experiment.
Experiment 5.1-2
A Two-Stage Amplifier without Capacitive Coupling
The program to find Vout1 is in Table 5.1-2. As can be seen in Fig. 5.1-7, Vout1
is almost 2.4V which means VSG 2 is around 3.3V-2.4V=0.9V. The program to show
the operating point of M2 is in Table 5.1-3 and the result is shown in Fig. 5.1-8. The
gain is shown in Table 5.1-4. We can see that the operating point of M2 is quite
good from Fig. 5.1-8 and the gain is about 156 from Table 5.1-4.
Table 5.1-2 Program for operating points of M1
070708TwoStageCMOSaa
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5-5
VDD
R1 11
R2 11
V2 2
11
2
1
0
0
3.3v
40k
0k
0
M1 2
M2 3
M3 3
5
2
4
0
1
0
0
1
0
VGS3
5
6
0.65v
nch L=0.35u W=5u
pch L=0.35u W=5u
nch L=0.35u W=5u
VGS1
4
0
0.65v
Vin 6 0 sin(0 0.001v 500k)
.DC V2 0
3.3v 0.1v
.PROBE I(M1) I(R1)
.end
IM1
VDS1
Fig. 5.1-7 The operating points of M1
5-6
Table 5.1-3 Program for operating points of M2
070708TwoStageCMOSb
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VDD
11
0
3.3v
R1 11
2
40k
R2 11
V3 3
1
0
0k
0
M1 2
M2 3
M3 3
5
2
4
0
1
0
0
1
0
VGS3
VGS1
5
4
6
0
0.65v
0.65v
nch L=0.35u W=5u
pch L=0.35u W=5u
nch L=0.35u W=5u
Vin 6 0 sin(0 0.001v 500k)
.DC V3 0v 3.3v 0.1v
.PROBE I(M2) I(M3) I(R2)
.end
5-7
IM2
I-V curve of M2(load curve of M3)
I-V curve of M3(load curve of M2)
V3=Vout=VDS3
Fig. 5.1-8 Operating points of M2
Table 5.1-4 The gain for Experiment 5.1-2
****
small-signal transfer characteristics
v(3)/vin
= 155.8296
input resistance at vin = 1.000e+20
output resistance at v(3) = 101.1364k
Section 5.2 The DC Analysis of a Two-Stage Differential
Amplifier
A two-stage differential amplifier is shown in Fig. 5.2-1. It can be seen that
transistors M1 to M5 form the first stage and transistors M6 to M7 form the second
stage.
5-8
3/2
VDD
3/2
M3
M4
1
M6
2
4/3
M1 3
V-
vin
V+
VBIAS
Vout
M2
10/2
10/2
30/2
M7
M5
14/2
VSS
Fig. 5.2-1 A two-stage differential amplifier
This first stage differential amplifier was analyzed rather thoroughly in Chapter 4.
So far as DC analysis is concerned, if Vi  increases, the voltage at the drain of M4,
namely V2 will also increase, as shown in Fig. 5.2-2.
3/2
3/2
M3
VDD
V2
M4
1
2
V-
M1 3
vin
M2
10/2
10/2
V+
VBIAS
30/2
VSS
M5
1
0
1
V-
Fig. 5.2-2 The input/out relationship of the first stage
Let us consider M6 and M7. Note that as V2 increases, VSG 6 decreases. As
shown in Fig. 5.2-3.
5-9
VDD
I
V2
I(M6)
I(M7)
M6
4/3
Smaller VSG6
Higher V2
Vout
M7
14/2
VSD
VSS
6
Fig. 5.2-3 The I-V curves of M6 and its load curve
From Fig. 5.2-3, we can see that the increasing of V2 will induce an increasing
of VSD 6 as shown in Fig. 5.2-4.
I
I(M6)
I(M7)
Smaller VSG6
Higher V2
VDD
M6
V2
4/3
VSD6
Vout
VSD6
M7
14/2
VSS
V2
Fig. 5.2-4 VSD 6 vs V2
But Vout  VDD  VSD6 . Thus we have the relationship between V o and V2 as
shown in Fig. 5.2-5.
5-10
VSD6
VDD
V2
M6
4/3
V2
Vout V
out
M7
14/2
VSS
V2
Fig. 5.2-5 Vout vs V2
Finally, we have the Vi  versus V o as shown in Fig. 5.2-6.
5-11
Vout
V7/2
VDD
7/2
M3
M4
1
M6
2
Vout
4/3
V-
M1 3
vin
M2
10/2
V+
10/2
VBIAS
100/2
M7
M5
14/2
VSS
Fig. 5.2-6 Vout vs V 
It should be noted that the gate of M1 was labeled as positive in Chapter 4.
Why is it labeled as negative in this two-stage circuit? It is labeled as negative
because as shown in Fig. 5.2-6, if V  increases, Vout decreases. For the same
reason, the gate of M2 must be labeled as positive now.
Section 5.3 Experiments
Experiment 5.3-1 The Gain
The circuit we used is that shown in Fig. 5.2-6. The program is in Table 5.3-1
and the result is shown in Fig. 5.3-1. As can be seen, the gain is 1202.
Table 5.3-1 Program for Experiment 5.3-1
0423
.PROTECT
.OPTION POST
5-12
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.UNPROTECT
VDD VDD! 0
1.5V
VSS VSS! 0
-1.5V
M3
11
VDD!
VDD! PCH W=7U
L=2U
M4
21
VDD!
VDD! PCH W=7U
L=2U
M1
1
V-
VSS! NCH W=10U
L=2U
M2
2
V+
3
VSS! NCH W=10U
L=2U
M5
3
VB
VSS!
M6
VO 2
M7
VO
VBIAS
3
VSS! NCH W=100U
VDD! VDD! PCH W=4U
VB
VB
VSS!
0
L=2U
L=3U
VSS! NCH W=14U
L=2U
-0.95v
.OP
VIN+ V+
VIN- V-
0
0
SIN(0V
0.000001V
10K)
DC 0
.TF V(VO) VIN+
.TRAN 1U 1M
.END
5-13
vin
vo
Fig. 5.3-1 The gain for the two-stage amplifier in Fig. 5.2-6
****
small-signal transfer characteristics
v(vo)/vin+
input resistance at
vin+
output resistance at v(vo)
=
1.2028k
= 1.000e+20
= 452.7281k
Experiment 5.3-2 The Relationship between Vi- and Vo
We set V  to be 0 and changed V  from -1V to 1V. The program is shown
in Table 5.3-2 and the result is in Fig. 5.3-2. It can be seen that Vout drops quite
sharply which indicates a high gain.
Table 5.3-2 Program for Experiment 5.3-2
0423
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5-14
VDD VDD! 0
1.5V
VSS VSS! 0
-1.5V
M3
11
VDD!
VDD! PCH W=7U
L=2U
M4
21
VDD!
VDD! PCH W=7U
L=2U
M1
1
V-
VSS! NCH W=10U
L=2U
M2
2
V+
3
VSS! NCH W=10U
L=2U
M5
3
VB
VSS!
M6
VO 2
M7
VO
VBIAS
3
VSS! NCH W=100U
VDD! VDD! PCH W=4U
VB
VB
VSS!
0
L=3U
VSS! NCH W=14U
-0.95v
.OP
*** Transient Simulation ***
VIN+ V+
Vin- V-
0
0
L=2U
0
0
.DC Vin- -1 1v 0.01v
.PROBE V(2, 1)
.END
5-15
L=2U
V2
Vout
VFig. 5.3-2
Experiment 5.3-3
Vo u t and V2 vs V
The Operating Point of M6
The operating point is always important. In this experiment, we tried to find the
operating of M6 to see whether it can be still improved. The program is in Table
5.3-3 and the result is in Fig. 5.3-3. As can be seen, the operating point can still be
improved, which will be done in the next experiment.
Table 5.3-3 Program for Experiment 5.3-3
0423-2
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.UNPROTECT
VDD VDD! 0
1.5V
VSS VSS! 0
-1.5V
M3
11
VDD!
VDD! PCH W=7U
L=2U
M4
21
VDD!
VDD! PCH W=7U
L=2U
M1
1
VSS! NCH W=10U
L=2U
V-
3
5-16
M2
2
V+
3
VSS! NCH W=10U
M5
3
VB
VSS!
M6
VO 2
M7
VO
VSS! NCH W=100U
6 VDD! PCH W=4U
VB
Rm6 VDD!
VSS!
6
VSD6
VDD!
VBIAS
VB
L=2U
L=2U
L=3U
VSS! NCH W=14U
L=2U
0
VO 0V
0
-0.95v
.OP
VIN+ V+
VIN- V-
0
SIN(0V
0
0.000001V
10K)
DC 0
.DC VSD6 0 3v 0.1v
.PROBE I(Rm6) I(M7)
.END
I(M6)
I(M7)
VSD6
Fig. 5.3-3 The operating point of M6 in Fig. 5.2-6
Experiment 5.3-4 The Changing of Operating Point of M6
5-17
In this experiment, we increased the width of M7 to be 17u to increase the current
of M7. This gives a better operating point and a gain of 13968. The program for the
operating point is shown in Table 5.3-4 and the result is Fig. 5.3-4. The program for
finding the gain is in Table 5.3-5 and the result is in Fig.5.3-5.
Table 5.3-4 Program for Experiment 5.3-4
0423-2
.PROTECT
.OPTION POST
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.UNPROTECT
VDD VDD! 0
1.5V
VSS VSS! 0
-1.5V
M3
11
VDD!
VDD! PCH W=7U
L=2U
M4
21
VDD!
VDD! PCH W=7U
L=2U
M1
1
V-
VSS! NCH W=10U
L=2U
M2
2
V+
3
VSS! NCH W=10U
L=2U
M5
3
VB
VSS!
M6
VO 2
M7
VO
3
VSS! NCH W=100U
6 VDD! PCH W=4U
VB
Rm6 VDD!
VSS!
6
VSD6
VDD!
VBIAS
VB
L=2U
L=3U
VSS! NCH W=17U
L=2U
0
VO 0V
0
-0.95v
.OP
VIN+ V+
VIN- V-
0
0
SIN(0V
0.000001V
10K)
DC 0
.DC VSD6 0 3v 0.1v
.PROBE I(Rm6) I(M7)
.END
5-18
I(M6)
I(M7)
VSD6
Fig. 5.3-4 A better operating for M6
Table 5.3-5 Program for finding the new gain
0423-3
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.UNPROTECT
VDD VDD! 0
1.5V
VSS VSS! 0
-1.5V
M3
11
VDD!
VDD! PCH W=7U
L=2U
M4
21
VDD!
VDD! PCH W=7U
L=2U
M1
1
V-
VSS! NCH W=10U
L=2U
M2
2
V+
3
VSS! NCH W=10U
L=2U
M5
3
VB
VSS!
M6
VO 2
M7
VO
VBIAS
3
VSS! NCH W=100U
VDD! VDD! PCH W=4U
VB
VB
VSS!
0
L=2U
L=3U
VSS! NCH W=17U
-0.95v
5-19
L=2U
.OP
VIN+ V+
VIN- V-
0
0
SIN(0V
0.000001V
10K)
DC 0
.TF V(VO) VIN+
.TRAN 1U 1M
.END
vin
vo
Fig. 5.3-5 The new gain
****
small-signal transfer characteristics
v(vo)/vin+
input resistance at
vin+
output resistance at v(vo)
= 13.9685k
= 1.000e+20
=
4.5357x
Experiment 5.3-5 The Input/Output Curve of the Second Stage
In Fig. 5.3-2, we can see that as V2 increases, Vout keeps a constant for a while and
suddenly drops sharply. Thus it is worthwhile to investigate the input/output
relationship between the input and output of the second stage. Fig. 5.3-6 shows the
second stage circuit. The program is in Table 5.3-6 and the result is in Fig. 5.3-7.
5-20
As can now be seen, the input/output is indeed very sharp.
VDD=1.5V
G
S M
2
D
G
D
M1
S
VG2
VG1
=-0.95V
VSS=-1.5V
Fig. 5.3-6 The second stage circuit
Table 5.3-6 The program for Experiment 5.3-5
HW4_CWLu
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.OP
VDD
VDD! 0 1.5V
VSS VSS! 0 -1.5V
M1 2
g1 VSS! VSS! NCH W=14U L=2U
M2 2
g2
VDD! VDD!
PCH
W=4U L=3U
VG1
g1 0
-0.95V
VG2
g2 0
0
.DC VG2 -1.5v 1.5v 0.1v
.END
5-21
VD2
VG2
Fig. 5.3-7 The input/output curve of the second stage
Experiment 5.3-7 The Investigation of the Reason Behind the Behavior of the
Input/Output of the Second Stage
In this experiment, we try to explain why the input/output curve of the amplifier in
Fig. 5.3-6 is so sharp. We plot the I-V curve of M1 and load curves corresponding to
different gate voltages of M2. The program is in Table 5.3-7 and the result is in Fig.
5.3-8. From Fig. 5.3-8, we can see that the I-V curves are very crowded when VG 2
is small. Thus when VG 2 is small, Vout does not change much. We may even say
that it remains a constant. But, as VG 2 reaches a certain value, Vout sharply
decreases.
Table 5.3-7 The program for Experiment 5.3-7
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.OP
VDD
VDD! 0 1.5V
5-22
VSS VSS! 0
-1.5V
Rdm
VDD!
3
0
M1 2
M2 2
VG1
VG2
VDS1
g1 VSS! VSS! NCH W=14U L=2U
g2 3 3
PCH
W=4U L=3U
g1 0
-0.95V
g2 0
X
2
VSS!
0
.DC VDS1 0v 3v 0.01v SWEEP X
.PROBE I(M1)
I(Rdm)
0
1v
0.1dv
.END
VG2=0
I(M2)
I(M1)
VG2=0.1
VG2=0.2
VG2=0.3
VG2=0.4
VG2=0.5
VDS1
Fig. 5.3-8 The I-V curve of M1 and its load curves
5-23