Download Mid-Term Report (March 20)

Gigabit Ethernet Optical Link Design Project
Group 3:
Michelle Middleton
Tiffany Banks
Ming Teng Han
John Patton
March 20, 2003
School of Electrical and Computer Engineering
Georgia Institute of Technology
Abstract
The recent creation of Gigabit Ethernet allowed Ethernet to maintain its current topology
but at much greater speeds. This paper is a summary of the work to date of creating an optical
transceiver for Gigabit Ethernet. The work thus far has included background research and the
design, build, and testing of the transceiver.
The testing of the independent receiver and
transmitter, as well as the transceiver, was quite successful. However, with the attenuation
added, the eye diagrams showed jitter indicating some noise between the transmitter and
receiver. The remaining tasks of this project include completing the testing of the current
transceiver board, building and testing a more aggressive layout, and if this layout meets the
specifications, replacing the connectorized VCSEL in the design with an unconnectorized
VCSEL.
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Table of Contents
Introduction ................................................................................................................1
Project Specification ..................................................................................................1
Background ................................................................................................................2

Laser Driver .....................................................................................................4

VCSEL .............................................................................................................4

Photodiode .......................................................................................................5

Transimpedance and Post Amplifiers ..............................................................6
Group Organization....................................................................................................6
Receiver Test Board ...................................................................................................7
Optoelectronic Link Design .....................................................................................10

Selection of VCSELs .....................................................................................10

Selection of PDs ............................................................................................10

Optical Link Budget ......................................................................................11
Financial Budget ......................................................................................................14
Transceiver Design ..................................................................................................15

Receiver Schematics ......................................................................................15

Transmitter Schematics .................................................................................16

Miscellaneous Components on Schematics...................................................17

Board Layout .................................................................................................18
Assembly and Transceiver Testing ..........................................................................20
Future Plans..............................................................................................................23
Conclusion ...............................................................................................................23
References ................................................................................................................25
Appendix A: IEEE 802.3z Tables ............................................................................26
Appendix B: Gantt Charts ........................................................................................27
Appendix C: Eye Diagrams from Test Receiver Board ..........................................30
Appendix D: Eye diagrams from Testing Transceiver ............................................36
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Introduction
The Internet is one of the most important methods of communication today. By allowing
people who may be thousands of miles apart to communicate quickly and cheaply with each
other, the Internet is quickly eclipsing all other forms of communication as the method of choice.
Additionally, the ability to access a wide range of data independent of time of day and location
makes the Internet a powerful tool that is a necessity in modern business society. Powered by
many different protocols, or forms of transport, that link together to seamlessly control data flow,
the Internet appears as a homogenous network to its users, while appearing as a conglomerate of
many different systems to its constructors. As a builder of this network, it is necessary to
understand many of these different protocols, among which Ethernet is one of the most
important.
Created in 1973 by Xerox, Ethernet provides reliable and fast communication over an
inexpensive medium through the use of a signaling scheme that is relatively simple to
understand. Because of these factors, Ethernet has become a dominant protocol in use in the
Internet. Recently, Gigabit Ethernet was created which increased the speed of any other form of
Ethernet ten-fold, while still allowing the signaling scheme to stay identical to its predecessors.
The purpose of this design project is to design and build a transceiver for Gigabit Ethernet,
through which valuable knowledge of this powerful protocol can be obtained as well as
necessary group organization and management can be learned and applied. Both skills will be
important to have in the business world.
Project Specification
The goal of this design project is to build the physical media dependent layer (PMD) of
the physical layer (PHY) of the Gigabit Ethernet implementation on the open systems
interconnection (OSI) reference model. In other words, the focus of this project is the creation of
an optical transceiver (receiver and transmitter) that will be used to send and receive signals over
a fiber optic cable. The device will be independent of the cable used (i.e. no cable is statically
attached, so this board can be used in many implementations) and independent of the driver (i.e.
no computer is statically attached). The design will be built and tested according to the IEEE
802.3z standards for Gigabit Ethernet. A condensed list of these specifications is shown in Table
1 (for a fuller listing of these specifications, refer to Appendix A). The design will be tested
1
using in-lab equipment that will generate pseudorandom bit sequences and record eye diagrams
to be analyzed to monitor transceiver functionality.
Table 1. Condensed listing of IEEE 803.2z specs
Receiver
Transmitter
Transmitter Type
Signaling Speed Range (GBd)
Wavelength Range (nm)
Extinction Ratio, min (dB)
Shortwave Laser
1.25+/-100 ppm
770-860
9
Signaling Speed Range (GBd)
1.25+/-100 ppm
Wavelength Range (nm)
770-860
Average Receive Power,max (dBm)
0
Receive Sensitivity (dBm)
-17
Return Loss, min (dB)
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The transceiver will implement 1000 BASE-SX Gigabit Ethernet used over a 1.25 Gbps
Optoelectronic link. The VCSEL and PD will utilize a single 5-volt power supply and must be
placed .5 inches apart so as to be implemented with a standard duplex connector. The transmitter
will be constructed using a shortwave 850 nm Vertical Cavity Surface Emitting Laser (VCSEL)
driven by the MAX3287 laser driver built by MAXIM. The receiver will utilize the MAX3266
Transimpedance Amplifier (TIA) and MAX3264 Limiting Amplifier, both also created by
MAXIM. The fiber optic cable that will be used will be 62.5µm width multi-mode fiber. The
VCSEL used will be SC connectorized (connector to the fiber link attached), while the photo
detector (PD) used in the receiver can be either connectorized or unconnectorized. The designs
will be constructed on a standard printed circuit board and driven using in-lab equipment.
Background
Ethernet was created in 1973 by researcher Bob Metcalfe at Xerox Corporation. He
created the network to link Xerox’s “Alto” computer to a printer at the company’s Palo Alto
Research Center. Since its inception, the use of Ethernet has rapidly expanded to become the
most popular and commonly deployed network topology worldwide. The system functions
essentially by connecting a number of computers via a single cable. Data is transmitting by a
computer on that cable and seen by every other computer on the network. To delineate which
computer should receive the information, an address is given in the data packet that specifies a
distinct address for the target computer. All computers read this address and, unless the address
matches the computer’s specific address, ignore the data packet. The computer that matches the
address reads and processes the information.
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Ethernet operates at speeds of 10 megabits per second (10 Mbps). Fast Ethernet, which
was adopted in June 1995 by the IEEE 802.3 committee, increased this speed to 100 Mbps
without protocol translation, which allowed for backwards compatibility between it and regular
Ethernet networks. In June 1998, Gigabit Ethernet was standardized and further increased the
speed of Ethernet to 1 Gbps (1000 Mbps). This increase in transfer rate was generated by
combining the 802.3 Ethernet standard with the ANSI X3T11 Fiber Channel technology. This
mergence of the two technologies allowed Ethernet to operate at faster speeds, while still
maintaining much of its original topology. In fact, the jump to Gigabit Ethernet only concerns a
change at the physical layer; the protocol looks identical to Ethernet from the Data Link layer
upward.
Figure 1. Ethernet standard architecture.
The Ethernet standard architecture can be described in Figure 1. This design project will only
concern the bottom two levels of the architecture (the red box on the figure) as all other layers
are controlled by the Ethernet topology itself. The “PMD” layer on the figure will be the
transceiver, while the “medium” consists of the fiber channel. A model of the PMD layer is
given in Figure 2.
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Figure 2. Model of PMD layer.
Data coming in from some device, possibly a computer, will be translated into a serial and
differential output. These signals will be fed to the laser driver which will create a modulating
current to drive the VCSEL. The VCSEL will emit light over the fiber optic channel, after which
the photo detector will receive the light. The photo detector will generate a current to be
received by the Transimpedance Amplifier. The TIA will then convert this current to a voltage,
which will be amplified by the post amplifier. This amplified voltage will then be the data
output of the PMD to be used by whatever analytical circuitry is next in the data path.
Laser Driver
The laser driver is a device, as the name suggests, that provides a current to drive the
laser. The MAX3287 is a laser driver that is optimized for Gigabit Ethernet operating at 1.25
Gbps, making it perfect for this design. The device can switch 30 mA of modulating current at a
specified data rate and can be configured to drive long wave, short wave, or vertical cavity
surface emitting lasers. The driver contains a bias generator, a laser modulator, and a number of
safety features. Additionally, the driver has automatic power control that adjusts the laser bias
current to maintain the optical power at a constant level, regardless of the characteristics of the
driven laser. These features make this device well suited for this design.
VCSEL
VCSELs are compound semiconductor micro-laser diodes that convert electrical
current into optical power and emit light in a perpendicular direction to their surface. Some of
the advantages VCSELs have over traditional edge-emitting lasers include circularly symmetric,
and hence tightly focused beams, making it easier to couple to an optical fiber, being able to be
produced in two-dimensional arrays, as well as parallel transmission, allowing almost limitless
data transfer rates. Because of this reason, the VCSEL is the device of choice used in Gigabit
Ethernet to drive signals onto the fiber channel medium.
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The choice of the VCSEL can determine many qualities of the ability of the PMD to
operate correctly.
When choosing a VCSEL, a number of characteristics are taken into
consideration. These characteristics include threshold current, slope efficiency, aperture size,
emitted power, forward voltage, and operating wavelength. Aperture size and emitted power are
self-explanatory, as they describe the operating size of the laser and the amount of power that the
laser emits, respectively. The forward voltage is the voltage drop across the VCSEL when it is
in operation, i.e. forward biased. The threshold current of the laser is the amount of input current
that is required to turn the laser “on” (i.e. cause it to emit light). The slope efficiency is a ratio of
the increase of emitting power to an increase of input current. These two characteristics are
important to the choice of a VCSEL because the combination of the two is used to determine
what modulating current the laser driver must output. Good VCSELs (and hence, the ones that
will be chosen for this design) will have high slope efficiencies while exhibiting low threshold
currents.
The operating wavelength is the wavelength of light that the laser emits and is
characteristic of the material that makes up the laser. For this design, a laser operating at 850 nm
must be selected. Additionally, the other characteristics of the VCSEL will be determined based
on circuitry limitations and the standards listed in the 802.3z specifications.
Photodiode
The photodiode (PD) is used in the receiver of the Gigabit Ethernet transceiver to monitor
signals transmitted across the fiber medium. A PD is a semiconductor device that produces, as a
result of the absorption of photons, free carriers that support the conduction of current. In other
words, a photo detector detects light and transmits a current based on the amount of light
detected. The PD used in this design will be of the PIN, or positive-intrinsic-negative, type with
a large intrinsic region sandwiched between p-doped and n-doped semi-conducting regions.
In choosing a PD, similar to that of a VCSEL, a number of characteristics must be taken
into consideration. Of main importance to this design are the characteristics of responsivity,
capacitance, and aperture size. Capacitance determines the response time, through a direct
correlation, of the PD, which must be low in order to be used in high-speed applications.
Responsivity is the sensitivity of the detector and is a ratio of the amount of current generated by
the amount of light received. Aperture size, as stated before in reference to the VCSEL, is the
size of the operating area of the device. A large aperture size is necessary to allow good
alignment to the fiber cable.
Generally, a large aperture size, high responsivity, and low
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capacitance are the desirable qualities of a good photo detector. These actual characteristics will
be determined based on the specifications in the 802.3z standard and the needs of the circuit.
Transimpedance and Post Amplifiers
The Transimpedance Amplifier (TIA) amplifies and transfers the current generated by the
PD into a voltage. This voltage is then amplified by the post amplifier to generate the output
level dictated by the IEEE specifications. The MAX3266 TIA used in this design is optimized
for use in 1.25 Gbps LAN receivers. The TIA has 200nA input-referred noise, 920 MHz
bandwidth, and 1mA overload characteristics. The MAX3264 Limiting Amplifier (LA) is a 1.25
Gbps amplifier designed for use in Gigabit Ethernet and Fiber Channel systems. The LA accepts
a wide range of input voltages and provides a constant level output voltage. The device offers a
number of qualities that allow it to be a perfect device for use in this design. Coupled with the
MAX3266 TIA, this system should effectively create an appropriate output voltage given the
input current of the PD.
Group Organization
To accomplish the goals of this project, tasks needed to be organized in two ways.
First, each group member was assigned certain tasks for which they were responsible. This
organization was determined by considering the strength of each individual in varying areas.
However, each member is still an integral part of other areas of the project for which they are not
specifically responsible. A table of the group organization is shown below.
Table 2. Group organization
Michelle Middleton
Board layout, board assembly
Ming-Teng Han
Online research, website manager
John Patton
Testing, Part Orders
Tiffany Banks
Editing
The second type of organization was accomplished by the creation of a Gantt chart,
which shows a timeline of projected work completion. The most recent Gantt chart is shown in
Figure 3. Preceding Gantt charts may be found in Appendix B.
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Figure 3. Most recent Gantt chart.
Receiver Test Board
The first phase in the design stage was to perform tests on a pre-fabricated
receiver board. This phase provided some insight on how to design, test, and implement the final
transceiver. It also gave some understanding on the use of the electronic testing equipment as
well as provided some soldering practice for the group. The receiver test board consists of the
MAX3266 TIA and MAX3264 LA with an electrical input in place of the photo detector. Onboard passives provide AC coupling, supply coupling, and DC biasing. Figure 4 shows a
schematic of the receiver test board while Figure 5 shows the test board after it was assembled.
Figure 4. Schematic of receiver test board.
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Figure 5. Close up of assembled test receiver board.
The board was tested using the Tektronix GTS1250 GBIC test system along with a
variable attenuator. The Tektronix GTS1250 serves to generate test patterns based on Fiber
Channel and Gigabit Ethernet standards, while the variable attenuator simulates the loss in a
fiber system. Different test signals with varying attenuation levels were used, including the
Ethernet standard K28.5 and the more rigorous Pseudo Random Bit Stream (PRBS7). The
differential output of the receiver was then displayed on the Tektronix TDS7154 Digital
Phosphor Oscilloscope as an eye diagram to display the signal integrity and jitter of the output
signal. Figure 6 shows the complete laboratory setup.
Figure 6. Complete receiver test board setup.
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The eye diagrams give a visualization of how the waveforms used to send bits of data
could potentially lead to misinterpretation of these bits. Jitter refers to the high frequency,
random displacement of a signal from its ideal location. Both signals showed the cleanest eye
diagram with the least amount of jitter at an attenuation level of 10 dB. Figure 7 shows two eye
diagrams taken in the laboratory.
Figure 7. Test results of receiver test board with K28.5 and PRBS7 input signals and 10 dB attenuation.
These same signals degraded significantly at about 60dB as shown below.
Figure 8. Test results of receiver test board with K28.5 and PRBS7 input signals and 60 dB attenuation.
Other eye diagrams with different input streams and attenuation levels can be found in the
Appendix C. The eye diagrams that were obtained proved that the receiver board was successful
in receiving the test signal.
The testing phase of the receiver board was thus completed
successfully.
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Optoelectronic Link Design
Selection of VCSELs
After extensive online research and careful consideration (including cost), two
connectorized and one unconnectorized VCSELs were chosen: the Honeywell HFE4384-522 and
HFE4391-541, and the Optek OPV210, respectively.
Connectorized components have the
advantage over their unconnectorized counterparts in that they are pre-aligned, ensuring that
optimal power is launched from the transmitter into the fiber optic cable. No single VCSEL
possessed all the desirable characteristics. The table below gives a summary of the VCSELs that
were chosen and their respective characteristics (red indicating estimated values).
Table 3. VCSEL Characteristics
The Optek OPV210 appeared to be the best among the three VCSELs, having a relatively high
slope efficiency and low threshold current. Unfortunately it was unconnectorized, which meant
that it would have to manually aligned to prevent loss of power from the VCSEL into the fiber
optic cable.
Selection of PDs
One connectorized and two unconnectorized photodiodes were chosen, namely, the
Lasermate RDS-M85A306, Hamamatsu S7912, and Optek OPF420 PDs. Table 4 shows the PDs
chosen.
Table 4. PD Characteristics
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Again, no single device proved to possess all of the optimal characteristics. For example, the
unconnectorized Optek OPF420 PD features high responsivity but high capacitance. The
Lasermate RSC-M85A306 has a relatively low responsivity but lower capacitance than the
Optek.
Optical Link Budget
The Optical Link Budget is a logical way of designing the gigabit optoelectronic link. It
tracks the allocation of available optical power (transmitted into the fiber by the VCSEL) among
various loss-producing mechanisms such as launch coupling, fiber attenuation, and connector
losses, in order to ensure that adequate signal strength (optical power) is available at the receiver
end of the link. The worst-case scenarios are taken into consideration in all calculations.
The first design parameter to be determined in the design was to ensure that the
maximum output power of the VCSEL, Pout(max),VCSEL, would not exceed the eye safe power limit
specified by the 802.3z spec. This was determined to be 0.78 mW [1], conforming to Class 1
laser standards set by the International Electrotechnical Commission (IEC). Class 1 lasers are
safe under reasonably foreseeable conditions for operation. Next, a graph of output power, Pout,
against total input current, Itot, was taken from a suitably chosen VCSEL datasheet [2] (shown
below in Figure 9).
Figure 8. Output Power vs. Input Current for VCSEL.
From Figure 9, the equation for the graph was determined to be
Pout   ( I tot  I th )
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(Eq. 1)
Where η is the slope efficiency and Ith is the threshold current. The value of Itot(max) can
now be determined by fixing the value of Pout(max),VCSEL and reading off the characteristics of η,
Ith , and Vf from their respective VCSEL datasheets.
A separate set of values of the total current, Itot(min) was calculated, taking into account an
extinction ratio of 9 dB. The extinction ratio, defined as the ratio of maximum optical power
generated when the VCSEL is “on” to minimum optical power generated when the VCSEL is
“off”, should be taken into consideration as it strongly influences receiver sensitivity. Using this
ratio, the value of Pout(min),VCSEL, was calculated using Equation 2.
Pout(min),VCSEL  9dB * Pout(max), VCSEL
(Eq.2)
This value represents the maximum power output of the VCSEL when it is off (hence the
minimum output power). The range of values of Itot(min) was then calculated, again using
Equation 1.
The modulation current, Imod, represents the current swing that the VCSEL can receive.
Equation 3 represents this relationship.
I mod  I tot,max  I tot,min
(Eq. 3)
The total current into the laser, or the current out of the laser driver, Itot, consists of two
components: modulation current to transmit data and bias current to set the laser above threshold.
Thus, a maximum total current of Ibias plus Imod can flow through the VCSEL. Equation 4
describes this relationship.
I tot(max)  I bias  I mod
(Eq. 4)
With the calculated value of Itot(max) and the threshold current, Ith, known, Imod can be
found. The modulation current should fall between 2mA and 30mA since these are the current
limits that the MAX3266 laser driver can provide [3].
For the calculations above, a four-corner analysis approach consisting of maximum/
minimum combinations of slope efficiency and threshold current was performed to obtain the
range of values of Itot, Imod, and Ibias.
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The laser driver consists of two resistors, Rmod and Rbias. To determine the value of Rmod,
a graph of Rmod vs. Imod was plotted using sets of values taken from the MAX 3287 datasheet [3]
for deterministic jitter. This graph is shown in Figure 10.
Rmod (kohms)
Graph of Rmod (kohms) vs Imod(mA)
14
12
10
8
6
4
2
0
y = 73.361x -1.0712
0
10
20
30
40
Imod (mA)
Figure 10. Graph of Rmod vs. Imod.
The equation relating Rmod and Imod was determined to by performing an exponential fit to the
sample values. This equation is given in Equation 5.
Rmod  73.361( I mod ) 1.0712
(Eq. 5)
The equation to determine the value of Rbias was found to be
Rbias 
5 Vf
I bias
(Eq. 6)
The values of Rbias and Rmod are implemented using potentiometers to span the entire
range of resistance values. The potentiometer to use for Rmod was selected to ensure that it
would span the entire range of Rmod. However, for Rbias an additional resistor, Rs, is connected in
series with a potentiometer. To obtain the values of Rs and the potentiometer, the minimum and
maximum values of Rbias were first identified. The value of Rs was set to the minimum value,
while the potentiometer was chosen so that it would provide the necessary resistance swing
between the maximum and minimum Rbias value.
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With the output of the VCSEL known, the input power of the PD, Pin,PD, can be calculated
by taking into account a maximum fiber attenuation of 7.5 dB. Equation 7 shows how P in,PD is
obtained.
Pin, PD = 7.5 (dB) * Pout(max), VCSEL
(Eq. 7)
With the input power of the PD known, the output current of the PD, Iout,PD is calculated
using the relationship shown in Equation 8.
Iout,PD = Responsivity * Pin, PD
(Eq. 8)
The output current of the PD goes in the MAX3266 transimpedance amplifier. The range of
values accepted by the TIA is 20 uA and 1 mA, as determined from the data sheet [4]. From the
MAX 3266 transimpedance amplifier DC Transfer curve [4], the corresponding output voltage is
read. The complete calculations are located on the group 3 website under Optical Link Budget.
Financial Budget
The group was allotted $350 for this project. This would include the total costs of the
VCSELs, PDs, passives, and miscellaneous items like shipping and handling. At the end of the
project, it will also be necessary to determine the cost to mass-produce the transceiver. The
financial budget to date is shown below.
Table 5. Financial Budget
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The rightmost column provides information on the initial projection of the cost to put the board
through two runs. To its left is the amount that the group has spent so far. It can be seen that the
group is well within its budget and has ample funds left for a second board run if the need arises.
Transceiver Design
The design of the transceiver consists of both a schematic and layout, which were created
using ExpressSCH and ExpressPCB, respectively. The receiver and transmitter were designed to
share a common power supply, though otherwise only share the board.
Due to the high
frequency signals in the transmitter, a power supply filter is required to protect the sensitive
receiver. The schematics were created first from which two electrically isolated layouts were
designed.
Receiver Schematics
The receiver schematics were heavily modeled off the provided receiver test board
schematic, which is shown below.
Figure 11. Schematic of provided receiver test board.
The only modification needed was to convert the circuit from an electrical to an optical input.
This was accomplished by replacing the SMA connector with a photodiode. The change resulted
in the removal of J3, R2, and C6 from the above schematic. The revised receiver schematic
follows.
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Figure 12. Final schematic of receiver.
Transmitter Schematics
The transmitter design began with the typical application circuit provided in Maxim’s
datasheet for the laser driver (MAX3287), as shown below [3].
Figure 13. Excerpt from Maxim datasheet of typical application circuit for MAX3287.
This circuit was modified by first removing the bias adjustment transistor and the feedback loop
photodiode. Since the BIASDRV pin was not used, the capacitor on that pin was also not needed.
Then, the FLTDLY pin was grounded directly and the capacitor on this pin was removed. The
resulting transmitter design schematic is shown below.
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Figure 14. Finalized transmitter schematic design.
Miscellaneous Components on Schematics
Besides just the receiver and transmitter, there were a few other modules in the
schematics. First, the power supply filter was needed between the power supplies of the receiver
and the transmitter. The design for this came from two different sources: [6] and [7]. The
capacitor values were all changed to 0.01μF for a slightly higher frequency pass through
compared to the 0.1μF capacitor. The large capacitors were not needed and consequently
omitted completely since they filter out lower frequencies. The complete power supply filter is
shown below.
Figure 15. Schematic of power supply filter.
The other two modules on the schematics are the power supply connector and the ground
shunt. The power supply connector is used to get power to the entire board, while the ground
shunt is used to connect the ground planes of the receiver and transmitter. They are connected at
one single point in order to minimize interference between the two. The connector and shunt are
shown below.
Figure 16. Schematic of power connector and ground shunt.
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Board Layout
The board layout was done using a few primary layout guidelines while optimizing for
specific critical paths. All components were placed with the intent to minimize space required
while still allowing enough room for all the signals to be routed on the top of the board. The
bottom of the board was used as the ground plane so all other signals had to fit on the top. Signal
lengths were minimized to avoid creating transmission lines. All bends in routes were set at
forty-five degrees to avoid reflections of high frequency signals except in the power nets since
they are DC signals. Care was taken to match lines for the differential signals to ensure correct
signal timing. A short ground return was critical from the load on the transmitter, so the resistor
was placed as close as possible to the VCSEL. The ground signals from these two parts were
routed together and then through a ferrite bead before reaching ground. This allows the option of
populating the ferrite bead with the intent of blocking high frequencies or just shorting the pads
together if it does not improve the signal.
The first attempt at the transceiver layout is shown below without a power supply filter.
Figure 17. First layout of transceiver.
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From here, many changes were made. First, the ferrite beads were pulled out to allow the
shortest path possible between the VCSEL and the laser driver. The VCSEL placement was also
optimized for this path. The two capacitors leading to the SMA connectors in the transmitter
were moved to keep them from appearing as a right angle with the resistor. This was necessary
to make a smoother path for the signals and prevent reflections. Next, the PD was moved to the
other side of the TIA to make the routes shorter between these two parts. Through all of the
changes, the VCSEL and PD were spaced further apart than the goal of duplex connector
spacing. However, because two complete transceivers fit on one board, the best compromise
was to create two different designs, allowing both to be tested with one board fabrication.
The first design is a conservative design that keeps all lines as short as possible, and the
output lines from the laser driver are symmetrical as well as matched. The final layout of the
conservative design is shown below.
Figure 18. Conservative transceiver layout.
Figure 19. Aggressive transceiver layout.
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The second is a more rigorous design shown above in Figure 19 where the goal is to align the PD
and the VCSEL to fit the duplex connector, while still trying to keep the original layout as much
as possible in hopes of success. This required some components to be moved away from their
ideal position. The output SMA connectors are moved to the far right edge of the board, which
prevents them from having symmetrical paths to the laser driver; however, their lengths are still
matched.
Assembly and Transceiver Testing
After the PCB returned from fabrication, board assembly and testing began. All testing
so far has been done with the PBRS7 signal. First, only the components for the receiver were
soldered onto the conservative side of the PCB, and the receiver was tested. This was done to
see if the receiver worked before actually soldering on any of the transmitter components. This
way, if it did not work once the other components were soldered on, the problem would be easily
identified without actually having to cut the connection between the two. The results were that
the receiver board worked fairly well as shown below with the eye diagram resulting from
testing with a PRBS7 signal.
Figure 20. Eye diagram for testing with PRBS7 signal
The results of testing with other signals are found in Appendix D. Then the two potentiometers
were mapped out to find the resistance with each turn and were both set to their maximum
values. The transmitter components were soldered on to the same half of the board without
populating the optional ferrite bead, L7, and it was tested. With the initial biasing, there was not
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an output from the VCSEL, though one was hardly expected with very small currents. The two
potentiometers were slowly adjusted one at a time down to their design values, but the only
results were a completely closed eye. This indicated that the board had power but most likely the
VCSEL was not biased correctly. After reviewing the board and the schematics again, the two
potentiometers were determined to be switched on the board. They were removed and soldered
on correctly, and the transmitter was retested. The combinations tested are in the following table
with the design values in bold.
Table 5. Combinations of two potentiometers.
#
Rbias-Ohms
Rmod-kOhms
#
Rbias-Ohms
Rmod-kOhms
1
1300
45.0
19
783
45.0
2
1300
38.6
20
783
38.6
3
1300
32.2
21
783
32.2
4
1300
25.8
22
783
25.8
5
1300
19.4
23
783
19.4
6
1300
13.0
24
783
13.0
7
1128
45.0
25
610
45.0
8
1128
38.6
26
610
38.6
9
1128
32.2
27
610
32.2
10
1128
25.8
28
610
25.8
11
1128
19.4
29
610
19.4
12
1128
13.0
30
610
13.0
13
955
45.0
31
438
45.0
14
955
38.6
32
438
38.6
15
955
32.2
33
438
32.2
16
955
25.8
34
438
25.8
17
955
19.4
35
438
19.4
18
955
13.0
36
438
13.0
The results began the same without an output for the combinations above numbered 1
through 11, which can be found in Appendix D. Combinations 12 through 18 ranged from a
completely closed eye to some areas of slightly higher concentration than others. Combination
number 19 was the first where an eye was noticeable and is shown below (left). As both values
were lowered even more, eventually a clean eye diagram was obtained with combination 36 as
shown in the following figure (right).
21
Figure 21. Eye diagram for combination 19 and 36
Since the receiver and transmitter were both working independently, the next test was the
loopback test to determine the affects of running both simultaneously. The result of this test
using a PSRS7 signal with the resistors still in their optimal positions is shown below (left).
When a 5dB optical attenuator was inserted in path between the PD and the VCSEL, the results
were as follows (right).
Figure 22. Eye diagram for transceiver using a PSRS7 signal without attenuation and with 5 dB attenuation
The loopback eye diagram with out attenuation shows more jitter than the transmitter and
receiver each, indicating some noise transferred between the two. The eye diagram of the
loopback test with 5dB attenuation shows that the signal was attenuated too much for the
22
receiver. This could be due to a number of different things. First, the power out of the
transmitter is unknown. It should be close to the design value of 0.78mW, but thus far it has not
been determined. The sensitivity of the PD may be too low to detect the signal. Ideally, the
power out of the transmitter will be measured and if needed, the transmitter will be adjusted to
output the correct power. The currents, Imod and Ibias, will be measured to determine the actual
biasing of the VCSEL. Then, ideally, the sensitivity of the PD will be determined using several
small attenuators.
The last test completed to date of the transceiver is the receiver sensitivity. When
inserting the smallest attenuator available of 5dB, the results were as follows.
Figure 23. Eye diagram for receiver sensitivity test
This indicates that the receiver is not sensitive enough to detect this signal. Again, the input
power before the attenuator is unknown, so for now, this test does not bear much significance.
Future Plans
The next step in this project is to finish testing the transceiver. When the conservative
design is completely tested, the more aggressive layout of the transceiver will be assembled and
all tests repeated. The effects of the layout on the transceiver performance will be noted.
Assuming the aggressive layout still meets the specifications, the VCSEL will be replaced by an
unconnectorized VCSEL for alignment tolerance testing.
Conclusion
Overall, the project has been successful thus far, encountering few problems with easy
solutions. The design, build, and testing of both the test receiver and the transceiver was done
23
carefully, paying attention to detail and being alert of any problems. The current status of the
project shows that group 3 is on track, but that this pace must be kept to ensure completion.
After the completion of the tasks outlined in future plans, a cost analysis of the mass production
of the transceiver will be performed. This analysis will help determine the feasibility of a
Gigabit Ethernet Optical link.
24
References
1.
Lightpointe, “White Paper: Free-Space Optical Laser Safety.” April 2001.
March 2003<http://www.essentia.it/documenti/WP_Articoli_Tecnici/LigthPointeWhitePaper_FSO_Human_Safety.pdf>
2. Honeywell, “HFE438x-522 SC Connectorized High Speed VCSEL 1.25Gbps.” December
2000. 12 March 2003 <http://content.honeywell.com/vcsel/pdf/HFE4383,4384.pdf>
3. “Maxim Quick View Data Sheet.” Maxim December 2002. 13 March 2003
<http://pdfserv.maxim-ic.com/arpdf/MAX3286-MAX3299.pdf >
4.
“Maxim Quick View Data Sheet.” Maxim June 2001. 13 March 2003
<http://pdfserv.maxim-ic.com/arpdf/MAX3266-MAX3267.pdf >
5. “Maxim Quick View Data Sheet.” Maxim July 2001. 13 March 2003
<http://pdfserv.maxim-ic.com/arpdf/MAX3264-MAX3765.pdf >
6. “Delta Electronics Specifications.” November 2002. 15 March 2003
<http://www.deltaww.com/products/fiberoptical/pdf/BiDi/BIDI155FIJI.pdf>
7. “E20 GBIC App Note.” April 2001. 15 March 2003
<http://www.e20inc.com/pdf/GBICAPNA.pdf>
8. “IEEE 802.3z Specification.” pp. 106-107. March 2001. 17 March 2003
<http://standards.ieee.org/getieee802/download/802.3-2002.pdf>
25
Appendix A: IEEE 802.3z Tables
Both charts may be referenced by [8].
26
Appendix B: Gantt Charts
Figure 1. Gantt chart for January 16.
Figure 2. Gantt chart for January 23.
27
Figure 3. Gantt chart for January 30
Figure 4. Gantt chart for February 13
28
Figure 5. Gantt chart for February 20.
Figure 6. Gantt chart for February 27.
29
Appendix C: Eye Diagrams from Test Receiver Board
Figure 1. Eye diagram for testing with PRBS7 signal at 0 dB and 10 dB
Figure 2. Eye diagram for testing with PRBS7 signal at 20 dB and 30 dB
Figure 3. Eye diagram for testing with PRBS7 signal at 40 dB and 50 dB
30
Figure 4. Eye diagram for testing with PRBS7 signal at 60 dB and 70 dB
Figure 5. Eye diagram for testing with D21.5 signal at 0 dB and 10 dB
Figure 6. Eye diagram for testing with D21.5 signal at 20 dB and 30 dB
31
Figure 7. Eye diagram for testing with D21.5 signal at 40 dB and 50 dB
Figure 8. Eye diagram for testing with D21.5 signal at 60 dB and 70 dB
Figure 9. Eye diagram for testing with K28.7 signal at 0 dB and 10 dB
32
Figure 10. Eye diagram for testing with K28.7 signal at 20 dB and 30 dB
Figure 11. Eye diagram for testing with K28.7 signal at 40 dB and 50 dB
Figure 12. Eye diagram for testing with K28.7 signal at 60 dB and 70 dB
33
Figure 13. Eye diagram for testing with K28.5 signal at 0 dB and 10 dB
Figure 14. Eye diagram for testing with K28.5 signal at 20 dB and 30 dB
Figure 15. Eye diagram for testing with K28.5 signal at 40 dB and 50 dB
34
Figure 16. Eye diagram for testing with K28.5 signal at 60 dB and 70 dB
35
Appendix D: Eye diagrams from Testing Transceiver
Figure 1. Results for combinations 1 through 11.
Figure 2. Results for combinations 13 through 18.
36