Download Appendix-A: Instruction Set of 8086

Appendix-A
Instruction Set of 8086 Microprocessor
A.1 : Anatomy of an Assembly Statement
An ‘assembly statement’ is a command to the CPU to carry out a ‘basic’ task like: data exchange
or ALU operation or program branching. The general format of an assembly statement is:
L1: mov
L1: mov
L1: mov
L1: mov
L1: mov
L1: mov
mov
mov
mov
mov
 L1: mov





data_destination, data_source
d, s
al, s
al, (03120h)
al, (00000 + 3000+ 0100 + 20)
ax, 0000h
ds, ax
bx, 3000h
di, 0100h
al, BYTE PTR ds:[bx + di + 20h]
al, BYTE PTR ds:[bx + di + 20h]
Data Destination
L1:
mov
Opcode
; 20-bit physical address cannot be directly given
; ds:[bx + di + 20h] is evaluated to 03120h
; ds:[bx + di + 20h] is evaluated to 03120h
20-bit Physical
Address = PA
16-bit Effective
Address = EA
Operators
Label
; this is a read operation
; this is a read operation
; this is a read operation
; data read from memory location 030120h
al, BYTE PTR ds: [bx] + [di] + [20h]
Displacement
; ds:[bx] + [di]+[20h]is evlauated to 03120h
Comment
Data Source
Operand
Assembly Instruction
GM: 1006ax : 16-12-06
Assembly Statement
Figure-A.1: Diagram showing various Fields of an Assembly Statement
In Fig-A.1, we find that an assembly statement consists of four fields (four columns), which are:
i. The Label field, which is optional for some instructions.
A label (L1:) is a symbolic name followed by a colon (:). It represents the 20-bit address of a
memory location, which contains the 1st code byte of an instruction. For example: In the code
listing of Page-122, the address value for label L1 is 01000 (0000:1000). This location contains
the code byte EB of the instruction. The next code byte 03 will be stored at the next memory
location of address 0000:1001, and so on.
The label is optional. It means that the placement of label is not mandatory for every
instruction. It is up to the programmer to decide where to place the labels to make the program
working and improving its clarity and readability.
169
ii. The Opcode (operation code) field, which is a compulsory field. It is impossible to write a
CPU instruction without an opcode.
iii. The Operand field, which is optional for some instructions. The nop and hlt instructions do
not have any operand.
iv. The Comment field, which is optional for all instructions. The comment field begins with a
semicolon (;) sign, which prevents n the assembler from reading the characters that follow the
semicolon. Comment field allows keeping short notes about the purpose of the instruction and
it helps easy modification of the program at later times.
A.2 : Assembler Statement
Anatomy of an Assembler Statement
What is an assembler? It is a program (masm.exe), which converts an assembly program into
executable binary codes along with many other jobs stated below. An ‘assembly statement’ is a
command to the assembler (and not to the CPU) to carry out:
i.
ii.
iii.
iv.
v.
Allocate physical memory space (the CSM) for the storage of the program codes,
Deciding the beginning address of the CSM,
Allocating 20-bit physical addresses for all the labels of the assembly source codes,
Discarding the comment field, and
Getting correct machine codes for the assembly instructions by consulting a lookup
table. The lookup table is a complex data structure built within the assembler itself.
The following assembler statements are the integral components of any assembly program:
i. To be written at the top of the assembly program:
MYCODE
SEGMENT
ASSUME
ORG
cs:MYCODE
1000h
; we can write some other permissible value instead of 1000h
ii. To be written at the bottom of the assembly program:
MYCODE
ENDS
END
START
The general format of an assembly statement is:
MYCODE
SEGMENT
Name
para public 'code'
; this is the begining of logical code segment
Operand
Comment
Assembler Directive
Assembler Instruction
Assembler Statement
GM: 1006ax : 16-12-06
170
An assembler statement consists of:
i.
Name Field: It is optional for some of the assembler instructions. The name MYCODE
refers to the ‘Logical Name’ for a memory segment that will be used by the program. The
name also initiates the beginning point of the memory segment. The fact that the ‘Logical
Name – MYCODE’ refers to a memory segment: is evident from the SEGMENT directive
of the statement. The type of segment (CSM or DSM or ESM or SSM) to which the name
refers to is yet to be known by looking at the ASSUME directive
ii.
Directive Field: It is a compulsory field. SEGMENT directive tells the assembler to allocate
some part of the available memory space for the user program. ASSUME directive tells the
assembler to convert the segment’s Logical Name (the MYCODE) into a Physical Segment
(the Code Segment, CS). The ORG directive sets the starting address at location 0000:1000
(01000h). The ENDS directive marks the end of the CSM. The END directive marks the end
of the assembly program that begun with the START: label.
iii.
Operand Field: It is a compulsory field. The operand, cs:MYCODE converts the logical
segment (MYCODE) into a physical segment (the Code Segment).
iv.
Comment Field: It is an optional field that carries meaning similar to an assembly
statement.
A.3 : Commonly used Assembler Directives
Directive
.286p
.287
ASSUME
ORG
ENDS
END
EQU
COMMENT
=
DB
DW
DD
Function
Enables assembly of protected mode 80286
Enables assembly of 80287, 8087
Converts a logical memory segment into a physical
segment
Sets the offset part of the beginning address of CSM
with respect to 00000
Marks the end of a memory segment
Marks the end of a program with the beginning label of
START
A named variable is replaced by the operand
A block of text is considered as comment
Assigns a 16-bit unsigned numerical value to the
named variable (X)
Allocates and initializes one Byte (8-bit) storage for the
named variable (FLAG1)
Allocates and initializes one word (16-bit) storage for
the named variable (FLAG2)
Allocates and initializes double word (4 bytes) for a
named variable (FLAG3)
171
Example
ASSUME
cs:MYCODE
MYCODE
ORG
1000h
ENDS
END
START
PAR
EQU
Comment &
………………
…………….
&
X = 12h
3600h
FLAG1
DB
xxh
FLAG2
DW xxxxh
FLAG3
DD
xxxxxxxxh
DQ
DT
INCLUDE
IF
expr
…….
ELSE
……
ENDIF
IFE expr
………..
ENDIF
REPT expr
………….
ENDM
PROC
……..
ENDP
IFIDN x1, x2
………….
ENDIF
IFDIF x1, x2
…………
ENDIF
MACRO x1,,,
………….
ENDM
Allocates and initializes a quad word (8 bytes) for a
named variable (FLAG4)
Allocates and initializes 10 byes storage area for a
named variable (FLAG5)
Allows automatic insertion of external ASM codes of
file b1.asm
Assembly codes following IF directive are executed if
the operand expr is evaluated to a non-zero value.
ENDIF must mark the end of any conditional-assembly
block module.
Assembly codes following the IFE directive will be
executed if the value of the operand expr is zero.
ENDIF must mark the end of the conditional assembly
block.
Assembly codes following REPT (repetition) directive
are executed for number of times specified by the
operand expr. The ENDM directive must mark the end
of a repeat block module.
Marks the beginning of a named procedure
(subroutine). The ENDP directive must terminate the
procedure.
Assembly codes following IDIDN directive will be
executed if the operands x1 and x2 are identical.
FLAG4
DQ
xx…….xxh
FLAG5
DT xx……..xxh
INCLUDE d:\mtk8086\b1.asm
X1
DB 00h
IF X1
…………
ELSE
……….
ENDIF
Y = 0
REPT 10
Y = Y+1
LOC
DB
Y
; Y is saved
ENDM
BIN2BCD PROC
……….
BIN2BCD ENDP
Assembly codes following the IFDIF will be executed
if the operands x1 and x2 are different.
Assembly codes that follow the MACRO directive will
be copied every time the MACRO’s name is inserted.
The MACRO allows passing arguments by its
operands. The ENDM must mark the end of the code
block under MACRO directive.
172
ADDX
MACRO x1, x2
mov
al, x1
add
al, x2
ENDM
A.4 : Commonly used Assembler Operators
Operator
* x1, x2
/ x1, x2
MOD x1, x2
SHL count
SHR count
NOT expr
AND x1, x2
OR x1, x2
XOR x1, x2
+ x1, x2
- x1, x2
+ x1
- x1
EQ x1, x2
GE x1, x2
GT x1, x2
LT x1, x2
LE
x1, x2
LENGTH
SIZE
OFFSET
SEG
:
BYTE
WORD
DWORD
PWORD
Function
Multiplies two expressions
Divide expr1 by expr2 to get the quotient
Divide expr1 by expr2 to get the remainder
Shift left by number of counts specified in the operand
filed
Shift right by number of counts specified in the operand
field
Performs bit wise inverse operation on the operand
expression
Performs bit wise logic AND operations on two
expressions
Performs bit wise logical OR operations on two
expressions
Performs bit wise logical XOR operations on two
expressions
Performs addition on two expressions
Performs subtraction on two expressions
Unary operation done on x1 to retain the current sign
Unary operation done on x1 to retain the current sign.
After the operation, how what figure would be stored in
al-register. CC? Why? (-34h = -51 = …..?)
x1 and x2 are compared and returns –1 (0) if they are
equal or not. The value comes via al-register.
x1 and x2 are compared and returns –1 (0) if x1  x2
or not
x1 and x2 are compared and returns –1 (0) if x1 > x2
or not
x1 and x2 are compared and returns –1 (0) if x1 < x2
or not
x1 and x2 are compared and returns –1 (0) if x1  or
not
Returns the size (byte or word) of the operand via cxregister
Returns the total number of bytes allocated for the
operand via bx-register
Returns a number indicating how far the operand (label
L12) is from the Origin
Returns the segment part of the address of the operand
Allows overriding the default segment of an offset
pointer
Data size is 8-bit
Data size is 16-bit
Data size is 4-byte
Data size is 6-byte (used in 80286 to initialize PVAM
Mode registers
173
Example
mov ax, (12h * 34h)
mov ax, (34h / 12h)
mov ax, (34h MOD 12h)
mov al, 23h SHL 3
mov
al, 23 SHR 3
mov
al, NOT 12h
mov
ah, 23h AND 32h
mov
al, 34h OR 56h
mov
ah, 45h XOR 56h
mov
mov
mov
mov
al, 23h + 45h
al, 34h – 12h
al, + 12h
ah, -34h
mov
al, 12h EQ 12h
mov
al, 32h GE 12h
mov
al, 12h GT 10h
mov
al, 10h LT 12h
mov
al, 12h LE 12h
mov
cx, LENGTH table
mov
bx, SIZE array
mov
bx, OFFSET L12
mov ax, SEG L12
mov al, BYTE PTR cs:[bx]
By default: bx is attached with dsregister
A.5 : Table showing affects of 8086 Instructions on Flag Bits of Flag Register
Flag Register (FR) of 8086
8 7
15
X
 = Flag Bit is updated
x = Flag Bit remains undefined (it may be 0 or 1)
 = Flag bit remains same as before (not affected)
Category
Data Transfer
Shift/Rotate/Logical
String
Arithmetic Instructions
Program Transfer
Processor Control
X
X
X
O D
I
T
S Z X
Overflow Flag (OF)
Direction Flag (DF)
Interrupt Flag (IF)
Trap Flag (TF)
Sign Flag (SF)
Zero Flag (ZF)
Instructions
Example
in, out, lahf, lds, lea, les, mov, pop, pusf, stos, xchg,
xlat, push
popf
sahf
and, cmp
neg
not
or
test
xor
rcl, rcr, rol, ror, sal,
sar, shl, shr,
cmps, lods
movs
scas
aaa
aad, aam
aas
add, sbb, sub, adc, cmp
cbw, cwd
daa, das
dec, inc
idiv
imul, mul
call, ja, jae, jb, jbe, jcxz, je, jg, jge, jl, Jle, jmp, jna,
jnae, jnb, jnbe, jnc, jne, jng, jnge, jnl, jnle, jno, jnp,
jns, jnz, jo, jp, jpe, jpo, js, jz, loop, loope, loopne,
loopnz, loopz, ret
clc
cld
cli
cmc
lock, nop, stc, wait
std
sti
174
0
A
X
P
X
C
Aux Flag (AF)
Parity Flag (PF)
Carry Flag (CF)
1x
O D I
  
Flag Bits
T S Z
  
A P
 
C



0



0
0
















































x


x
x
x












0



0
0




x
x
x


x

x












x
x











x
x











x
x




x

x




x
x




x

x




x
x





x





x
x




x

x




x
x





x





x










0



1



0



1



































0






A.6 : Classifications of 8086 Assembly Instructions
The instructions of the 8086 microprocessor can be grouped and sub-grouped into many classes,
which are shown below in a Table. The detailed study of the syntax and semantic rules of these
instructions would be discussed in later sections.
DATA
TRANSFER
General Purpose
mov
push
pop
xchg
xlat
Input/Output
in
out
SHIFT
/ROTATE/
LOGICAL
Shift
shl = sal
shr = sar
ARITHMETIC
PROGRAM
TRANSFER
PROCESSOR
CONTROL
String
movs
rep
cmps
scas
lods
stos
Addition
add
adc
inc
aaa
daa
Conditional
Transfer
Je = jz
Jl = jnge
Jle = jng
Jb = jnae
Jbe = jna
Jp = jpe
jo
js
Flag Operations
clc
cmc
stc
cld
std
cli
sti
Rotate
rol
ror
rcl
rcr
Subtraction
sub
sbb
dec
neg
cmp
aas
das
Logicals
not
and
or
xor
test
Multiplication
mul
imul
aam
Unconditional
Transfer
call
ret
jmp
External
Synchronization
hlt
wait
esc
lock
Division
div
idiv
aad
cbw
cwd
Iterations
Control
loop
loope = loopnz
jcxz
No Operation
nop
Address Object
lea
lds
les
Flag Transfer
lahf
pushf
popf
STRING
jne = jnz
jnl = jge
jnle = jg
jnb = jae
nbe = /ja
jnp = jpo
jno
jns
Interrupts
int
into
iret
175
A.7 : Summary of 8086 Assembly Instructions
mov
pop
xchg
in
lea
les
lahf
pushf
movs
scas
stos
Repe = repz
DATA TRANSFER INSTRUCTIONS
General Purpose
Move byte or word
Push word onto stack
push
Pop word off the stack
Translate byte of al-register
xlat
Exchange between two storage locations
Input/Output
Input byte or word
Output byte or word
out
Address Object
Load effective address
Get data from memory and load then into a
lds
pointer register and then into DS register
Get data from memory and load them
into a valid pointer register and then
into ES-register
Flag Transfer
Copy low byte of FR into ah register
Copy Ah-register into lower byte of Flag
sahf
Register
Push flag register onto stack
Pop word from top of stack and store it into
popf
flag register
STRING INSTRUCTIONS
Move byte or word string
cmps
Scan byte or word string
lods
Store byte or word string
rep
(Prefix) Repeat the string instruction repn/repnz
while not zero.
Compare byte or word string
Load byte or word string
Repeat
(Prefix) Repeat the string instruction while
not equal/zero
add
inc
daa
ARITHMETIC INSTRUCTIONS
Addition
Add byte or word
Add byte or word with carry
adc
Increment byte or word
ASCII adjust after addition
aaa
Decimal adjustment after addition
sub
dec
aas
Subtraction byte or word
Decrement byte or word
ASCII adjust after subtraction
mul
Subtraction
sbb
neg
das
Multiplication
Unsigned multiply byte or word
imul
aam
ASCII adjust after multiply
div
aad
cwd
Divide byte or word unsigned
ASCII adjust after division
Convert word to double word
Division
Idiv
Cbw
176
Subtract byte or word with borrow
Negate byte or word
Decimal Adjust after subtraction
Integer (Signed) Multiplication byte or
word
Integer (signed) divide byte or word
Convert byte to word
not
or
test
shl = sal
shr = sar
rol
rcl
ja/lnbe
jb/jnae
je/jz
jge/jnl
jle/jng
jne/jnz
jnp/jpo
jo
js
call
jmp
Loop
Loopne
=
loopnz
SHIFT/ROTATE/LOGICAL INSTRUCTIONS
Logical
Not byte or word
AND byte or word
and
Inclusive OR byte or word
Exclusive OR byte or word
xor
Test byte or word
Shift
Shift logical/arithmetic left
Shift logical right
shr
Shift arithmetic right
Rotate
Rotate left
Rotate right
ror
Rotate left through carry
Rotate right through carry
rcr
PROGRAM CONTROL INSTRUCTIONS
Conditional Transfer
Jump if above/Jump if not below not equal
Jump if above or equal/JUMP IF not
jae/jnb
below
Jump if below/Jump if not above not equal
Jump if carry
jc
Jump if equal/Jump if zero
Jump if greater/Jump if not less nor
jg/jnle
equal
Jump if greater or equal/Jump if not less
Jump if less /Jump if not greater nor
jl/jnge
equal
Jump if less or equal/Jump if not greater
Jump if not carry
jnc
Jump if not equal/Jump if not zero
Jump if not overflow
jno
Jump if no parity/ Jump if parity odd
Jump if not sign
jns
Jump if overflow
Jump if parity/Jump if parity even
jp/jpe
Jump if sign
Unconditional Transfer
Call procedure (subroutine)
Return form procedure (SUR)
ret
Jump to a target location
Iteration Controls
Loop
Loop if equal = Loop if ZF=1
loope
=
loopz
Loop if Not Equal = Loop if ZF !=1
Jump if Register cx is Zero
jcxz
Interrupts
int
iret
clc
stc
std
sti
hlt
esc
nop
Software Interrupt
Return from Interrupt Subroutine
into
Interrupt if Overflow
PROCESSOR CONTROL INSTRUCTIONS
Flag Operations
Clear Carry Flag (CF) Bit
Complement Carry Flag (CF) Bit
cmc
Set Carry Flag (CF) Bit
Clear Direction Flag (DF) Bit
cld
Set Direction Flag (DF) Bit
Clear Interrupt Flag (IF) Bit
Cli
Set Interrupt Flag (IF) Bit
External Synchronization
Halt
Wait for Interrupt
Wait
Escape
Lock the Bus
Lock
No Operation
No Operation
177
Detailed Description of 8086 Instructions
Mnemonic
mov
Movement
push
Psuh
A.8 : Data Transfer (General Purpose)
Assembly Examples
moves from source to Example-1. 8-bit immediate data to any 8-bit
register
mov
al, 23h
Flags affected : unaffected
;-------------------------------------------------------Examle-2. 8-bit immediate data to a memory
Syntax: mov d, s
location of any memory segment pointed by a
valid offset pointing register
The source can be:
mov
BYTE PTR ds:[bx+10h], 23h
1. 8-bit or 16-bit direct (=immediate) data
mov
BYTE PTR ds:[di], 23h
2. 8-bit register or 16-bit register
mov
BYTE PTR ds:[si], 45h
3. one memory location
;----------------------------------------------------------4. two consecutive memory locations
Example-3. 16-bit immediate data to any 16-bit
register.
The destination can be:
mov
cx, 1234h
1. 8-bit register or 16-bit register
;-----------------------------------------------------------2. one memory location
Example-4.
16-bit data to two consecutive
3. two consecutive memory locations
memory locations of any memory segment pointed
by a valid offset pointing register
mov
WORD PTR ds:[bx+12h], 1234h
mov
WORD PTR cs:[bx+di], 4567h
;-----------------------------------------------------------Example-5. Between any two 8-bit registers
mov
al, bl
;----------------------------------------------------------Example-6. Between any two 16-bit registers
mov
bx, cx
;----------------------------------------------------------Example-7. Between an 8-bit register and a
memory location of any segment
mov
BYTE PTR ds:[bx+12h], al ; write
mov
al, BYTE PTR es:[bx+12h] ; read
;----------------------------------------------------------Example-8. Between a 16-bit register and two
consecutive memory locations
Meaning
Meaning: Data
destination.
Meaning: A programmer may execute this
instruction at any point in the MLP, or at the
beginning of a SUR/ISR to save 16-bit data
into two empty locations of ‘Stack Segment
Memory’. The empty locations are pointed by
TOS (Top of Stack).
Flags affected: unaffected
Syntax: push
s
mov
WORD PTR ds:[bx+23h], ax ; write
mov
ax, WORD PTR es:[bx+23h] ; read
Example-9. Stores content of a 16-bit register
into two empty locations of stack
push
ax
push ax instruction decrements the stack pointer
register (SP) by two. The CPU performs the
following instruction (beyond the knowledge of
user) to store the content of ax-register into
locations < 08FFE, 08FFF>.
sub sp, 0002h
mov WORD PTR ss:[sp], ax
The source can be:
178
BAS
SBA
1x
pop
pop
Meaning: A user may execute this instruction
at any point in the MLP or at the beginning of
a SUR/ISR to retrieve 16-bit data from two
empty locations of ‘Stack Segment Memory’.
The empty locations are pointed by TOS (Top
of Stack).
Current TOS
Stack Grows
d
BAS
The destination can be:
1. a 16-bit register except Flag Register
2. two consecutive memory locations
1x
SBA
SSM
09000 Filled up
08FFF
08FFE
08FFD
08FFC
07000
00000
WORD PTR ds:[bx]
Example-13. 8-bit data exchange between two 8bit registers
xchg al, bl ; (al)  bl, (bl)  al
;-----------------------------------------------------------Example-14. 16-bit data exchange between two
16-bit registers except the segment and flag
registers.
xchg ax, bx
xchg ds, ax ; not valid with segment registers
;-----------------------------------------------------------Example-15. Exchanges 8-bit data between a
GPR register and a memory location
xchg al, BYTE PTR ds:[bx]
xchg BYTE PTR cs:[bx], cl
Flags affected: none
xchg
Exchange
00000
pop ds instruction performs the following
instructions to bring 16-bit data from stack into dsregister. After this, the CPU adds 02h with spregister and brings the TOS in the previous
position.
mov ds, WORD PTR ss:[sp]
add
sp, 0002h
;-----------------------------------------------------------Example-12. Retrieves 16-bit data from Top-ofStack into two consecutive memory locations
pop
Meaning: Simultaneous data exchange takes
place between two storage locations.
07000
;-----------------------------------------------------------Example-10. Store content of two consecutive
memory locations of any segment into two empty
locations of stack
push
WORD PTR ds:[bx]
Example-11. Retrieves 16-bit data from Top-ofStack (TOS) into a 16-bit register
pop ds
Flags affected: none
Syntax: pop
SSM
09000 Filled up
ah
08FFF
08FFE
al
08 FFD
08FFC
Empty Spce
TOS
Stack Grows
TOS after push ax
Empty Space
1. a 16-bit register except Flag Register
2. two consecutive memory locations
Syntax:
1. Assembly Code: xchg d, s
2. Pseudo Code: (al)  (bl)
The source and destination can be:
1. 8-bit register
2. 16-bit register
3. one memory location
4. two consecutive memory locations
179
xlat
Translation
or
xlatb
Translate a
Byte in
al register
Meaning: 8-bit content of al-register is
translated (transformed / converted) into
another form of 8-bit by consulting a memorybased Lookup Table (LUT). The OFFSET (the
distance of the table from the current
instruction) of the LUT must be in bx-register.
The result is kept in the al-register.
Syntax: xlat
Example-16. Exchanges 16-bit data between a
16-bit GPR register and two memory locations of
any valid segment
xchg WORD PTR ds:[bx], ax
Example-17. Converting content of al-register
(03h) into its ASCII code of 33h.
mov
bx, OFFSET LUT
mov
al, dbyte ; dbyte = data byte
xlat
; (al) = new data from LUT
LUT
DB ‘0’, ‘1’, ‘2’, 3, … , ‘9’
LUT is the name of the Table containing ASCII
codes for the digits 0, 1, … , 9. The execution of
the instruction xlat involves the following steps:
a. offset part (16-bit) of the name LUT is passed
to bx-register
b. CPU executes the following instruction, where
displacement part has been taken from alregister
Mnemonic
in
Input
mov al, BYTE PTR cs:[bx+03h]
A.9 : Data Transfer (Input/Output)
Meaning
Assembly Examples
Meaning: Data comes into al ( or ax) Example-18. Read 8-bit data into al-register from
register from one (two consecutive) ports.
a fixed port
in
al, 22h ; port address is 22h
Syntax:
or
1. Assembly Code: in d, s
PAR EQU 22h
2. Pseudo Code: al  (port)
in
al, PAR
PAR is symbolic name for the port of address 22h
;----------------------------------------------------------Example-19. Read 16-bit data into ax-register
from two
consecutive fixed ports
in
ax, 22h
(22h and 24h are the consecutive addresses of two
fixed ports. 8-bit data of port location 22h will
enter into al register. Data from port location 24h
will enter into ah register).
;-----------------------------------------------------------Example-20. Read 8-bit data into al-register from
a variable port, whose 16-bit address is in dx
register.
mov dx, 3606h
in
al, dx
; (dx) is not moving to al
or
PAR EQU 3606h
mov dx, PAR
in
a, dx
(8-bit data comes into al register whose address
3606h is in dx register). Pseudo Code: al  ((dx))
180
out
Output
Meaning: 8-bit (16-bit) data from al (ax)
register goes into one port (two consecutive
ports)
Syntax:
1. Assembly Code: out d, s
2. Pseudo Code: (al)  port
Mnemonic
lea
Load Effective
Address
lds
Load 16-bit
offset pointer
register and
also segment
register ds
Example-21. Read 16-bit data into ax-register
from two consecutive variable ports.
mov dx, 3604h
in
ax, dx
(al register will hold the content of port location
3604h. ah register will hold the content of port
location 3606h). Pseudo Code: ax  ((dx))
Example-22. Write 8-bit data form al-register
into a fixed port
out
22h, al
;----------------------------------------------------------Example-23. Write 16-bit data from ax-register
into two con3secutive fixed ports
out
22h, ax
;-----------------------------------------------------------Example-24. Write 8-bit data from al-register
into a
variable port
out
dx, al
(al) enters into port whose address is in dx
;----------------------------------------------------------Example-25. Write 16-bit data from ax-register
into two consecutive variable ports.
(al) enters into port whose address is in dx
(ah) enters into port with address (dx) + 02h
3
A.10 : Data Transfer (Address Object)
Meaning
Assembly Examples
Meaning: Loading effective address (16-bit Example-26. Loading the effective address of
offset part of a 20-bit instruction) of a target label L12 Into bx-register
object (memory location or Label) into an
lea
bx, L12
offset pointer register (bx, si, di, bp,sp).
L12: nop
Or
Syntax: lea L12
mov bx, OFFSET L12
L12: nop
Meaning: By default, we have the following
pointers to contain 20-bit address of a target
object: ds:[bx], es:[si], ss:[sp], and cs:[ip].
The lds instruction loads simultaneously both
the offset pointer register (bx, si, di, bp, sp)
and the segment register, ds. The 32-bit (16 +
16) value comes from a memory-resident
table.
Either of the above two instructions computes the
offset part (16-bit) of the Label L12 and puts
it into bx-register
Example-27. Loading ds:si from a table.
;- create data table first---mov ax, 0000h
mov es, ax
mov bx, 5000h
mov WORD PTR ds:[bx], 4321h
mov WORD PTR ds:[bx+02h], 8765h
lds
di, es:[bx]
Syntax:
lds pointer_register, table_address_pointer
BAE
SBA
181
05003
05002
05001
05000
ESM
87
65
43
21
00000
1x
In the above example, we have wished to load the
pointer ds:[bx] with the value 8765:4321, which
resides in a memory-based table of ESM segment.
lahf
Load Low byte
of Flag register
into AH
register
Synstx: lahf
pushf
PUSH Flag
Register into
Stack
popf
X C
0
1x
AH Register
Example-28.
assume FR = 1234h
lahf
; ( ah ) = 34h
Content of AH-register is copied into low byte
of FR.
Meaning: 16-bit content of FR-register is
stored into the empty space of the stack. The
empty space consists of ‘two stack locations’
and is pointed by TOS (Top of Sack) = ss:
[sp]. TOS always points ‘two empty
locations’ at just low ordered addresses.
mov
mov
mov
pushf
P
7
The source is: lower 8-bit of FR
The destination is ah-register
sahf
Store AHregister into
Low byte of FR
0
X
ax, 0000h
ss, ax
sp, 9000h ; TOS is at: 0000:9000
TOS is set at 0000:9000. So, the empty
locations are: 0000:8FFF and 0000:8FFE. So,
whenever we say TOS; we mean these two
Locations, which are ready to accept data.
Meaning: Opposite of pushf instruction
Content of stack location pointed by TOS will
be loaded in FR.
Pop (read)
from Stack into
Flag Register
After the execution of the above instruction, the
lower 8-bit (34h) of FR will enter into ah-register.
Example-29.
mov
ah, 23h
sahf
; (ah)  FRL ; (FRL) = 23h
Example-30.
TOS
Stack Grows
TOS after pushf
BAS
1x
SBA
07000
00000
After the execution of pushf instruction, the CPU
decrements the sp-register by 02h, and then
performs the write operation:
sub sp, 0002h
mov
WORD PTR ss:[sp], FR
Example-31.
Current TOS
Stack Grows
BAS
1x
182
SSM
09000 Filled up
FRH
08FFF
08FFE
FRL
08 FFD
08FFC
Empty Spce
Mnemonic
Similar to lds instruction; but now for any
valid offset pointer register and the segment Similar to lds instruction.
register es.
A.11 : Data Transfer (Flag Transfer)
Meaning
Assembly Examples
Meaning: The lower 8-bit of the flag register
Flag Register (FR) of 8086
(FR) of the 8086 microprocessor will be
15
8 7
copied into the ah-register of the MPU. This
X X X X O D I T S Z X A
is an indirect way of accessing the content of
the flag register.
SBA
SSM
09000 Filled up
08FFF
08FFE
08 FFD
08FFC
07000
00000
Empty Space
les
(Load a 16-bit
offset pointer
register and
also the esregister
Example-32
popf
After the execution of popf instruction, the CPU
reads the content of TOS into FR, and then adds
two with the stack pointer register sp. Stack Top
(TOS) comes back to original position.
Mnemonic
add
Addition
(valid for both
unsigned and
signed
numbers)
(08FFE, 08FFF)  FRL, FRH
(sp) + 0002h  sp
A.12 : Addition Instructions
Meaning
Assembly Examples
Meaning: Add two data (operand) without Example-33. 8-bit unsigned immediate data with
taking into consideration of the carry an 8-bit register.
generated in the previous operation
add al, 23h
;-----------------------------------------------------------Example-34. 8-bit unsigned immediate data with
O D I T S Z A P C
Flags affected:
the content of a memory location.
add BYTE PTR ds:[bx], 23h
;-----------------------------------------------------------Syntax:
Example-35. Between two 8-bit registers
1. Assembly code: add d, s
(unsigned)
2. Pseudo code : (s) + (d)  CF, d
add al, bl
The add instruction can be used to add both ;----------------------------------------------------------the unsigned and signed numbers in Example-36. Between an 8-bit registers and a
memory location (unsigned).
consultation with the flag bits.
After the addition, the result goes to
‘destination, d’ and the ‘Carry Flag, CF’. The
destination (also the source) can be:
a. an 8-bit data (not for destination)
b. a 16-bit data (not for destination)
c. an 8-bit register or a 16-bit register
d. one memory location
e. two consecutive memory locations
;-----------------------------------------------8-bit Unsigned Binary Number: All bits of a
given number (0000 0000 to 1111 1111) carry
positive positional values. Positional value of
a bit=Bit_value x Positional_Weight.
For example: 1010 1010 is equal to:
1x27+0+1x25+0+1x23+0+1x21+0 = +176. The
range of an 8-bit unsigned number is: 00h to
FFh = 00 to 255.
When two 8-bit unsigned binary (hex)
numbers are added, any carry generated from
MSBit is stored into the CF (Carry Flag) of
the 8086 processor. Hex (hexadecimal) system
is a compact form of binary and is used as a
matter of convenience.
;-------------------------------------------------;
16-Bit Unsigned Binary Number: All
183
add BYTE PTR ds:[bx], al
;----------------------------------------------------------Example-37. 16-bit immediate data with the
content of a 16-bit register (unsigned).
add ax, 2345h
;----------------------------------------------------------Example-38. 16-bit immediate data with the
contents of
two consecutive memory locations
(unsigned).
add WORD PTR ds:[bx], 1234h
;----------------------------------------------------------Example-39.
Between 16-bit GPR and the
contents of two consecutive memory locations
add WORD PTR ds:[bx], cx
;-----------------------------------------------------------Example-40. Between two 16-bit GPR registers
(unsigned).
add ax, bx
;----------------------------------------------------Exampl-41. Adding signed numbers: -32 and 78.
mov al, -32 ; (al) = 2’sC of -32 = E0
add
al, 78 ; (al) = E0+4E = 2E, SF=0, OF=0
;--how to extract correct sign and magnitude?—
The programmer knows that he is dealing with 8bit signed numbers. Therefore he has to check the
SF and OF flag bits. Both can’t assume 1s at the
same time.
If (SF=1)
features of an 8-bit unsigned binary number
are equally applicable for a 16-bit (even
higher) unsigned binary numbers.
;------------------------------------------------;
8-Bit Signed Binary Number: By saying
‘signed numbers’, we include both positive
and negative numbers. Now the question is:
How do we use an 8-bit register (say al) to
handle positive number and negative
numbers? The conventions are:
1. Lower 7-bits of the register are reserved to
accommodate the magnitude of a positive
number. The MSBit is always 0 and indicates
the + (plus) sign for the positive number.
Thus, using 8-bit capacity of a register, we can
represent a positive number of the range: 00h
to 7Fh = 00 to +127.
There is no scope to employ an 8-bit register
to hold positive number greater than +127
(say, +128). In this case, we have to use a 16bit register. Using a 16-bit register (say, ax),
we can represent a positive number of the
range: +0 to +32767.
2. Using an 8-bit register, we can represent a
negative number of the range: -128 to -1. The
MSBit is always 1 and carries negative
(minus) positional value of the number. Each
of the lower 7-bits carries positive positional
value.
Thus, the 8-bit register can hold a negative
number of the range: 10000 0000 to 1111
1111 = (-1x27 +0+0+0+0+0+0+0) to (1x27+1x26+1x25+1x24+1x23+1x22+1x21+1x20)
= -128 to -1 = 80h to FFh.
We can easily verify that 80h is the 2’s
complement form of -128 and FFh is also the
2’s complement (2’sC) form of -1. Hence, we
can state that the negative numbers are
represented in 2’sC form in 8086 architecture.
;-------------------------------------------------;
16-Bit Signed Binary Number: All features
of an 8-bit signed binary number are equally
applicable for a 16-bit (even higher) unsigned
binary numbers.
;-------------------------------------------------;
Overflow: In signed arithmetic (SA), the
addition of the positive numbers +127 and
+127 must produce a positive result of +254
and needs to be accommodated within the 8bits of the destination register.
184
All 8-bits of destination contains -ve result
Else
All 8-bit of destination represents +ve result
;----------------------------------------------------js
L12 ; -ve result
;-- +ve result---------Call BIN2BCD
Call SHOWPS ; show result 46 with +ve sign
Hlt
;----------------------L12: ;----negative result
;-----------------------------------------------------------Example-42. The processing environment is 16bit signed numbers. The ax-register has received
the data DATA1 (say, A897h= -22377) and the
cx-register has received DATA2 (say, 8200h = 32256). The final result is the addition of these
two numbers (1 2A97h = -54633). How can we
correctly extract the sign and magnitude of this
result?
add
ax, cx ; (ax) = 1 2A97 = (CF, ax)
;----manual addition-----------------------------DATA1 = A897 = 1010 1000 1001 0111
DATA2 = 8200 = 1000 0010 0000 0000
SUM = 1 2A97= 1 0010 1010 1001 0111
OF = 0, SF = 0, CF = 1
;----------------------------------------------------The programmer must know the size (number of
bits : 8 or 16 or 32 or …) and the sign of the
numbers he is dealing with, and only then he can
interpret the result to extract the correct sign and
magnitude of the result. The CPU will help the
programmer by providing values of the SF and OF
flag bits.
The following Flow Chart might help to determine
the sign and magnitude of result after add
operation on signed numbers.
1x
L1:
SA operation
L2:
Y
(OF)=1
?
N
L3:
(SF)=1
?
Y
L4:
-ve number
N
L6:
+ve number
L5:
ret
ret
mov al, 7Fh
add al, 7Fh
; +127
; (al) = FE = 1111 1110
In the above example, the MSBit is 1. So, it is
a negative number! It can’t be a negative
number; because we have added two positive
numbers (+127 and +127) and the result
should be a positive number of +254. Now,
what should we do to extract +254 and not (128+112+14 = -2) from the content of alregister?
The solution has been found by introducing
the ‘Overflow’ concept. The 8086 architecture
has included a OF (overflow flag bit) into its
FR (flag register). The OF assumes LH-state
whenever there occurs a bit propagation from
bit-6 to bit-7 during the addition of two
positive numbers (range: 0 to +127) under SA
(Signed Arithmetic). Overflow concept is not
valid while adding +ve and –ve numbers
though there is a bit propagation from bit-6 to
bit-7 (bit-14 to bit-15 for 16-bit operation) as
in the case of adding: 7Fh (+127) and FFh (1). Readers may verify it using 8086 Trainer
like MicroTalk-8086 (Bangladeshi) or
MDA8086 (Korean).
adc
add with carry
Meaning: Add two data (operand) along with
single bit carry generated in the previous
operation. The adc instruction is actually
adding three data of different dimensions.
Flags affected:
O D I T S Z A P C
Syntax:
1. Assembly Code: adc d, s
2. Pseudo Code: (d) + (s) + (CF)  CF, d
inc
Meaning: The content of a storage location is
added with 01h and the result is kept in the
same storage location.
Increment by
01h means add
01h
Flags affected:
O D I T S Z A P C
Syntax:
1. Assembly code: inc s
2. Pseudo code: (s) + 01h  s
;------------------------------------------------------As we don’t know which flags are active; we need
to start testing the flags as per above Flow Chart.
;-DSMAG-input BIN via ax-Output BCD via axL2: jo
L6
L3: jns
L6
L4: ;---- result is negative----------------------mov cx, 0000h
cub
cx, ax
call
BIN2BCD
; BCD via ax
call
SHOWMS ; show with minus sign
L5: ret
L6: ;---result is positive
call BIN2BCD
; BCD via ax
call SHOWPS ‘ show with + sign
jmp L5
;---------------------------------------------------Example-43. Adding two signed positive
numbers.
mov al, 7Fh
; +127
add al, 7Fh
; (al) = FE, OF = 1
jo
LX
; Overflow has occurred
jns LX
; (0F)=0, (SF)=0
;----- al contains negative result-------cov ah, 00h
cub ah, al
; extract absolute result
call BIN2BCD ; convert Binary to BCD
call SHOWNS ; show result with - sign
hlt
;-----------------------------------------------LX: ;- all 8-bit of al contribute to +ve result
call BIN2BCD
call SHOWPS ; show result with + sign
hlt
Example-44. Adding unsigned numbers with
Carry
mov al, 2Ah
adc
al, 45h ; result  CF, al= 0, 70h
;-----------------------------------------------------------Examle-45. Adding unsigned numbers with Carry
mov al, 0FCh
adc
al, 18h ; result  CF, al = 1, 15h
Example-46. Increment the content of an 8-bit
register
inc al ; (al) + 01h  al
;----------------------------------------------------------Example-47. Increment the content of a 6-bit
register
inc ax ; (ax) + 0001h  ax
;-----------------------------------------------------------
185
The source can be:
1. 8-bit or 16-bit registers except:
fr, ip, cs, de, es, ss.
2. One memory location
3. Two consecutive memory locations
aaa
Adjust after
ASCII addition
Meaning: ASCII codes for the BCD digits 0-9
are 30h-39h. BCD digits from remote
computers may arrive as ASCII codes. The
addition of the received ASCII codes produces
incorrect BCD result. The aaa instruction
allows extracting correct BCD result from the
incorrect BCD result. The aaa instruction
works only on the 8-bit content of al-register.
Flags affected:
O D I T S Z A P C
x
daa
Decimal Adjust
after Addition
x x
x
Syntax: aaa
Meaning: When the MPU is asked to add two
BCD numbers (say, 35 and 48); it performs a
binary addition on the given numbers and
produces incorrect BCD result (7D). To obtain
correct BCD result (83) from the incorrect
BCD result, we need to adjust the incorrect
BCD result. The adjustment is done using the
daa instruction, which works only on 8-bit
data of the al-register.
Flags affected:
Example-48. Increment the content of a memory
location
inc BYTE PTR ds:[bx]
Meaning: If the present content of location 3012h
is 34h; after the execution of the instruction, the
memory location will hold 35h.
;-----------------------------------------------------------Example-49.
Increment the content of two
consecutive memory locations. The 16-bit content
of these memory locations is considered as a
single data unit.
inc WORD PTR es:[di]
Meaning: If the present content of locations
<03013h, 03012h> is 2EFFh, then after the
execution of the instruction, the memory locations
will hold 2F00h.
Example-50. BCD digits (say 5 and 9) arrive as
35h and 39h. These numbers are added; then aaa
is applied to obtain BCD result 14 (5+9 from 6E
mov al, 35h ; ASCII of 5
add
al, 39h ; ASCII of 9, (al)=6E (incorrect)
aaa
; al = 14 (correct BCD)
O D I T S Z A P C
x
Example-51. Add the BCD numbers : BCD1 and
BCD2, and be sure that the result is a correct BCD
number
mov al, 35h
; (al) = 35, BCD1
mov ah, 48h ; (ah) = 48, BCD2
add al, ah
; (al) = 7D not 83
daa
; (al) = 91
;-----------------------------------------------------Example-52. Adding multi-byte BCD numbers:
4567 and 2853.
dax
Syntax:
1. Assembly code: daa
2. Pseudo Code : (al)  CF, al
BCD1
45
67
+BCD1
28
53
Incorrect BCD
6D
BA
+Adjustment
06
66
Correct BCD
74
The data source is al-register.
The destination is : CF, al
20
carry
L1: mov
add
daa
mov
186
al, 67h
al, 53h
bl, al
; h is placed to keep 67
; result  CF, al = 0, BA
; (CF, al) = 1, 20
;-------------------------------------------------------L2: mov al, 45h
; with ‘h’ 45 will be 2Dh
adc
al, 28h
; result  CF, al = 0, 6E
daa
; (CF, al) = 0, 74
mov bh, al
;
L3: ;-- correct BCD result in bx-register-----------The daa instruction applies one or more (but never
more than two) of the following rules to obtain
correct BCD result from the incorrect BCD result:
a. if (lower 4-bit > 9)
add 06h
b. if (AF = 1)
add 06h
c. if ( upper 4-bit > 9
add 60h
d. if (CF = 1)
add 60h
Mnemonic
sub
Subtraction
A.13 : Subtraction Instructions
Meaning
Assembly Examples
Meaning: Subtract two data (operand) without Example-53. 8-bit immediate data with an 8-bit
taking into consideration of the borrow register (unsigned numbers).
generated in the previous operation
sub al, 23h
;-----------------------------------------------------------O D I T S Z A P C
Flags affected:
Example-54. 8-bit immediate data with the content
of a
memory location of a memory segment
(unsigned numbers).
sub BYTE PTR ds:[bx], 23h
Syntax: sub d, s
;-----------------------------------------------------------1. Assembly code: sub d, s
Example-55. Between two 8-bit GPR registers
2. Pseudo code: (d) – (s)  CF, d
(unsigned numbers).
After the subtraction, the result goes to sub al, bl
‘destination, d’ and the ‘Carry Flag, CF (now ;-----------------------------------------------------------Example-56. Between an 8-bit GPR and a
called borrow)’.
memory location (unsigned numbers).
sub BYTE PTR ds:[bx], al
The destination (also the source) can be:
;-----------------------------------------------------------a. an 8-bit data (not for destination)
Example-57. 16-bit immediate data with 16-bit
b. a 16-bit data (not for destination)
GPR (unsigned numbers).
c. an 8-bit register
d. a 16-bit register
sub ax, 2345h
e. one memory location
;-----------------------------------------------------------f. two consecutive memory locations
Example-58. 16-bit immediate data with the
contents of
two consecutive memory locations
(unsigned numbers).
sub WORD PTR ds:[bx], 1234h
;-----------------------------------------------------------Example-59.
Between 16-bit GPR and the
contents of two consecutive memory locations
(unsigned numbers).
sub WORD PTR ds:[bx], cx
;-----------------------------------------------------------Example-60. Between two 16-bit GPR registers
(unsigned numbers).
sub ax, bx
187
sbb
Subtract with
borrow
Meaning: Subtract two data (operand) along
with single bit borrow generated in the previous
operation. The subb instruction is actually
subtracting three data of different dimensions.
Flags affected:
O D I T S Z A P C
Syntax:
1. Assembly Code: subb d, s
2. Pseudo Code: (d) - (s) - (CF)  CF, d
dec
Decrement
Meaning: The content of a storage location is
deducted by 01h and the result is kept in the
same storage location.
mov ax, 5678h
sub
ax, 3456h
mov bl, 34h
sbb
bl, 12h ; result in (bl, ax)
Example-64.
a. Decrementing an 8-bit register
dec al
O D I T S Z A P C
b. Decrementing a 16-bit register
dec cx
Flags affected:
Syntax:
1. Assembly code: dec s
2. Pseudo code: (s) - 01h  s
neg
Negate
Example-61. Subtraction of signed numbers ( -25
and 8)
mov al, -25 ; al-register holds E7 (2’sC)
sub
al, 08h ; (al) = DF
;-determine sign and magnitude by---Jo
L12
; +ve number
;---negative number, (ai) = -ve
sub
ah, 00h
sub
ah, al
; (ah) = absolute value
call
BIN2BCD
call
SHOWMS ; show with – (minus) sign
hlt
L12: ;---- =ve sign and magnitude
Example-62.
DATA1 = 2Ah
DATA2 = 35h
(CF)
=1
mov al, 2Ah
sbb
al, 45h
; assume (CF) = 1 ; (al) = E4
;-- determine sign and magnitude by the Flow
Chart of Example-41.
;-----------------------------------------------------Example-63. Multibyte subtraction
DATA1 = 345678h
DATA2 = 123456h
c. Decrementing a memory location
dec BYTE PTR ds:[bx]
The source can be:
1. 8-bit or 16-bit registers except:
fr, ip, cs, de, es, ss.
2. One memory location
3. Two consecutive memory locations
Meaning: In Intel architecture, a negative
number (say -123) is stored in a register or
memory location in 2’s complement form
(2’sC). The content of a storage location is
converted into 2’sC form and the result is
saved in the same storage location. The neg
instruction subtracts the source operand from
00h, which is equivalent to ‘inverting the bits of
the source operand and then adding 1’. If the
source operand is already a negative number
(with MSBit = LH); its 2’s complement remains
188
d. Decrementing the content of two consecutive
memory locations.
dec WORD PTR ds:[bx]
Example-65. 2’s complement of an 8-bit register
mov
al, 70h
neg
al
; (al) = 85h = 2’sC of 70h
;----------------------------------------------------Example-66. 2’s Complement of an 8-bit negative
number.
mov
al, 82h
neg
al
; (al) = 2’sC of 82h = 7Eh
;------------------------------------------------------
the same. However, if an unsigned number (say,
70h) is submitted to the neg instruction, the
CPU just produces the correso\ponding 2’sC
form of (70h = 0111 0000  1000 1111 +1
=1001 0000 = 90h).
Flags affected:
O D I T S Z A P C
Syntax:
1. Assembly code: neg s
2. Pseudo code: 00h - (s)  s
cmp
Compare
The source (destination) cane be:
1. 8-bit or 16-bit register
2. One memory location
3. Two consecutive memory locations
Meaning: The destination data (d) is subtracted
from the source data (S) but none of the data is
destroyed. The comparison determines if: (i) d
is equal to s, or (ii) d is greater than s, or (iii) d
is less than s.
When:
(i) d is equal s, the ZF assumes LH,
(ii) d is greater than s, the CF assumes LL, and
(iii) d is less than s, the CF assumes LH.
So, these are flag bits that help the CPU to take
decision about relationship of the given data.
The Flow Chart for the cmp instruction is given
to the right column.
O D I T S Z A P C
Flags affected:
Syntax:
1. Assembly code: cmp d, s
2. Pseudo Code: d  s  TR
The source (destination operand) can be:
1. 8-bit immediate data (not valid for d)
2. 16-bit immediate data (not valid for d)
3. 8-bit register
4. 16-bit register
5. one memory locations
6. Two consecutive memory locations
189
Example-67. 2’s complement of a 16-bit register
nov
ax, 3456h
neg
ax
; (ax) = CBAA
;----------------------------------------------------Example-68. 2’s complement of a memory
location.
(03010) = 34h
neg
BYTE PTR ds:[bx+10h]
;-----------------------------------------------------Example-69. 2’s complement of two consecutive
memory locations.
(03011, 03010) = 4567h
neg
WORD PTR ds:[bx+10h]
;------------------------------------------------------
1200ab
L1:
s~d
L2:
ZF = 1 ?
Y
L3:
s=d
N
L4:
s != d
CF = 1?
N L6:
s>d
Y
L5:
s<d
L1: cmp
d, s
L2: jnz
L4
; s != d
L3: ;- (s ) = (d)----------hlt
L4: jnc
L6
L5: ;--- (s) < (d)--------hlt
L6: ;----- (s) > (d)------Hlt
;------------------------------------------------------Example-70. . 8-bit immediate data with an 8-bit
register.
cmp
al, 23h
;------------------------------------------------------Example-71. 8-bit immediate data and the content
of a memory location
cmp
BYTE PTR ds:[bx+12h], 45h
;------------------------------------------------------Example-72. 16-bit immediate data and 16-bit
GPR.
cmp
ax, 3456h
;-----------------------------------------------------Example-73. 16-bit immediate data and two
consecutive memory locations.
cmp WORD PTR ds:[bx+10h], 4567h
;------------------------------------------------------
aas
ASCII Adjust
after
Subtraction
Meaning: ASCII codes for the BCD digits 0-9
are 30h-39h. BCD digits from remote
computers may arrive as ASCII codes. The
subtraction of the received ASCII codes
produces incorrect BCD result. The aas
instruction allows extracting correct BCD result
from the incorrect BCD result. The aas
instruction works only on the 8-bit content of
al-register.
O D I T S Z A P C
Flags affected:
x
x x
x
Syntax: aaa
das
Decimal
Adjust after
Subtraction
Same as daa instruction; but now for
subtraction operation of two BCD numbers.
190
Example-74. 8-bit GPR and 8-bit GPR
cmp al, cl
;-----------------------------------------------------Example-75. 8-bit GPR with a memory location.
cmp BYTE PTR ds:[bx+12h], al
cmp al, BYTE PTR ds:[bx+12h]
;------------------------------------------------------Example-76. 16-bit GPR and 16-bit GPR.
cmp
ax, cx
;-----------------------------------------------------Example-77. 16-bit GPR and two consecutive
memory locations.
cmp WORD PTR ds:[bx], 2345h
;-----------------------------------------------------Example-78. 16-bit GPR to 16-bit GPR.
cmp WORD PTR ds:[bx], 1234h
;-----------------------------------------------------Example-79. BCD digits (say 5 and 7) arrive as
35h and 37h. These numbers are subtracted; then
aas is applied to obtain BCD result -2 (5-7) from
FE. The minus ( - ) sign is appended by
interpreting he flag bts.
mov al, 35h ; ASCII of 5 BCD1
mov bl, 37h ; ASCII of 7 BCD2
sub
al, bl ; al = FEh incorrect
aas
; al = 02 (-) BCD, (CF) = 1
jnc
L12
; +ve BCD
;----place – sign-------------call
SHOWMS ; show with – sign.
hlt
L12: ;---- +ve number-------Example-80. BCD1=40, BCD2=34, BCD1BCD2=06,
mov al, 40h ; 40 BCD1
mov ah, 34h ; 34 BCD2
sub
al, ah ; al= 0C incorrect!
das
; al = 06 correct!
;-------------------------------------------Example-81. Multibyte BCD subtractions.
BCD1=3456h, BCD2=1234h.
mov al, 56h
sub
al, 34h
das
mov cl, al
;------------mov
al, 34h
sub
al, 12h
das
mov
ch, al
;---- BCD result = (ch, cl) = 2222-----
Mnemonic
mul
Multiplication of
unsigned Binary
numbers
A.14 : Multiplication Instructions
Meaning
Examples
Meaning: Two unsigned binary (hex) Example-82. Two 8-bit data. Both are in registers.
numbers will be multiplied. Unsigned refers mov al, 23h
to the fact: all bits of the number carry mov cl, 56h
positive positional magnitudes.
mul
cl
; 16-bit result in ax-register
O D I T S Z A P C
;----------------------------------------------------------Flags affected:
Example-83. Two 8-bit data. One in a register and
x x x x x x x
other in a memory location.
mov al, 34h
Syntax:
mul
BYTE PTR ds:[bx] ; result in ax
Assembly code: mul s
;----------------------------------------------------------;----------------------------------------------------Example-84. Two 16-bit registers. Both are in
For 8-bit by 8-bit multiplication:
registers
Data Source:
mov ax, 1234h
1. One data must be in al-register.
mov cx, 6789h
2. 2nd data may reside in:
mul cx
; 32-bit result in < dx-ax>
An 8-bit GPR
;-----------------------------------------------------------Or
Example-85. Two 16-bit data. One in a register
A memory location
and the other one is in two consecutive memory
locations.
Destination:
The 16-bit result always goes into ax- mov ax, 4567h
register.
mul WORD PTR ds:[bx] ; result in <dx, ax>
;---------------------------------------------------;-----------------------------------------------------For 16-bit by 16-bit multiplication:
Data Source:
1. One data must be in ax-register.
2. 2nd data may reside in:
A 16-bit GPR
Or
Two consecutive memory locations
Destination:
The 32--bit result always goes into <dx, ax>
register pair.
imul
Integer Multiply
Meaning: The imul instruction performs
‘signed multiplication’, which means that it
can multiply both ‘positive and positive’,
‘positive and negative’, and ‘negative and
negative’ numbers under 2’s complement
arithmetic rules (TCA).
-----------------------------------------------------Signed integers cover all numbers having
positive ( + ) and negative ( - ) signs. For
example:
-3, - 5, +12, 34 are all integers or signed
numbers.
-----------------------------------------------------Unsigned integers cover numbers with only
positive ( + ) signs. For example:
+4, 78 are all unsigned numbers or unsigned
integers.
------------------------------------------------------
191
In 8086, we have mul instruction, which is
dedicated to multiply only the unsigned
integers/numbers. The result is always
unsigned integer/number.
-----------------------------------------------------imul instruction works on the following
conditions (applicable for both 8-bit and 16
bit data):
1. Integers that are to be multiplied must be
represented in 2’s complement form. In
2’s complement form, the MS-bit bears
negative positional value and all other
bits carry positive positional values. For
example:
mov
al, -123 loads 85h (1000 0101 = 1
x 27 + 0+0+0+0 + 1x22 + 0 + 1x20 =
123) into al-register, where 85h is the 2’s
complement form of the decimal number 123.
2. For 8-bit positive numbers, the lower 7
Bits bear positive positional values and
the MS-bit indicates sign of the number
and is always 0.
3. In the multiplication of 8-bit signed
numbers, if the magnitude of the result
(product) does not require all of the bits of
the destination register (ax = ah, al), the
unused upper 8-bits will be filled with
copies of the sign bit. For example:
imul 12, -10 ; <ah, al> = FF88h
= 1111 111 1 1000 1000
1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0
Sign Bit
1x
Copies of Sign Bit
If the ah-register contains only the copies
of the sign bit (all 0s or all 1’s; no part of the
of the 16-bit result), the CF and OF flags of
8086 will both be 0’s; else 1’s.
4. In the multiplication of 16-bit signed
numbers, all the features of Step-3
mentioned above would be applied. In
the present case, the registers <dx, ax> is
involved to hold the 32-bit signed result.
Flags affected:
O D I T S Z A P C
x x x x x x x
192
Example-86. Determination of sign and magnitude
of result after imul instruction.
L1:
1x
Legend:
P = Product
2'sC = 2's Complement Form
Upart = Upper Part of Product
7/15 = Lower 7-bit or 15-bit
Perform: imul
L2:
N
(CF)=0
?
L3:
L7:
Y
(ah) = Sign Bits
(ah) = Upart of P
L4:
L8:
(ah) = FFh
?
L5:
N L6A
L6B N
Y
P=(al) = 2'sC
ret
S-bit = 1
?
L9:
Y
P=(al) = +ve (7/15)
P = (ax)=2'sC
ret
ret
ASM Coding for the above Flow Chart:
;--------------------------------------------------------------------IMUL8SM: ; IMUL for 8-bit signed number
;L1: mov al, data1 ; data1 = -128 to +127
;
mov cl, data2 ; data2 = -128 to +127
;
imul cl
; result in ax-register
L2: jnc
L7
L3: ;-ah-register contains copies of sign bit of al-register
L4: cmp ah, 0FFH
jnz
L6A
L5: ;--al-register contains negative result in 2’sC form--mov ah, 00h
sub ah, al ; ah-register holds the absolute value
mov cl, 01h ; flag to say 8-bit –ve result in ah
L5A: ret
L6A: ;-- result is positive and is within lower 7-bit
mov ch, 01h ; flag to say 8-bit +ve result in al
jmp L5A
L7: ;-ah-register contains upper part of result-----L8: jns
L6B
L9: ;-ax-register holds negative result in 2’sC fprm--mov dx, 0000h
sub dx, ax ; ax-register holds absolute value
mov dl, 01h ; flag to say 16-bit –ve result in ax
jmp L5A
L6B: ;--result is positive and is within lower 15-bit of ax
mov dh, 01h ;flag to say 16-bit +ve result in ax
jmp L5A
;---------------------------------------------------------------------
Example-87. Two 8-bit positive data. Both are in
registers.
mov
al, 10
; decimal 10 = 0Ah = 0000 1010
mov
cl, 12
; decimal 12 = 0Ch = 0000 1100
imul
cl
; (ax) = 0078h = 0000 0000 0111 1000
;--exract 120 from 0078h. How?-------------------------call
IMUL8SM
;---test flag to determine sign and magnitude-----
Syntax: imul s
For 8-bit by 8-bit multiplication:
Data Source:
1. One data must be in al-register.
2. 2nd data may reside in:
An 8-bit GPR
Or
A memory location
Destination:
The 8/16-bit result always goes into al/axregister and its content is in 2’s complement
form for negative result. The Flow Chart of
right column determines the sign and
magnitude of the result.
;---------------------------------------------------For 16-bit by 16-bit multiplication:
Data Source:
1. One data must be in ax-register.
2. 2nd data may reside in:
A 16-bit GPR
Or
Two consecutive memory locations
Destination:
The 16/32--bit result always goes into
ax/<dx, ax> register pair and their contents
are in 2’s complement form for negative
result. The Flow Chart of right column after
modification for 16/32 bits; determines the
sign and magnitude of the result.
;-----------------------------------------------------
193
cmp
cl, 01h
Jnz
NXT1
;----8 bit negative result in ah------call
EBIN2BCD ; 8-bit Binary to BCD
call
SHOWMS ; show with – (minus) sign
hlt
;----------------------------------------NXT1:
cmp ch, 01h
jnz
NXT2
;-- 8-bit positive value in al-register-------call
EBIN2BCD
call
SHOWPS ; show with + (plus) sign
hlt
;-----------------------------------------------NXT2:
cmp dl, 01h
jnz
NXT3
;--16 bit negative result in ax-register -----------call SBIN2BCD ; 16-bit Binary to BCD conversion
call SHOWMS ; show with – (minus) sign
hlt
;---------------------------------------------------------NXT3:
cmp dh, 01h
jnz
NXT4
;-- 16 bit positive result in ax-register----------call
SBIN2BCD
call
SHOWPS
; show with plus sign
hlt
;----------------------------------------------------------NXT4: hlt
;---------------------------------------------------------------------
Example-88. -31678 x 30123 = -954236394
Mov
ax, -34678
; 6442h
Mov
cx, 30123
; 75ABh
Imul
cx
; (dx:ax) = C71F 8216h , (CF) = 1
Jnc
L12
;---- result in (dx:ax)----------Mov
bx, dx
Shl
bx, 0001h
Jnc
L13
;----- (dx:ax) = -ve number------------------mov
cx, 0000h
sub
cx, ax
mov
ax, cx
;-------------------Mov
cx, 0000h
Sbb
cx, dx
Mov
dx, ax
; |dx:ax| = result in Binary
;------------------Call
BIN2BCD
Call
SHOWMS ; show result with – sign.
Hlt
L12: ;------ (dx) = sign of the number, (ax) = magnitude--Cmp
dx, 0FFFFh
Jz
L14
;------ (ax) = +ve result
Mov
dx, 0000h
Call
BIN2BCD
Call
SHOWPS
; show with + sign---Hlt
L13: ;--- (dx:ax) = + ve result-----L14: ;--- (ax) = - result---------------
aam
ASCII adjust
after
Multiplication
Meaning: Multiplication of two unpacked
BCD numbers produces equivalent 8-bit
binary number in the al-register. The aam
instruction converts the above binary into a
packed BCD number, and then the BCD
number is transformed into two ASCII codes
for the digits of the said BCD number. In
brief, the aam instruction converts the
Binary content of al-register into packed
BCD and then transforms the BCD numbers
into two ASCII-coded BCD numbers. The
aam instruction works only on al-register.
Flags affected:
Example-89. After multiplication of 07h and 02h,
the al-register contains 0Eh. The aam instruction
makes it 14 and then puts 31h (0011 0001) and 34h
(0011 0100) into ah- and al-register respectively.
mov
mov
mul
aam
al, 07h
bl, 02h
bl
; unpacked BCD for 7
; unpacked BCD for 2
; ax = 000Eh (incorrect BCD)
; (al)  14  31h, 34h  <ah, al>
O D I T S Z A P C
x
x
x
Syntax: aam
The source and destinations are the same
and it is the al-register
Mnemonic
div
unsigned
Division
A.15 : Division Instructions
Meaning
Assembly Examples
Meaning: An unsigned dividend (16-bit or Example-90. 16-bit / 8-bit Signed division.
; to hold upper pat of Quotient
32-bit) will be divided by an unsigned divisor mov ch, 00h
ax, 0FFFFh ; maximum range
(8-bit or 16-bit). Two important features of mov
mov
cl, 0FFH
; maximum range
div instruction are:
1. If an attempt is made to make a division
by 0; the CPU will automatically be
interrupted for int 00h.
2. When a 16-bit (32-bit) by 8-bit (16-bit)
division takes place, and the result
(quotient) does no fit ( > FF or >FFFF) in
the destination register (al or ax), an
interrupt of int 00h will be generated only
for once at the first partial division.
div
cl ; expected Q = (al) = 101h, R=(ah) = 00h
;---- Q in cx-register and R in ah-register
ISR00 : ; we must have this ISR00 as we don’t know the
; sizes of dividend and divisor.
cmp
cl, 00h
jz
L12
mov
ch, 01h
; int 00h happended; Q > FF
iret
L12: ; correct divisor
iret
;--------------------------------------------------------------------
Example-91. 24-bit / 8-bit signed division.
O D I T S Z A P C
Flags affected:
x x x x x x x x x
Syntax:
1. Assembly code: div source
2. Pseudo code:
a. data16 / (al)  <ah, al>
(ah)=remainder, (al) = Quotient (result)
b. data32 / (ax)  <dx, ax>
(dx)=remainder, (ax)= Quotient (result)
;----------------------------------------------For 16-bit / 8-bit:
1. The dividend (numerator) must be in axregister.
2. The divisor (denominator) may reside in
an 8-bit register or in a memory location
194
;-- expected result: FFFFFFh – 10101
; assume dividen in < cl bh bl >; divisor in ch
mov dh, 00h
mov ah, cl
mov al, bh
; (ax) = (cl bh)
div
ch
: Q0 = first partial (al), R0 = (ah)
;-- Q0 = (dh, al), R0 = (ah)------------------mov dl, al
; Q0 = (dx) = 0101
mov di, dx
; Q0 = (di)
;------------------------mov al, bl
; new dividend in ax
div
ch
; Q1 = (al), R1 = (ah)
;---- Final Q = (dh dl cl) and R = (ah) ------------------mov cl, al
hlt
;--------------------------------------------------------------------ISR00 : ; we must have this ISR00 as we don’t know the
; sizes of dividend and divisor.
mov
dh, 01h
; int 00h happened; because Q > FF
iret
;---------------------------------------------------------------------
3. The result (quotient) enters into al-register
and the remainder goes into ah-register.
;----------------------------------------------------For 32-bit / 16-bit:
1. The dividend (numerator) must be in < dx
ax > register pair.
2. The divisor (denominator) may reside in
a 16-bit register or in two consecutive
memory locations.
idiv
Integer (signed
numbers)
Division
3. The result (quotient, Q) enters into axregister and the remainder (R) goes into dxregister.
;-----------------------------------------------Meaning:
A 16-bit signed dividend (range: -32768 to
+32767 = 8000h – 7FFFh) can be divided by
an 8-bit signed divisor (range: -128 to +127
= 80h – 7Fh) by the idiv instruction.
OR
Example-92.
L1:
1x
Perform: idiv
L2:
R = +ve
A 32-bit signed dividend (range: 2147484648 to +214748647 = 80000000h –
7FFFFFFFh) can be divided by a 16-bit
signed divisor (range: -32768 to +32767 =
8000h – 7FFFh) by the idiv instruction.
L3:
N
L8:
Y
dividend = +ve
dividend = -ve
L4:
L9:
N L7:
In idiv operation for 16-bit / 8-bit:
1. The dividend (N) must be in ax-register
divisor = +ve
L5:
2. The divisor (D) must be in an 8-bit
register or in a memory location.
4. The 8-bit quotient (Q) enters into alregister in 2’sC form.
5. The sign of the remainder (R) is same as
the sign of the dividend.
6. An interrupt of type int00h is generated if:
a. an attempt is made to divide the N by 0
b. Q becomes greater than +127 (7Fh). It
is because +128 (80h) can not be
accommodated within lower 7-bit of
al-register. The problem has to be
solved using 32-bit/16-bit idiv. The
dividend remains unchanged.
c. Q becomes less than -128 (80h). It is
because -129 can not be accommodated
195
divisor = +ve
Y
Q = +ve, R= +ve
L6:
3. The 8-bit remainder (R) enters into ahregister in 2’sC (2’s complement) form.
L11: Y
ret
L10:
N
Q =-ve, R= +ve
Q =+ve, R= -ve
ret
ret
Coding of above Flow Chart with Ex-1: 939/-45
IMULS: ; S for 16-Bit
L1: mov ax, dividend16 ; 16-bit = 939 = 03ABh
mov ch, divisor8
; 8-bit = -45 = D3h (2’sC)
idiv
ch
; P = < Q, R > = < al, ah >
; = <ECh, 27h> = -20, +39
;-- in this example int00h interrupt will not be generated-L2: rcl
ah, 01h ; checking sign ob R
jc
L8
L3: ;--N is positive ------L4: rcl
ch, 01h ; checking sign bit o D
jc
L7
L5: ;-- Q is +ve, R is +ve --------------L6: hlt
L7: ;--Q is – ve, R is +ve----jmp L6
L8: ;--dividend (N) is negative----L9: rcl
ch, 01h ; checking D’s sign
jnc
L11
L10: ;-- Q is +ve and R is –ve
jmp L6
L11: ;-- Q is –ve and R is +ve------
within 8-bit of al-register. The problem has
to be solved using 32-bit/16-bit idiv. The
dividend remains unchanged.
7. All flag bits are undefined.
8. If D can not divide the N, the Q will be
truncated, not rounded.
9. The Flow Chart of the right column and
The associated ASM codes correctly
Determine the sign and magnitudes of the
result (R and Q).
Flags affected:
O D I T S Z A P C
x x x x x x x x x
Syntax:
1. Assembly code: idiv source
2. Pseudo code:
a. data16 / 8-bit  <al, ah> = <Q, R>
(al)=Quotient (result), (ah)=Remainder
b. data32 / 16-bit  <ax, dx> = <Q, R>
(ax)=Quotient (result), (dx)=Remainder
mov cl, 00h
sub
cl, al
; Q = (cl) = | 00 – EC | = 14h
call
BIN2BCD8 ; Q = 14h  20
call
SHOWMS ; show with – (minus) sign
jmp
L6
;--------------------------------------------------------------ISR00: ; interrupt for Type 0 (int 00h)
IL1: if (D = 00) ; D for divisor = denominator
Goto ISLX and correct it
IL2: ; -- Q > 7Fh = +127) or < 80h (-129)
Show message to Solve problem by 32-bit /16-bit
idiv instruction
Abort process, artificially reset interrupt logic and
Goto prompt.
ISLX: ;--- show error message of D=00 -----------Abort process, artificially reset interrupt logic and
Goto prompt.
;---------------------------------------------------------------------
Examples-93:
1. -17654 / 123 = BB0Ah / 7Bh
Let us see if this example could be solved by 16-bit /
8-bit idiv instruction or not. Yes! It can be solved
provided that the Q does not appear to be greater than
+127 or less than -128 (why does literature say -127?).
Can we find the values of Q and R by analysis rather
than running the program? Yes! We can.
1.
−17654
123
= (𝑄, 𝑅) = −143, −65 ; 𝑄 < −128,
2. Problem must be solved using 32-bit / 16-bit idiv so that
the Q (-143) fits in the 16-bit capacity of ax-register in
2’sC form.
3.
aad
Adjust masked
ASCII into
unpacked BCD,
convert to
binary before
Division
Meaning: ASCII coded BCD digits are first
represented as unpacked two BCD digits:
ASCII codes for 6 and 7 are 36h, 37h. These
are transformed into 06 and 07 called masked
ASCIIs. 0607 is kept in a 16-bit register. The
execution of aad instruction convents the
unpacked BCD number into packed BCD
(67), and then convents into its equivalent
binary of 43h. The div instruction, which
follows the aad instruction, produces normal
unsigned Q (quotient) in al-register and
unsigned R (remainder) in ah-register. If the
div instruction that follows the aad
instruction attempts to make a division by 0
or the the Q > 9, an interrupt of Type 0 (int
00h) is automatically generated.
O D I T S Z A P C
Flags affected:
x
x
x
196
−17654
123
=
𝐹𝐹𝐹𝐹𝐵𝐵0𝐴ℎ
007𝐵ℎ
=
𝐷𝑊𝑂𝑅𝐷
𝑊𝑂𝑅𝐷
= (𝑄, 𝑅) = (𝐹𝐹71, 𝐹𝐹𝐵𝐹) = (𝑎𝑥, 𝑑𝑥)
Example-94. ASCII codes of 8 and 9 are: 38h and
39h.
mov ah, 38h
and
ah, 0Fh
mov al, 39h
and
al, 0Fh
aad
;-----------------mov ch, 09h
div
ch
; (ah) = 38h
; (ax) = 0809
; (ax) = 59h = Binary of BCD_89
; Q = (al) = 06 ; R = (ah) = 05
Syntax:
Assembly code: aad
cbw
Convert signed
byte to signed
Word
The source and destination are the same 16bit register.
Meaning: This instruction converts a signed
byte in al-register (8 bit: -128 to +127 = 80h
to 7Fh) into signed word in ax-register (16
bit: 1111 1111 1000 0000 to 0000 0000 0111
1111 = FF80h to 007Fh). This is done by
copying the sign bit of al-register into all
positions of the ah-register. The cbw
instruction is engaged before dividing a
signed 8-bit (byte) dividend by a signed 8-bit
(byte) divisor using idiv instruction.
Example-95.
-65 / -8 = (Q, R)
= 8, -1=(al, ah)
mov
cbw
mov
idiv
al, -65
cl, -8
cl
; (al) = 9Bh =1001 1011 (2’sC)
; (ax) = 1111 1111 1001 1011
; (cl) = F8h
; Q = (al) = 08h, R = (ah)= -1=FFh
O D I T S Z A P C
Flags affected:
Syntax:
Assembly code: cbw
cwd
Convert signed
Word to Double
word
The source is the al-register and the
destination is the ax-register.
Meaning: This instruction converts a signed
word in ax-register (16 bit: -32768 to +32767
= 8000h to 7FFFh) into signed double word
in dx:ax-register (32 bit: 1111 1111 1111
1111 1000 0000 0000 0000 to 0000 0000
0000 0000 0111 1111 1111 1111 =
FFFF8000h to 00007FFFh). This is done by
copying the sign bit of ax-register into all
positions of the dx-register. The cwd
instruction is engaged before dividing a
signed 16-bit (word) dividend by a signed
16-bit (word) divisor using idiv instruction.
Flags affected:
O D I T S Z A P C
Syntax:
Assembly code: cwd
197
Example-96.
-3897 / 657 = Q, R = -5, -612
= FFFB, FD9C (ax, dx)
mov
cwd
mov
idiv
; (ax) = F0C7h (2’sC form)
; (dx:ax) = FFFF:F0C7
cx, 657
; (cx) = 0291h
cx ; Q = (ax) = FFFB, R=(dx)=FD9Ch
ax, -3897
Mnemonic
shl
Shift Left
=
sal
Shift Arithmetic
Left
A16. : Shift
Meaning
Meaning: All bits will be shifted to the left
by 1-bit position. MSBit will enter into CFposition and 0 (zero) will enter at LSBit. If
shifting is desired by more than 1-bit
position, the ‘number of shift’ must be passed
via cl-register.
Because 0 enters into LSBit, the execution of
shl doubles the ‘source data’. Thus, shl could
be used in place of mul instruction as a means
of ‘faster multiplication’ process.
Examples
Examples-97. Shifting left 8-bit GPR by 1-bit
mov al, 34h ; (al) = 0011 0100
shl al, 01h ; (al) 0110 1000
;-----------------------------------------------------------Example-98. shifting left 8-bit register by 3 bit
position.
mov al, 34h
mov cl, 03h
shl al, cl
; number of shift
; (al) = 1010 0000
CF ← MSB       LSB  0
Flags affected:
Syntax:
Assembly code: shl s
shr
Shift Right
=
sar
Shift Arithmetic
Right
The source and destination are:
1. an 8-bit register,
2. a 16-bit register,
3. one memory location and
4. two consecutive memory locations
Meaning: Shift Right all bit by 1-bit
position. 0 will enter at B7-position, B6 will
shift to B5-position, …, B0 will shift to Carry
Flag. Execution of shr instruction will
automatically store 0s into the higher bits.
0  MSB      LSB  CF
Syntax:
a. shr d, 01h ; shift right by 1-bit position
b. shr d, cl ; shift right by counts in cl
When shifting is more than 1-bit position;
the shift count must be in cl-register.
The destination can be:
a. an 8-bit or 16-bit register
b. one memory location
c. two consecutive memory locations
Example-99. Shifting right 16-bit data by 1position.
mov ax, 0FFFFh
shr
ax, 01h ; ax = 7FFF
;----------------------------------------------------------Example-100. Shifting memory content bt 1position.
shr
BYTE PTR [bx], 01h
;-----------------------------------------------------------Example-101. Shifting 16-bit content of two
consecutive memory locations by 1-bit position.
shr
WORD PTR [bx], 01h
;----------------------------------------------------------Example-102. Shifting right the 8-bit content of a
register by 3-bit positions.
Mov al, 45h
mov cl, 03h ; ro shift bt 3-bit positions
shr
al, cl
; (al) = 000 00011 = 03h
;---------------------------------------------------------Example-103. What is the meaning of the
following instruction?
shr
WORD PTR es:[ bx + si + 03h], 01h
The 16-bit content of the emory location pointed
by es:[bx + si + 03h] will be shifted right by 1-bit
position.
198
Mnemonic
rol
Rotate Left
A.17 : Rotate
Meaning
Meaning: Rotate left all bits by 1-bit
position. B0 (LSB) will shift at B1-position,
…, B6 will shift at B7-position, B7 (MSB)
will shift at CF and LSB positions.
CF  MSB  LSB
Syntax:
a. rol d, 01h ; rotate left by 1-bit position
b. rol d, cl
; rotate left by counts in cl
When rotation is more than 1-bit position;
the rotate count must be in cl-register.
The destination can be:
a. an 8-bit or 16-bit register
b. one memory location
c. two consecutive memory locations
ror
Rotate Right
Meaning: Rotate right all individual bits by
1-bit position. B0 (LSB) will shift at B7position, …, B6 will shift at B5-position, B0
(LSB) will also shift at CF positions.
CF
MSB      
LSB
Syntax:
a. rol d, 01h ; rotate left by 1-bit position
b. rol d, cl
; rotate left by counts in cl
When, more than one rotation is required, the
rotate count must be loaded into cl-register.
rcl
Rotate Left
through Carry
The destination can be:
a. an 8-bit or 16-bit register
b. one memory location
c. two consecutive memory locations
Meaning: All individual bits will rotate to the
left through CF by 1-bit (or more) position.
MSB (B7) will got to position CF, B6, … ,
LSB will go to position B1, and CF will go to
LSB position.
199
Examples
Example-104. Rotating left 8-bit data by 1-bit
position.
mov ax, 0F23Fh ; ax = 1111 0010 0011 1111
rol
a,l 01h ; CF=0, LSB = 0, (al) = 7Eh
;-----------------------------------------------------------Example-105. Rotating left 16-bit data by 1-bit
position.
mov ax, 0F23Fh
rol
ax, 01h ; CF=1, LSB=1, (ax) = E47Fh
;-----------------------------------------------------------Example-106. Rotating left 8-bit data of a memory
location by 1-bit position.
rol
BYTE PTR [bx], 01h
;-----------------------------------------------------------Example-107. Rotating left 16-bit contents of two
consecutive memory locations by 1-bit position.
rol
WORD PTR [bx], 01h
;-----------------------------------------------------------Example-108. Rotating left 8-bit content of a
register by 3-bit positions.
mov cl, 03h ; to rotate by 3-bit positions
rol
al, cl
; CF=?, MSB=?, LSB=?, (al)=?
;-----------------------------------------------------------Example-109. Rotating left 16-bit content of two
consecutive memory locations by 1-bit position.
rol
WORD PTR es:[ bx + si + 03h], 01h
Memory location pointed by es:[bx + si + 03h]
will be rotated to the left by 1-bit position.
CF  MSB       LSB
190
Syntax:
a. rcl d, 01h
b. rcl d, cl ; rotation count in cl register
If rotation is to be made by more than 1-bit
position; the rotation count must be given via
cl register
rcr
Rotate Right
through Carry
The destination can be:
a. an 8-bit register
b. a 16-bit register
c. one memory location
d. two consecutive memory locations
Meaning: All the bits will rotate to the right
through CF by 1-bit (or more) position. MSB
will got to position B6, … , LSB will go to
position CF, and CF will go to MSB position.
CF 
MSB       LSB
Syntax:
a. rcr d, 01h
b. rcr d, cl ; rotation count in cl register
If rotation is to be made by more than 1-bit
position; the rotation count must be given via
cl register
The destination can be:
a. an 8-bit register
b. a 16-bit register
c. one memory location
d. two consecutive memory locations
A.18 : Logical
Mnemonic
Meaning
not
(Not = Invert)
Every bit of 8-bit (16-bit) register or memory
locations would be inverted. Bit with LLvalue is converted to LH and vice-versa.
Logical Not
Bit by bit
Examples
Example-110. Inverting all individual bits of an 8bit register.
mov al, 34h ; (al) = 0011 0100
not
al
; (al) = 1100 1011
;-----------------------------------------------------------Example-111. Inverting all individual bits of a 16bit register.
Mov ax, 3456h ; (ax) = 0011 0100 0101 0110
not
ax
; (iax) = 1100 1011 1010 1001
;----------------------------------------------------------Example-112. Inverting all individual bits of a
memory location.
not
BYTE PTR [bx]
200
and
Logical AND
Bit by bit
or
xor
test
Test a
particular bit
for LH or LL
condition
without
affecting other
bits
(Bit-wise AND)
Two 8-bit (16-bit) data are bit-by-bit ANDed.
Data source and destination may be
immediate number, register or memory
locations.
(Bit-wise OR)
Two 8-bit (16-bit) data items of 8-bit (16-bit)
registers or memory locations are bit-wise
inclusive ORed.
(Bit-wise XOR)
Two 8-bit (16-bit) data items of 8-bit (16-bit)
registers or memory locations are bit-wise
exclusive ORed (XOR).
Meaning: A particular bit (let us call it
destination bit) of a storage location can be
tested for LH or LL state. To test the state,
the bit has to be compared with LH (1). The
test is done by ANDing the corresponding
bits of two operands (destination and source).
The test instruction does not produce any
result, and not change the operands. It only
affects the flags so that the programmer can
take decision.
The storage location can be:
a. an 8-bit or 16-bit register
b. one memory location
c. two consecutive memory locations
201
Example-113. Inverting all individual bits of two
consecutive memory locations.
not
WORD PTR [bx]
Example-114. ANDing all individual bits of an 8bit immediate data.
mov al, 10101010B
and
al, 01010101B ; al=00h
;-----------------------------------------------------------Example-115. ANDing two 8-bit registers
and
al, ah
;-----------------------------------------------------------Example-116. ANDing 16-bit immediate data.
and
ax, 1234h
;----------------------------------------------------------Example-117. ANDing two 16-bit registers
and
ax, bx
;----------------------------------------------------------Example-118. ANDing 8-bit content of a memory
location.
and
al, BYTE PTR [bx]
;----------------------------------------------------------Example-119. ANDing individual bits of the 16bit content of two consecutive memory locations.
and
ax, WORD PTR [bx]
Example-120.
or
al, 23h
;-------------------------------or
al, bl
;----------------------------------or
ax, 1234h
;--------------------------------or
ax, bx
;----------------------------------or
al, BYTE PTR [bx]
;-------------------------------------or
ax, WORD PTR [bx]
Similar to above
Example-121. Testing al0-bit of
(destination operand) for LH-state.
al-register
mov al, 35h ; (al) = 0011 0101
test al, 01h ; 1 AND 0 = 0; (ZF) = 1
jnz
L1
; al0 = LH ; jump if (ZF) !=1
;----- al0 is LL-----------L1:
;---------------------------------------Example-122. Testing ax3-bit for LL.
mov ax, 0FE0Fh ;(ax) = 1111 1110 0000 0111
test ax, 0008h ; (ax) = 0000 0000 0000 1000
jz
L12
; ax3 – bit LL ; jump if (ZF) = 1
;------------L12:
The test instruction performs a logic AND
between the ‘destination bit’ and the ‘source
bit’. If the ANDing of the bits produces nonzero result (1 AND 1=1), the ZF assumes
LL-state; else ZF assumes LH-state. The
ANDing must be done by putting LH in the
‘nth source bit’, which corresponds to the
same ‘nth bit of the destination operand’.
O D I T S Z A P C
Flags affected
0
x
Example-123. Testing Bit-0 for LL of a memory
location.
test BYTE PTR [bx], 01h
jz
L13
; Bit- is LL, (ZF) = 1
;--------------------------------------------------------------------
Example-124. Testing a particular bit of the 16-bit
content of two consecutive memory locations.
test WORD PTR [bx], 0001h
0
PF has meaning only for the lower eight bits
of the destination operand.
Syntax: test d, s
Mnemonic
movsb
Move a String of
Bytes from a
‘source table’ to a
‘destination table’
A.19 : String
Meaning
Examples
Meaning: A block of data bytes will be Example-125. Moving 16 bytes data from DSM to
transferred from DSM (pointed by ds:si) to ESM using movs instruction.
ESM (pointed by es:di). Number of of
DSM
ESM
bytes to be moved is put into cx-register.
05010
0300F
LL at direction flag (DF) causes the
pointer registers to automatically increase
after a byte move.
To operate the pointer registers in the
decreasing mode, the DF-flag must contain
LH value.
O D I T S Z A P C
Flags affected:
05000
03000
PTR ds:si
cld
PTR es:di
1x
; (DF) = 0, pointer registers
; will be automatically incre; mented
mov ax, 0000h
mov ds, ax
mov es, ax
;--------------mov si, 3000h ; points DSM
mov di, 5000h ;points ESM
mov cx, 0010h ; 16
REP movsb ; 16 bytes
Syntax: movs
;----------------------------------------------------Example-126. (Alternative method) The above
data transfer operation can be accomplished by the
following program. Compare the execution time
and memory space occupation of these programs.
mov ax, 0000h
mov ds, ax
mov es, ax
;--------------mov si, 3000h ; points DSM
mov di, 5000h ;points ESM
mov cx, 0010h ; 16
;----------------------AGN:
Mov al, BYTE PTR ds:[si]
202
Mov BYTE PTR es:{di], al
;-----------------------Dec cx
Jz
LX
;------ adjust pointer registers
Inc
si
Inc
di
Jmp AGN
LX:-----end
;---------------------------------------------------------------------
movsw
Move a String of
Words from a
‘source table’ to a
‘destination table’
rep
Repeat
;-------------------repe
Repeat if the
result is equal to
zero
=
repz
Repeat if the (ZF)
= LH
;--------------------repne
Repeat if not
equal
=
repnz
Repeat if not zero
;------------------cmps
Compare Strings
Meaning:
Similar to movs instruction; but now the
data items are words (2 bytes long).
Meaning: REP is a prefix, which is
written before one of the following string
instructions:
Example-128:
a. REP movs
b. REP movsw
a. movs
b. movsw
c. cmpsb
d. scasw
c. REPE cmpsb or REPZ cmpsb
Keep comparing the string bytes of two tables,
until match occurs between any two bytes.
When a match occurs, the ZF flag assumes LHstate.
d. REPNE scasw or REPNZ scasw
Scan (keep checking) a string of words until a
word in the string matches with the word present in
ax-register or until all the words in the string have
been scanned.
Two data items 8-bit (16-bit) of two
strings are compared until (i) the end of
the string is reached, (ii) or compared
bytes are not equal.
cmpsb
Compare String
byte
cmpsw
Compare String
Word
Scas
Scan Strings
scansb
Scan String Byte
scasw
Scan String Word
Example-127. Write ASM codes to move 5 words
of data from DSM to ESM. The beginning address
of DSM is 03010h and that of ESM is 05010h
Example-129.
mov
cx, 0010h
mov
si, OFFSET STRING1
mov di, OFFSET STRING2
REP cmpsb
Example-130.
Example-131.
Example-132.
Example-133.
Meaning: A string of byte-size of ESM is
scanned by comparing it with al-register
until the desired item is found. The desired
item is kept in the al-register.
203
Example-134.
; al = 0Dh looking for < CR > ; 0Ah = LF
mov
al, 0Dh
mov
di, OFFSET STRING
mov
cx, 50h ; 80 items are in Table
REP
scasb
lodsb
Meaning: An 8-bit data item from a
location of a memory-based string is
loaded into al-register.
lodsw
stosb
Meaning: An 8-bit data item from alregister would be stored into a location of
a memory-based string.
stows
Mnemonic
jz
Jump if
(ZF)=LH
=
je
Jump if result is
Equal to zero
jl
Jump if Less
=
jnge
Jump if Not
Greater nor
Equal
jng
Jump if Not
Greater
=
jle
Jump if Less or
Equal
jc
Jump if Carry
=
jb
Jump if Below
=
jnae
Jump if Not
Above nor
Equal
jbe
Jump if Below
or Equal
=
jna
Jump if Not
Above
jp
Jump if even
Example-135.
mov di, OFFSET STRING
lodsb
lodsw
Example-136.
Example-137.
mov di, OFFSET STRING
stosb
stows
Example-138.
A.20 : Conditional Transfer (Branching) Instructions
Meaning
Assembly Examples
Meaning: Make a jump to the target location Example-139.
if the previous operation has put zero result mov al, 23h
in the destination location making (ZF) = 1.
sub
al, 23h
; (al)=00, LH  ZF
jz
L1
; program branches at L1
The distance of the target is in byte and must …………….
be +127 in the forward direction and -128 in L1:
nop
the backward direction.
Program control will transfer to target label if
the 1st operand was less than the 2nd operand
in the previous operation.
Program control will transfer to the target
label if the 1st operand was not greater than
the 2nd operand in the previous operation.
Program control will transfer to the target
label if the 1st operand was below the 2nd
operand in the previous operation.
Program control will transfer to the target
label if the 1st operand was not above the 2nd
operand in the previous operation.
Program control will transfer to the target
204
Example-140.
mov al, 23h
sub
al, 27h
jl
L1
…………….
L1:
nop
; (al) < 27
; program branches at L1
Example-141.
mov al, 27h
sub
al, 27h
jng
L1
…………….
L1:
nop
; (al) = 00
;program braches at L1
Example-142.
mov al, 23h
mov
bl, 27h
sub
al, bl
; (al) < (bl)
jb
L1
; program branches at L1
;-------------------L1:
nop
Example-143.
mov al, 23h
sub
al, 23h
jbe
L1
…………….
L1:
nop
Example-144.
mov al, 23h
; (al)=00
; program branches at L1
; 0010 0011
Parity
=
Jpe
Jump if Parity
is Even
label if the previous operation has produced a
result that contains even number of 1s or all
0s. All 0s are considered as even parity.
jo
Jump if
Overflow Flag
is set
Program control will transfer to the target
label if an overflow (OF bit assumes LH) had
occurred during the previous operations.
;------------------------------------------------;
a. In TCA, positive numbers are represented
by 7-bit for 8-bit word operation or 15-bit
for 16-bit operation. The MS-bit is used to
indicate +ve sign (0).
b. In TCA, negative numbers are represented
by all 8-bits for 8-bit word operation or 16bits for 16-bit operation. The MS-bit is used
to indicate -ve sign (1) and magnitude also (1x27 or -1x215).
;-----------------------------------------------;
OF-bit of 8086 assumes LH under the
following conditions of 2’s Complement
Arithmetic (TCA):
After the addition of two positive numbers
(85 = 55h, 87=57h), the result is positive but
can not be accommodated in the lower 7-bit
of the destination location. The lower 7-bit
can accommodate only +127.
;-----------------------------------------------
js
Jump if the
result is Signed
jnz
Jump if Not
logic high at
Zero flag (ZF)
=
jne
Jump if result is
Not Equal to
zero
jge
Jump if Greater
or Equal
=
jnl
Jump if Not
Less
Program control will transfer to the target
label if the previous operation has produced a
negative result (MSBit = LH)..
Program control will transfer to the target
label if the previous operation has produces a
non-zero result. As a result ZF has not
assumed LH-state
Program control will transfer to the target
label if the 1st operand was greater or equal of
the 2nd operand during previous operation.
205
mov ah, 01h
add
al, ah
jp
L1
…………….
L1:
nop
; 0010 0100 = EVN parity
; program branches at L1
Example-145.
85 + 87 (55h + 57h) = 172 (AC = 1010 1100). To
extract actual result of +172 from AC, we must
take the help of OF bit.
mov al, 85 ; (al) = 55h
mov ah, 87 ; (ah) = 57h
add
al, ah ; (al) = AC, (OF) = LH
jo
L1
; program branches at L1
;--check sign bit-----mov ah, al
shl
ah, 01h
jnc
L2
; lower 7-bit is +ve result
;--- (al) = negative result in 2’sC form-------mov ah, 00h
sub
ah, al ; (al) = absolute Binary
call
BIN2BCD8
call
SHOWMS ; show result with - sign .
hlt
;----------L1: ;--all 8-bit carry positive result---call
BIN2BCD8
call
SHOWPS ; show result with + sign.
hlt
;-----------L2: ;--lower 7-bit carries +ve result---jmp
L1
Example-146.
mov al, 01h
sub
al, 02h ; (al)= FFh (-1) = 1111 1111
js
L1
; program branches at L1
…………….
L1:
nop
Example-147.
mov ax, 1234h
sub
ax, 1235h ; (al) < 1235 ; (ZF) != 1
jne
L1
; program branches at L1
…………….
L1:
nop
Example-148.
mov al, 23h
cmp
al, 23h
jge
L1
…………….
L1:
nop
; (al)= 23
; program branches at L1
jg
Jump if Greater
=
jnle
Jump if Not
Less nor Equal
jnc
Jump if Not
logic high at
Carry flag (CF)
=
jnb
Jump if Not
Below
=
jae
Jump if Above
or Equal
ja
Jump if Above
=
jnbe
Jump if Not
Below nor
Equal
jpo
Jump if Parity
is Odd
=
jnp
Jump if Not
even Parity
Program control will transfer to the target
label if the 1st operand was greater than the
2nd operand in the previous operation.
Example-149.
mov al, 23h
mov bl, 20h
sub
al, bl
jg
L1
…………….
L1:
nop
Program control will transfer to the target
label if the 1st operand was not below than
the 2nd operand in the previous operations. As
a result, the CF did not assume LH-state.
Example-150.
mov al, 23h
sub
al, 21h
jnc
L1
…………….
L1:
nop
Program control will transfer to the target
label if the 1st operand was above than the 2nd
operand in the previous operations.
Example-151.
mov al, 47h
mov
cl, 34h
cmp
al, cl
; (al) > (cl)
ja
L1
; program, branches at L1
;-----------------------L1:
nop
Program control will transfer to the target
label if the previous operation has produces a
result that contains odd number of 1s.
jno
Jump if Not
logic high of
Overflow flag
Program control will transfer to the target
label if the previous operation has not
produced any overflow.
jns
Jump if Not
logic high for
Sign flag (SF)
Program control will transfer to the target
label if the previous operation has not
produced any negative result.
206
Example-152.
mov al, 23h
sub
al, 03h
jpo
L1
…………….
L1:
nop
; (al ) > (bl)
; program branches at L1
; (al) > 21h, (CF) = 0
; program branches at L1
; 0010 0011
; 0010 0000
; program branches at L1
Example-153.
Similar to jo instruction
Example-154.
mov al, 23h
sub
al, 22h
jns
L1
…………….
L1:
nop
; (al)=01h ; (SF) = 0
; program branches at L1
Mnemonic
call
Call a
subroutine
unconditionally
A.21 : Unconditional Transfer (Branching) Instructions
Meaning
Assembly Examples
Note: The execution mechanism of the Example-155.
unconditional call instruction is same as the call SURNAME or
unconditional jmp instruction. Therefore, the call bx
readers are referred to the description of the
jmp instruction for the clarification of the The offset (16-bit = 0000h – FFFFh) part of the
call instruction.
SUR is passed by putting the name of the
;------------------------------------------------;
subroutine (here SURNAME) or via bx-register or
A subroutine (SUR) is a small program, any other valid pointer register. This is an
which resides in memory with a ‘name’. A example of an ‘indirect near call’ instruction.
programmer can use the SUR in his main line Please see: jmp bx instruction.
program (MLP) for as many times as he ;------------------------------------------------;
wishes by executing the following Example-156.
instruction:
call [bx] or
call
SURNAME
call WORD PTR [bx] or
call WORD PTR ds:[bx]
The label ‘SURNAME’ has a 20-bit address,
which can also be represented inn the
The offset part of the SUR is passed via two
segment : offset format.
locations of a memory based table. The beginning
;------------------------------------------------;
address of the table is pointed by bx-register. This
When the MLP calls a SUR, the MLP goes to
is an example of a ‘indirect near call’ instruction.
the beginning address of the SUR, executes
Please see jmp [bx] instruction.
the SUR, returns to the MLP, and resumes
;-----------------------------------------------;
the execution of MLP.
Example-157.
DWORD PTR ds:[di]
During SUR call, the CPU saves the ‘return call
address = RADR’ in the segment:offset form
on the stack. RADR is the location of the The address ( in segment : offset form) of the SUR
MLP, which comes just after the call is kept in a memory based table. The beginning
instruction. To understand the mechanism of address of the table is passed via ds and bx
saving RADR on the stack, please see the registers. This is an example of a ‘indirect far call’
instruction. Please see the jmp
WORD PTR
push instruction.
ds:[di] instruction.
;------------------------------------------------;
0000:1000 B0 23
L1: mov al, 23h
Example-158.
0000:1002 E8 08 10
L2: call
SUR1
0000:1005 04 45
L3: add
al, 45h
call 20_Bit_Address or
0000:1007 90
nop
call 02050h (0000:2050) or
9A
50 20 00 00
0000:1008 02 C8
SUR1: add cl, al
0000:100A C3
ret
In the above example, the RADR is
0000:1005 (01005h).
The Stack Diagram with RADR shown:
TOS
Stack Grows
TOS after call
BAS
ret
SBA
Stack Segment Memory
09000 Filled up
00
Seg of
08FFF
00
RADR
08FFE
Offset of
10
08 FFD
05
RADR
08FFC
07000
00000
207
The address (segment : offset form) is directly
given in the instruction. This is an example of a
‘direct far call’ instruction. Please see the
instruction: jmp
20_Bit_Address
;------------------------------------------------------
ret
Return to main
line
program
after executing
the subroutine
jmp
Jump to a
target location
unconditionally
The execution of the ret instruction allows
the CPU retrieving the return address (RADR
= return label) from the stack, putting it in the
CS:IP pair, and then resuming the MLP
program correctly.
Meaning: The CPU unconditionally jumps
to another ‘memory location or Address or
Label’ to begin program execution.
Example-159.
ML1: call
SUR1
ML2: nop ; Return label
SUR1: nop
……….
ret
Example-160.
L1: 0000:1000 - jmp
L3
The Label of the target location is L3. The segment
part of L3 is same as the current instruction. The
offset of the destination label can be as large as
127 byte in the forward direction, and it is coded in
place of L3. The offset is measured as the number
of bytes between the current instruction and the
destination instruction; but excluding the bytes of
both end instructions.
Flags affected: unaffected
;---- Jump in the forward direction------------------L1: 0000:1000 – jmp L3
: EB 03
L2: 0000:1002 – nop
: 90
L2: 0000:1003 – mov al, 34h : B0 34
L3: 0000:1005 – nop
In the above program, current instruction is at label
L1, and the target instruction is at label L3. The
distance (offset) between these two labels is 3-byte
(90 B0 34). The MASM assembler has coded the
distance as 03 in place of L3.
The CPU transfers program control at L3 after the
execution of instruction of L1. After fetching the
code bytes for the instruction of L1, the PC
(Program Counter = CS:IP) holds the value
0000:1002. After the execution of the instruction
of L1, the CPU is about to reach at L3 and reaches
there by adding 03 with the present content of IPregister. The CPU begins program execution from
address 0000: (1002 + 03) = 0000:1005, which is
the address of label L3.
;-----Jump in the backward direction----------------When the target location lays in the backward
direction, the distance (offset) between the ‘next
instruction’ and the ‘target instruction’ is coded in
2’s complement form. The distance can be as large
as -128 byte. The offset is measured as the number
of bytes between the current instruction and the
destination instruction; but including the bytes of
both end instructions.
L3: 0000:1000 – mov ah, 12h
0000:1002 – mov al, 45h
0000:1004 – add al, 03h
208
: B4 12
: B0 45
: 04 03
L4: 0000:1006 – jmp
L5: 0000:1008 – nop
L3
: EB F8
: 90
In the above example, the program branching takes
place at label L4 and the target label is L3 in the
backward direction. The number of bytes including
both instructions is 8. The 2’s ccomplement of -8
is coded as F8h, and it takes the place of L3.
;-----------------------------------------------------------Example-161.
jmp
di
The segment part of the target label (see codes
below) is same as the current instruction. The
offset is an unsigned 16-bit number and is loaded
into di-register before the execution of the current
instruction. The unconditional jump could be made
either in the forward or backward direction. During
program execution, the CPU copies the content of
di-register into IP-register.
L1: 0000:1000 – mov di, OFFSET L4 : BE 07 10
L2: 0000:1003 – jmp di
: FF E7
L3: 0000:1005 – add al, 34h
: 04 34
L4: 0000:1007 – mov al. 56h
: B0 56
L5: 0000:1009 – mov di, OFFSET L3 : BE 05 10
L6: 0000:100C – jmp di
: FF E7
L7: 0000:100E -
.
In the above example, jump instruction is executed
at L2 to reach at target L4. The 16-bit OFFSET
(1007) of L4 has been coded in the instruction, and
been loaded into di-register. For jump at backward
direction to label L3, the offset 1003 of L3 has also
been coded and loaded into a pointer register.
;----------------------------------------------------------Example-162.
jmp
[di] or
jmp
WORD PTR [di] or
jmp
WORD PTR ds:[di]
The 16-bit offset part of the target label is now
kept in two consecutive memory locations of a
memory-based table. The beginning address of the
table is passed via di-register. The CPU begins
program
execution at the target address just by
loading the IP-register with the content of
the
memory-based table pointed by di- register or any
other valid pointer register.
[di]
BAT
MBA
Scratch Pad Memory
00501
10
0E
00500
00000
BAT = Beginning Address of Temporary Table
209
L1: 0000:1000 - BF 00 05 : mov
0000:1003 - B8 0E 10 : mov
0000:1006 - 89 05
: mov
L2: 0000:1008 - FF 25 : jmp
0000:100A - B0 45 : mov
0000:100C - 04 34 : add
L3: 0000:100E - 90
: nop
di, 0500h
ax, OFFSET L3
WORD PTR ds:[di], ax
[di]
al, 45h
al, 34h
In the above program, the top 3 instructions has
initialized a ‘memory based table’ with the offset
(100E) part of the target label L3. At L2, the CPU
has loaded the IP-resister with the content of the
said table. The program execution will start at label
L3 with address 0000:100E.
This is an example of an ‘indirect near jump’. It is
‘indirect’, because the offset part is not passed
directly rather in an ‘indirect’ way using a memory
based table.
;----------------------------------------------------Example-163.
jmp
DWORD PTR ds:[di]
The segment:offset (seg : off) of the target label is
taken from a 4-byte wide memory based table. The
beginning address of the table is passed via diregister (or any other valid pointer register). The
CPU begins program execution at the target
address just by loading the CS- and IP-registers
with the content of the memory-based table
pointed by di-register or any other valid pointer
register.
[di]
MBA
Scratch Pad Memory
00503
00
segment
00502
00
00501
10
Offset
12
00500
00000
L1: 0000:1000 - BF 00 05 : mov di, 0500h
0000:1003 - B8 12 10 : mov ax, OFFSET L3
0000:1006 - 89 05
: mov WORD PTR ds:[di], ax
0000:1008 - B8 00 00 : mov ax, SEG L3
0000:100B –89 45 02 : mov WORD PTR ds:[di+02h], ax
L2: 0000:100E - FF 2D : jmp DWORD PTR ds:[di]
0000:1010 - 04 23
: add al, 23h
L3: 0000:1012 - 90
: nop
In the above program, the top 5 instructions
initialize a ‘memory based table’ with the
segment:offset (000:1012) part of the target label
L3. At L2, the CPU loads the CS- and IP-resisters
with the content of the said table. The program
execution will begin at address 0000:1012.
210
This is an example of an ‘indirect far jump’. It is
‘indirect’, because the segment:offset part is not
passed directly rather in an ‘indirect’ way, which is
a memory table. It is a ‘far jump’, because the
‘target label’ and ‘fly label’ do not lay in the same
‘Code Segment’. In this example, C(CS) = 0000h
is a coincidence; it could be anything from 0000h –
FFFFh as the CS-register is loaded.
;-----------------------------------------------------------Example-164.
jmp
20_Bit_Address
L1: 0000:1000 – EA 20 10 00 00 ; jmp 01020h
;--------------------;--------------------L3: 0000:1020 Alternate Codes which MASM can assemble:
1. The programmer knows the 20-bit physical
Address of the target location : 01020
(0000:1020).
2. Store the segment;offset part of the above
Address in a memory based table.
3. Execute the following instruction:
jmp DWORD PTR ds:[di]
mov
mov
mov
jmp
di, 0500h
WORD PTR ds:[di], 1020h
WORD PTR ds:[di], 0000h
DWORD PTR ds:[di]
This instruction accepts the 20-bit target address
directly as an operand. The address must be given
in the segment:offset format.
There is no assembly syntax for this instruction so
that MASM can find machine codes for it. The
binary codes are determined by looking at the
‘Instruction Template’ of the 8086 microprocessor.
This instruction is very helpful in the development
of large program especially the ‘Monitor Program
or Operating System’ of an 8086 based system.
The programmer visualizes the locations of ‘free
memory space’ and easily makes a ‘direct far
jump’ to accommodate further program codes. It
relives from computing the values of the offset of
the target location
211
Mnemonic
loop
A.22 : Iteration Control Instructions
Meaning
Assembly Examples
Meaning: This instruction decrements cx- Example-165.
register and then checks if cx is zero by
L1:
looking in its content. If not, the loop is
repetitively executed. The working principle
of the loop instruction could be expressed by
the Flow Chart of right column.
HERE:
0004h ---> cx
cx - 01h --> cx
Flags affected: none
Syntax:
Assembly code: HERE: loop HERE
N
cx = 0
?
Y
lo
L1:
mov cx, 0004h
HERE: dec
cx
jnz
HERE
or ;--------------------------------------------------mov cx, 0004h
HERE: loop
HERE
loope
Loop until cxregister is
Equal to zero
=
loopz
Loop until ZF
becomes logic
high
Meaning: This instruction decrements the
content of cx-register and checks if cx is zero.
If not loope is repetitively executed.
However, during the execution of loope
instruction, the CPU also checks if the ZF
has assumed LH. After loading some value
into cx-register, the CPU might be executing
some other ALU operation, which will affect
the ZF flag. The CPU will stop the execution
of loope instruction whenever it finds (i) cxregister is zero, or (ii) ZF flag is LH. The
working principle of the instruction is
explained by the Flow Chart of the right
column.
In the above program, the CPU keeps executing
the ‘HERE: loop HERE’ instruction until the cxregister is emptied.
Example-166.
L1:
0004h ---> cx
L2:
03 -
al
HERE:
Cx – 01 ---
cx = 0
?
cx
N
Y
Al – 01 –
al = 0
?
Y
al
N
lo
Case-1: CPU keeps executing loope until cx is
zero
0004h  cx
03h  al
HERE: al – 01h  al
loope
HERE
212
loopne (loopnz)
jcxz
Jump if CX
register is Zero
Mnemonic
int
Interrupt
into
Interrupt ON
overflow
iret
Return from
Interrupt
subroutine
Example-167.
Meaning: The program control branches to a
target location if the content of cx-register is
found zero. Otherwise, the CPU continues
the execution of the next instructions. The
distance of the target location must be in the
range of 128 (minus) byte in the backward
direction and 127 (plus) byte in the forward
direction. To take the decision, the CPU
looks at the content of cx-register and not on
the LH-state of the ZF-bit.
Example-168.
L1:
mov
cx, 0001h
dec
cx
jcxz
L3
L2:
loop
L2
L3:
---------------In the above program, the CPU will skip the
execution of the instruction at label L2, because
(cx) = 0000h. The program branches at label L3.
A.23 : Interrupts Instructions
Meaning
Example
Meaning: The execution of the next Example-169.
instruction of the current program may be L1: nop
interrupted by inserting instruction like int L2: int 10h
nnh (known as software interrupts, where L3: mov al, 23h
nn = 00h – FFh). The value of nnh is called ;-------------------------Interrupt Type Code (ITC Code). The 20-bit
address of the ISR (Interrupt Sub Routine) is
computable from the ITC code following the ISR10: ; Interrupt subroutine due to int 10h
steps that have been discussed elsewhere. ;----------Interrupts of these are nonmaskable. There is Iret
no instruction to disable these interrupts.
In the above program, the CPU has encountered
the interrupt of type int 10h at label L2. The CPU
will be immediately interrupted and will jump to
the ISR10. After finishing the ISR10, the CPU will
resume the MLP at label L3.
Meaning: Overflow condition will exist if Example-170.
the CPU is asked to add two 8-bit (16-bit)
mov al, 70h
signed positive numbers and the result could
add
al, 30h ; (al) = A0h, (OF)=LH
not be accommodated within 7-bit (15-bit) of L2: into
the destination location. Under this
----------------------------circumstance, the OF-bit of the flag register
will assume LH-state. After the ALU ISR04: (ISR due to ITC code 04h/Overflow )
instruction, if the into instruction is inserted
-------------------------and that that the OF-bit has already been set iret
to LH in the previous operation; the CPU will
be interrupted and will jump to the ISR04 for
the ITC code of 04h.
Meaning: Execution of the IRET instruction
at the end of ISR retrieves the FR and the
return address from the stack. The original
enable condition of the interrupt is preserved.
The CPU becomes ready to accept the next
interrupt.
213
Example-171.
ISRINTR:
------------------Iret
Mnemonic
clc
Clear Carry
Cmc
Complement
Carry
stc
Set Carry
Cld
Clear Direction
Flag
std
Set Direction
Flag
Cli
Clear Interrupt
Flag
sti
Set Interrupt
Flag
Mnemonic
hlt
wait
esc
lock
Mnemonic
nop
A.24 : Flag Operations Instructions
Meaning
Assembly Examples
Meaning: Clear (Put LL) carry flag of 8086.
Example-172.
clc
; (CF) = 0
Meaning: Carry-bit is complemented to Example-173.
make it LH from LL and vice versa.
mov al, 0FEh ; (al) = -2
add
al, 02h
; (CF) = 1
cmc
; (CF) = 0
Meaning: Carry-bit of the FR-register is Example-174.
made LH.
Meaning: Clear Direction-bit of FR-register.
Example-175.
cld
; (DF)=0
Meaning: The Direction-bit is made LH.
Example-176.
Meaning: Logic-L is placed at the IF-bit of
Flag Register. As a result, the CPU does not
respond to ‘maskable interrupt’ that arrives at
its INTR pin.
Meaning: Logic-H is placed at the IF-bit of
Flag Register. As a result, the CPU acquires
the ability to respond to ‘maskable interrupt’
that arrives at its INTR pin.
Example-177.
cli
; (IF) = 0
Example-178.
sti
; (IF)=1
A.25 : External Synchronization Instructions
Meaning
Example
Meaning: CPU stops fetching and executing Example-179.
instructions. It enters into halt state.
Interrupting signal on the RESET-pin or
INTR-pin or NMI-pin will bring the CPU
out-of-its halt state.
Meaning: WAIT instruction is included in Example-180.
the instruction set of the 8086 in order to
synchronize the parallel operation between
the 8086 and the 8087 math coprocessor.
Wait instruction is executed to tell the 8086
to continuously check the ‘not-busy’
condition (TEST/-pin is LL) of the 8087.
Meaning: The ESC instruction allows the Example-181.
8086 to pass instructions to the 8087 that
belongs to the 8087.
Meaning: In a multi-processor system, only Example-182.
one processor CPU or Coprocessor should be
allowed to use the BUS. This is ensured by
executing the LOCK instruction.
A.26 : No Operation Instruction
Meaning
Examples
Meaning: The CPU does do any useful Example-183.
work. It just increments the program counter L1: 0000:1000 – nop : 90
(CS:IP) to fetch the next instruction. NOP L2: 0000:1001 may be considered as a tiny ‘time delay’.
L3: -----------------------------
214