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INTERCONNECT MODELING
M.Arvind
2nd M.E Microelectronics
OVERVIEW

Introduction to On-Chip interconnects

Modeling the parasitics

Elmore Delay Model

Repeater insertion

Min delay condition

Power Model

Optimizing Power
Introduction to On-chip
interconnects

Wires linking the transistors together

Three types of interconnects :

Local

Semi-global and

Global interconnect
Introduction to On-chip
interconnects

Can be modeled as R, RC, LC, RLC or RLGC
network.
Power lines
R,RL
Signal lines
C, RC
Clock lines & buses
RLC
Modeling a piece of wire
Capacitance Modeling

Capacitance
•
cw = 2 * (cg + cf * cc )
•
cf is the coupling factor
Capacitance Modeling (cont)

cg has 2 components: cg1, cg2
cg1  f ( ILDT , w,  )
cg 2  f ( ILDT ,  , s, h)
cc  f (s, , h)
Simplified Capacitance Model

For a circuit designer
 ILDT, h and ε are fixed. Therefore,
cg1  f ( w)
cg 2  f ( s )
cc  f ( s )
Fringing Effects
Cf 1
Cf  2
Cf  0
Cf 1
Cf 1
Modeling Wire Resistance

Resistance
rw 

l
A

 l
hw

 
h sq
Pros and Cons of Cu

Pros


Better electro-migration resistance
Cons

Cu atoms diffuses into SiO2

Cladding layers of TiN, Si3N4 used to prevent this

Increases the resistance
Elmore Delay Model

Delay of a RC network is given by
D  R1C1  ( R1  R2 )C2  ( R1  R2  R3 )C3  ...
 ( R1  R2  ...  Rn )Cn
Delay of a long wire


Delay grows quadratic
Hence need repeaters
Repeater Insertion

Repeaters are placed to reduce delay
Repeater Insertion (cont)

Delay grows linear
Modeling the repeater



Repeater is a large inverter (5-25μm) placed inbetween interconnect lines.
Cgate, Cp α size of the repeater
RT = VDD/2*Iavg, where Iavg = ∫Iddt in the interval Td
Modeling the repeater (cont)
I d  I dlin
 I dsat (1   (Vds  Vdsat )
Vds  Vgs  Vth
Vds  Vgs  Vth
I dsat  I d at Vds  Vdsat  Vgs  Vth
I dlin
2
ds
V
W
 eff Cox {(Vgs  Vth )Vds  }
L
2
Delay equations

Delay of an interconnect segment is
D= R T * (Cw  Cgate

Cw
 C p )  Rw * (
 Cgate )
2
Total delay is
Cw
D tot = {R T *(Cw  Cgate  C p )  Rw *(  Cgate )}* N
2
Optimal Repeater Size and
Spacing

The minimum delay condition
cwl
rwl cwl
rT
D [
{(cgate  c p ) size  }  {
 cgate s}]* N
size
N
N 2N
D
D
 0;
 0;
size
N
rt cw
Size 
rwcgate
N
rwcw
2rt (cgate  c p )
Power modeling

Total power dissipated in the interconnect network
is given by
•
•
•
•
Ptotal= Pdy + Psc + Pleak
Pdy = Ctotal V²ddf
Psc = Isc per μm Vdd Wtotalftt
Pleak = Ileak per μm WtotalVdd
Where is the switching factor, tt is the time taken
for the input to transit from Vthn to Vdd – Vthp
Power modeling (cont)
Ctotal
Cw
 (Cgate  C p  ) * N
2
Vgs Vth
I leak  I 0 e
nVt
(1  e
Vds
Vt
)
Vdd
I sc  I d at Vgs 
, Vds  0.1Vdd
2
Wtotal  Wmin * size * N
Optimizing power

Min delay does not imply min power
Techniques to Reduce Power

Can be reduced by decreasing

Supply voltage

Size of repeaters

Number of repeaters
Optimal Power Delay Tradeoff
References

William J.Dally John W.Poulton., ”Digital Systems Engineering”
Cambridge University Press,1998

Kaustav Banerjee et al., ”A power-optimal insertion methodology for
global interconnects in nanometer designs” IEEE TRANSACTION
ON ELECTRON DEVICES, VOL. 49, NO. 11, NOVEMBER 2002

Kaustav Banerjee et al., ”A global interconnect optimization scheme
for nanometer scale VLSI with implications for latency, bandwidth,
and power dissipation” IEEE TRANSACTION ON ELECTRON
DEVICES. VOL. 51, NO.2, FEBRUARY 2004.
Thank You