Download REFERENCES

REFERENCES
[1] A. Collins, "Solid State Solutions for Electricity Metrology", IEE Metering and Tariffs for
Energy Supply, no. 462, pp. 1, May 1999.
[2] W. Koon, "New Developments in Current Sensors in Solid State Meters", Metering
International Magazine, Issue 3, pp. 50 - 52,2001.
[3] http://www.1oadcontrols.com/application notes/pdfs/power sensors& load control.pdf
[4] A. Bilotti, "Monolithic Magnetic Hall Sensor Using Dynamic Quadrature Offset
Cancellation", IEEE journal of solid-state circuits, vol. 32, no. 6, pp. 829-836, June 1997.
[5] G. Bjorklund, "Improved Design of Hall Plates for Integrated Circuits", IEEE
Transactions on Electron Devices, Vol. ED-25, No.5, May 1978.
[6] Y. Kanda and M. Migitaka, "Effect of mechanical stress on the offset voltage of Hall
devices in Si IC", Phys. Status Solidi (a), vol. 35, pp. KI15-KI18, 1976.
[7] M. Ai and M. Shimazoe, "Cantilever-type Displacement Sensor using Diffused Silicon
Strain Gauges", Sensors and Actuators, 2, pp. 207-307, 1982.
[8] R.S. Popovic (B.E. Jones), "Hall Effect Devices, Magnetic Sensors and Characterization
of Semiconductors", Adam Hilger, Bristol, England, 1991.
[9] R.S. Popovic, "Hall-Effect Devices", Sensors and Actuators, 17, pp. 39-45, 1989.
[10]
G.S.
Randhawa,
"Monolithic
Integrated
Hall
Devices
In
Silicon
Circuits",
Microelectronics Journal, vol. 12, no. 6, pp. 24 - 25,1981.
[11] W. Gapel, l Hesse and IN. Zemel, "Sensors, Volume 5, Magnetic Sensors", VCH
Publishers Inc., New York, USA, 1989.
104
on
Tutorial
B. [12J
2001. and Application", Honeywell
Effect
[ 13J
[14] 1. Gilbert, "Technical Advances
1 - 6,
00-1, Anaheim,
Paper
EXPO, Technical
2000.
Emerald, "'Non-Intrusive'
[1
Current-Sensing Techniques
Protection for Power Electronics", International Appliance
Detection
Paper STP 98-1, pp. 1 - 18, May 1998.
VVLJJ.HV':U
IC Applications
[16J J.
27701
pp. 1
, Allegro MicroSystems, Inc.,
34.
F.
[17] P.M.
S.
and
"High Sensitivity
Concentrators", The 11 til
Planar Micro
on Solid-State ::>erlsors and
Munich,
June 2001.
"Alternating current static watt-hour meters
[18] CEl/lEC
energy
Safe,
vlU."''''''>':>
1 and
, Edition
1996.
Ebel, "Modem measurement techniques
[19]
on
[20] , Metering International
Effect in Semiconductors",
meters
4, pp. 15
.l'AUSUoL,U
19, 1
Custom Published
pp. 1 ­
November
1] C.
measurement using
Hall
Institute of
R.F. Wick, "Solution of
Physics, Vol. 25,
Electronic
1-
field problem
Germanium gyrator",
of Applied
1954.
105
References
[23] A. Bakker, S. Bellekom and S. Middelhoek, "Low-Offset Low-noise 3.5 mW CMOS
Spinning-Current Hall Effect Sensor with Integrated Chopper Amplifier", Physical Sensor
Applications, 28C2, pp. 1045-1048, September 1999.
[24] S. Bellekom, S. Yin and A. Bakker, " Spinning-current Hall plate with integrated
switches", Proceedings of the ProRISC Workshop Circuits, Systems and Signal Processing,
pp. 37-42, 1997.
[25] A. Bakker, K Thiele and J.H. Huijsing, "A CMOS Nested-Chopper Instrumentation
Amplifier with 100-nV Offset", IEEE Journal of Solid-State Circuits, Vol. 35, no . 12,
December 2000.
[26] T. Hara, N. Mihara, N. Toyoda and M. Zama, "Highly linear GaAs Hall devices
fabricated by ion implantation", IEEE Trans. Electron Devices, Vol. ED-29, pp . 78-82, 1982.
[27] J.W.A. von Kluge, "Analysis of split-current magnetic field sensitive resistors", Sensors
and Actuators, A 3054, pp. 5, 2001.
[28] B. Razavi CW. Stephen), "Design of Analog CMOS Integrated Circuits", McGraw-Hill ,
New York, pp. 100 - 369, 377 - 397 and 418 - 422, 2001.
[29] P.E. Allen and D.R. Holberg, "CMOS Analog Circuit Design", Saunders College
Publishing, Orlando, Florida, pp. 197 - 240 and 365 - 387, 1987.
[30] A. Bakker and J.H. Huijsing, "A CMOS Chopper Opamp with Integrated Low-Pass
Filter", Proceedings of the ProRISC Workshop on Circuits, Systems and Signal Processing,
pp. 25 - 28, 1997.
[31] M. Degrauwe, E. Vittoz and I. Verbauwhede, "A Micropower CMOS-Instrumentation
Amplifier", IEEE Journal of Solid-State Circuits, Vol. SC-20, no. 3, June 1985 .
[32] R.C. Yen and P.R. Gray, " A MOS Switched-Capacitor Instrumentation Amplifier",
IEEE Journal of Solid-State Circuits, Vol. SC-17, no. 6, December 1982.
Electrical, Electronic and Computer Engineering
106
References
[33] South African Micro-Electronic Systems, "Single Phase Bi-directional Power / Energy
Metering IC with Instantaneous Pulse Output", http ://www.sames.co.za/energy/sa2002h.pdf.
pp. 1 - 12, 2002.
[34]
Analog
Devices,
"Energy
Metering
IC
with
Pulse
Output",
http://www.analog.com/productSelectionipdfI.ADE7755 O.pdf, pp. 1 -16,2002.
Electrical, Electronic and Computer Engineering
107
ADDENDUM A: 1.211M CMOS PROCESS PARAMETERS e
sames
CMOS1.2 Process
Physical Characteristics
Process Geometry
1.2 Micron
Metal II Width
2.0~
Metal II Space
20~
Process Num ber
C1201 (S .M)/C 1202(D .M)
Operating Voltage
5v
Gate Poly Width
12~
Well Doping
N-WELL
Gate Poly Space
18~
Metal Layers
2
Bottom Poly Width
30~
Poly Layers
2
Bottom Poly Space
20~
Contact
1.5~
N+/P+Space
2.0~
Via
1 . 5~
N+ to N-WELL
7~
Metal I Width
20~
N+ to P+
g~
Metal I Space
20~
OR-0003{
CROSS SECTIONAL VIEW OF THE CMOS1.2 PROCESS
ID vs YD. W/L
5
til
_0
<­
c
~
/
2
~
u
c
-e
0
0
-3
~
/ vcJ4.e~
3
Y
~/
iY'
o
!--
1
10 vs VO. W/L =
20/1.2
VGS .!.s.ev
4­
5
=
-
I
I/)
-='
~
~
~
I
Vcs -2.0'l
~
VGs=1. 0V
.5
:3
4
~
'0
5
6
M68- 1780
~ SAMES
."
(L
-I
-.5 Ii. V
Ij:;:.­
vcs=
3.0V
I
vas=
2.0V
r-­
J.
vcs =-1.0V
2
3
Orcin
5
6
8
voltage V
N· CH transistor IV characteristics of a 20 /1.2 device
N-CH Ira nsistor IV characteristics of a 20/1 .2 device
---------
I-­ ~
I-~
1
I
/
-1.5
o
Oroin Vol tage V
~
/v-J I
-2
0
e
_I
V as --5 .0V
-2.5
.§. Ves -3.eV
2
J
20/1.2
1/2
WF-H004.(lOl
REV. 8
108
I.211m CMOS Process Parameters
Addendum A
CMOS1.2 Process Electrical Characteristics
n-ch transistor
Parameters
Threshold Voltage (linear
extrapolated)
Sym
Min
Typ
VTO N
0.55
0.75
g
Body Factor
Conduction factor (normalized)
Effective Channel Length
Width Encroachment
Punch Through Voltage
Poly Field Threshold
Threshold Voltage Offset
(two sigmas)
p-ch transistor
bN
Leff N
OWN
BVDSS N
VTF PIN)
OVT N
Threshold Voltage (linear
extra polated)
Body Factor
VTO p
Conduction Factor (normalized)
Effective Channel Length
bp
Leffp
Width Encroachment
DWp
Punch Through Voltage
Poly Field Threshold
Threshold Voltage Offset
(two sigmas)
(T = +25°C unless otherwise noted)
Max
Unit
Comments
0.95
0.35
60
75
90
0.7
0.9
1.1
0.6
V
100/1.2 device
V112
100/1 .2 device
~A1V 2
100/100 device
~m
~m
V
9
10
100/1.2 device
perside
100/1.2 device
V
5
-1 .1
-0.9
g,
-0.7
0.4
mV
100/10 device
V
100/1.2 device
V112
100/1 .2 device
20
25
30
~A/V 2
100/100 device
0.8
1.0
1.2
11 m
100/1.2 device
~m
per side
0.6
BVDSS p
-9
-10
VTF PIP)
OVTp
V
V
mV
5
100/1.2 device
100/10 device
diffusion & thin films
Well (field) Sheet Resistance
N+ Sheet Resistance
N+ Junction Depth
RW(" )
RN+
0.5
1
1.5
kW/O
20
30
40
WID
100
WID
0.3
XjN +
P+ Sheet Resistance
Rp+
P+ Junction Depth
X p•
60
80
11 m
0.3
11 m
RpOLYN
15
25
35
WID
Gate Poly Sheet
Resistance (p-ch)
RpOLYP
15
25
35
WID
Bottom Poly Sheet Resistance
15
25
Metal 1 Sheet Resistance (SLM)
RpOLYB
RMl
Metal 1 Sheet Resistance (DLM)
RM 2
50
WID
mWIO
mW/O
Metal2 Sheet Resistance (DLM)
RM2
30
mWIO
Gate Poly Sheet
Resistance (n -ch)
n-well
35
30
capacItance
1.28
1.38
1.58
fF III m2
Gate Oxide
Cox
Poly Gate To Bottom Poly
Cpp
0.86
fF I~ m2
Melal1 to Poly
CM1P
CMM
0.057
fF III m2
fF I~ m2
Metal2 10 Metal 1
M 68· 1780
~
SAMES
Electrical, Electronic and Computer Engineering
0.035
interpoly capa cilo
-2/2­
109
ADDENDUM B: OPERATIONAL AMPLIFIER DESIGN
Specifications:
•
VDD = 5 V
•
A V(opo en-loop)
•
UGBW prod = 1 MHz (stable)
•
Slew-rate
=
> 80 dB
2V Ills
Figure B.6.1 shows the proposed circuit.
M9
m=2
M2
m=2
MI
m=2
M3
m=4
Rj=IOk
Vout
m=4
r------.. INP
MI2
m=2
M6
m=2
m=2
MIl
m=2
Figure B.6.1 CMOS operational amplifier
Design equations:
SR
--=
2n(VGS -
VJ
(B. 1 )
V
SR
+V
(B. 2)
UGBW
GS
(2n(UGBW))
I
(B. 3)
110
Operational Amplifier Design
AddendumB
The input stage's gate-source voltage can thus be calculated from equation B.3 as
VGSS
2
= -+ 1.0
(B. 4)
27r
=1.318V
but, we know that
(B. 5)
=
where,
(B. 6)
IDS
gos
go8
(B. 7)
VA?
=
I D8
(B. 8)
VAN
From figure B.6.1 , it can be seen that
I D8
=
(B. 9)
IDS
thus,
21 -k WS
D) P
AVl =
L
5
(21"'J
( B. 10 )
VAP
and so too,
2IDll k n
AV2
Electrical, Electronic and Computer Engineering
~l
L) \
(~J
VAN
(B.11 )
111
Operational Amplifier Design
Addendum B where,
12.5 JlJl But we know that
W.
_II
(B.12)
7 , from the bias ratios and thus from equation B.3,
L"
=
Av
95dB ~ 56000
= AVIAn
/
-~
210skp Ws
Ls
(~;' J
x~
210llkn
~I
(B. 13 )
L"
(2::, J
From this we can calculate Ws < 46.l. A width/length ratio of approximately ~
Ls
Ls
=
38,
was chosen such as to accommodate for the 1.2 )..lm process. This will assist in the matching
of the devices within the operational amplifier. M4 is biased the same as Ms and symmetry is
required in the differential stage such that the inverting and non-inverting input transistors
amplify symmetrically.
I
011
=
JlCox ~ I (V
_ V )2
2 L
GSII
I
( B. 14 )
II
( B. 15 )
and thus,
0.92 V As M8 is biased under the same conditions as M 7, VDC
(B. 16)
=
0 and thus M8 will remam
III
saturation.
Electlical, Electronic and Computer Engineering
112
Operational Amplifier Design
Addendum B
Compensation
The compensation capacitor needed is calculated from
c=
m
=
IT
SR
(B.17)
25f.1A
2V/j1!
=12.5pF
The resultant pole positions are thus as follows;
1
( B. 18)
But the DC gain of the second stage is high and thus
(B. 19)
And so;
(B. 20)
=
~(2)(12.5JlX75f.1X7)
=114.56 f.1A/ V
( B. 21 )
= (
30
12.5f.1A
JII ( 12.5f.1A
60 J
=1.6MQ
(B. 22)
1
(14.56 e-6)(1.6 e6)(1.6 e6)(12.5 e-12)
=-----------------------­
= 273 Hz
Electrical, Electronic and Computer Engineering
113
Operational Amplifier Design
Addendum B
The second pole is given by
(B. 23)
It was given that f.1Cox for PMOS and NMOS transistors were 25 j.lAN 2 and 75
j.lAly 2
respectively. From addendum A the gate capacitance is seen to be 1.4 fF / j.lm2 and thus the
2
mobility constants are calculated as f.1e= 536 cm Ns and f.1h = 179 cm 2Ns .
Now,
C1
=
112x3x1.4e-15
(B. 24)
= 470jF
C2
=
28x4x1.4e-15
(B. 25)
= 160jF
P2
= 114.56,uAlV x 12 .5 pF + 470 jF + 160 jFx 12.5 F
470 jFx160 iF
P
(B. 26)
=180.1 MHz
As was mentioned before, the zero introduced by the compensation capacitor does influence
CMOS operational amplifiers, thus:
(B. 27)
=
=
114.56 e-6
12.5 e-12
9.2 MHz
This is not to say that the zero will not affect the stability, as more phase is introduced. To
ensure this will be the case, a compensation resistor will be implemented with the value of
z =
1
(B. 28)
Electrical, Electronic and Computer Engineering
114
Addendum B
Operational Amplifier Design
Choosing Rz > 1/gm2 , will result in moving the zero from the right half plane to the left half
plane close to the second dominant pole, where stability can once again be achieved. Here, the
zero contributes to positive phase shift. Thus choosing Rz = 10H2, results in the zero
frequency to be at approximately 10 MHz. This will also affect the UGBW to move as the
zero now occurs after the uncompensated RHP zero.
Electrical, Electronic and Computer Engineering
115
ADDENDUM C: SYSTEM SCHEMATICS
System Simulation
Rl = 500k
R]
=
500k
R3
55.5k
e - - - - - - - -__-1Vmains
. - - - - - -___--l clk
lout---.p
.--___--1 EN
lout n
V2 = 5 V
Rext Power Sensor
50 Hz
gnd
=
gnd
5
agnd
Figure C.l Schematic illustrating simulation test bench
Figure C.l illustrates the simulation setup used to simulate the sensor. The voltage divider
network can be clearly seen. An external resistor of 50 kQ is used for calibrating the current
bias circuit. The output of the circuit was loaded with a 2 kQ resistance for simpler result
calculations.
116 = 2k
System Schematics
Addendum C
Power Sensor
~ TN<O>
P
T< l >
~ T<O> :~: TN<J>
cJk ••- - - - -____
"'=---~~
lout n
+
~-----~- louty
T<O:l >
TN<O:l >
switches
Vmains
EN
---f---j
Vin~
Yybais l
V pbais2
V nbaisl t~:'-=-":1f-'
Bandgap
Rext
Vpbals2
Bias Generator
Rext
Figure C.2 Schematic of the power sensor system
Figure C.2 shows the entire system schematic of the power sensor. The inputs and outputs are
indicated in figure c.l. The amplifier biasing circuits comprises of the bandgap generator
(figure C.3) and the current reference generator (figure CA). The current reference generator
uses a self-biased amplifier shown in figure C.S. The biasing amplifier (figure C.6) drives the
Electrical, Electronic and Computer Engineering
117
System Schematics
AddendumC
Hall generator via the transmission gate switches (figure e.S). The switches are configured
such that quadrature rotation is implemented on the Hall generator (figure e.9). This amplifier
uses two operational amplifiers shown in figure e.7. The Hall output is low passed filtered
(figure e.lO) and finally amplified by the final output stage (figure e.6). The 4 inverters
generate the clock cycles required by the transmission gates.
Bandgap reference
S2
EN1 m=l
Sl
EN
-----l
Ml
m=2
M3
m=l
S3
E~
m=l
m=2
m=2
EN.-j
EN---1
S4
S5
m=2
Co = 9 pF
Eli1
S6
Vss
Figure C.3 Bandgap reference schematic
Electrical, Electronic and Computer Engineering
118
System Schematics
AddendumC
Current bias generator
MI5
M4 M6
m=2 m=2
M8
m=2
Vpbiasl
m=2
MI4
Yin
Vpbias2
m=2
MO
m=2
M5
MI3
m=1
m=1
Vnbias2
MI2
m=1
Rext
m=1
Vnbiasl
Figure CA Current reference generator
Self biased operational amplifier
M9
m=2
M2
m=2
MI
m=2
M3
m=4
R]=IOk
m=4
~INP
MI2
m=2
M6
m=2
Vout
C 1=12.5p
M8
m=2
Mll
m=2
Figure C.S Operational amplifier used in current reference circuit
Electrical, Electronic and Computer Engineering
119
System Schematics
Addendum C
Instrumentation amplifier
+__----1t----j +
Is
~-----+-- -lout
+
-lout
+i out
___------0>-----1
+
~----+---- +i out
Is
Figure C.6 Instrumentation amplifier
Voltage-to-current converting operational amplifier
M4
m=2
MI
m=2
f---.
I2.5u
lout
VV'----ll...---+---. Vout
C j =I2.5p
V nbias2
r----.
INP
MIO
--------1
M3
Mll
Vnbiasj~
m=2
m=I
Figure C.7 Operational amplifier implemented in instrumentation amplifiers
Electrical, Electronic and Computer Engineering
120
System Schematics
Addendum C
Quadrature rotation switching circuitry
NCH ______ rout
T<O:l > ..,.--T<O>
LT< l >
TN<O:l > ~TN<O>
LTN< l >
Cin .-PCH
INM
•
•
INP
INP
T<l >
T<O>
PCH
INM
NCH
TN<O>
TN< l>
TN<O> TN<l >
TN<l>
T< l>
TN<O>
T<O>
T<O>
PCH
T< l >
T< l >
T<O>
TN<l >
TN<O>
INP
NCH
INM
Figure C.8 Transmission gate switching circuitry
Electrical, Electronic and Computer Engineering
12 1
AddendumC
Hall generator simulation model
I in
Ro=3k
';0 Hz
C.9 Hall generator simulation model
Low
C.lO Passive low-pass filter
122
... .
[J
ADDENDUM D: LAYOUT LEGEND · . ... .. . . . .
... ..
· · ..
... ..
. . .
· . . . . .
·
.
. . . .
· · ..
.. .
.. .. .
· · . ... .. . . . .
·
·
•
N-Well
N-Active
P-Active
Poly 1
Contact
Metal 1
Via
•
Meta12
123