Download Institutionen för systemteknik Department of Electrical Engineering A “Divide-by-Odd Number” Injection-Locked Frequency Divider.

Institutionen för systemteknik
Department of Electrical Engineering
Examensarbete
A “Divide-by-Odd Number” Injection-Locked
Frequency Divider.
Examensarbete utfört i Elektroniska Komponenter
vid Tekniska högskolan vid Linköpings universitet
av
Malik Summair Asghar
LiTH-ISY-EX--13/4653--SE
Linköping 2012
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Linköpings tekniska högskola
Linköpings universitet
581 83 Linköping
A “Divide-by-Odd Number” Injection-Locked
Frequency Divider.
Examensarbete utfört i Elektroniska Komponenter
vid Tekniska högskolan i Linköping
av
Malik Summair Asghar
LiTH-ISY-EX--13/4653--SE
Handledare:
Prof. Michael Peter Kennedy, FIEEE
Electrical and Electronic Engineering, University College Cork
Examinator:
Prof. Atila Alvandpour
isy, Linköpings universitet
Linköping, 15 December, 2012
Avdelning, Institution
Division, Department
Datum
Date
Division of Electronic Devices
Department of Electrical Engineering
Linköpings universitet
SE-581 83 Linköping, Sweden
Språk
Language
Rapporttyp
Report category
ISBN
Svenska/Swedish
Licentiatavhandling
ISRN
Engelska/English
Examensarbete
C-uppsats
D-uppsats
Övrig rapport
2012-12-15
—
LiTH-ISY-EX--13/4653--SE
Serietitel och serienummer ISSN
Title of series, numbering
—
URL för elektronisk version
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-88014
http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-88014
Titel
Title
A “Divide-by-Odd Number” Injection-Locked Frequency Divider.
Författare Malik Summair Asghar
Author
Sammanfattning
Abstract
The use of resonant CMOS frequency dividers with direct injection in frequency
synthesizers has increased in recent years due to their lower power consumption
compared to conventional digital prescalers. The theoretical and experimental
aspects of these dividers have received great attention. This masters thesis work
is a continuation of earlier work, based on the fundamentals of Injection-Locked
Frequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection is wellknown for its divide-by-2 capability. However, it does not divide well by odd
numbers. The goal of this master thesis work is to modify the LC CMOS ILFD
with direct injection so that it can divide equally well by odd and even integers.
In this master thesis report, an introduction to the basic concepts behind
Injection-Locked frequency dividers is first presented. Some of the previous work
and the background of a reference LC CMOS ILFD design are studied. The author,
studied the reference design, and the experimental setup used for characterizing
it’s locking behavior. The algorithm used to characterize the locking behavior of
this ILFD are explored to reproduce the results for divide-by-even numbers for the
existing ILFD topology. Using a Spice model these results are also reproduced in
simulations.
Over the years, numerous ILFD circuit topologies have been proposed, most of
which have been optimized for division by even numbers, especially divide-by-2.
It has been more difficult to realize division by odd numbers, such as divide-by-3.
This master thesis work develops a simple modification to an LC CMOS injection
locked frequency divider (ILFD) with direct injection, which gives it a wide locking
range both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequency
division by an odd number. The work presents the circuit architecture, SPICE
simulations and experimental validation.
Nyckelord
Keywords
Injection-Locked Frequency divider (ILFD), Phase Locked Loop(PLL), Frequency
divider (FD)
Abstract
The use of resonant CMOS frequency dividers with direct injection in frequency synthesizers has increased in recent years due to their lower power consumption compared to conventional digital prescalers. The theoretical and experimental aspects of these dividers have received great attention. This masters thesis
work is a continuation of earlier work, based on the fundamentals of InjectionLocked Frequency Dividers (ILFD’s). The LC CMOS ILFD with direct injection
is well-known for its divide-by-2 capability. However, it does not divide well by odd
numbers. The goal of this master thesis work is to modify the LC CMOS ILFD
with direct injection so that it can divide equally well by odd and even integers.
In this master thesis report, an introduction to the basic concepts behind
Injection-Locked frequency dividers is first presented. Some of the previous work
and the background of a reference LC CMOS ILFD design are studied. The author,
studied the reference design, and the experimental setup used for characterizing
it’s locking behavior. The algorithm used to characterize the locking behavior of
this ILFD are explored to reproduce the results for divide-by-even numbers for the
existing ILFD topology. Using a Spice model these results are also reproduced in
simulations.
Over the years, numerous ILFD circuit topologies have been proposed, most
of which have been optimized for division by even numbers, especially divide-by-2.
It has been more difficult to realize division by odd numbers, such as divide-by-3.
This master thesis work develops a simple modification to an LC CMOS injection
locked frequency divider (ILFD) with direct injection, which gives it a wide locking
range both in the “divide-by-odd number” mode and in the conventional “divideby-even number” regime, thereby opening up applications which require frequency
division by an odd number. The work presents the circuit architecture, SPICE
simulations and experimental validation.
v
Acknowledgments
First of all I would like to thank Almighty Allah,who gave me strength and
knowledge to carry out my masters degree and thesis work. I would like to thank
my parents and family who were always there to provide me with moral support
and gave me the confidence to accomplish my study tasks.
Secondly, I would like to pay my deepest gratitude to my respected supervisor Prof. Michael Peter Kennedy for providing me with the opportunity to work
on this project. I feel very blessed to work under his dynamic and encouraging
supervision. He is a man of responsibility, divergent knowledge, sharp thinking
ability, producing multiple solutions and having excellent leading skills. His guidelines and knowledge not only helped me with this project but will also remain as
a useful asset for my future life, educational and professional career.
Further more, I would like to thank my examiner Prof.Atila Alvandpour and
my University, Linköping University, for providing me with the opportunity to
do my master thesis as an ERASMUS exchange student and also for helping me
out in all administrative issues. I would also like to thank University College
Cork Ireland and Tyndall National Institute for providing me with this valuable
opportunity to study in Ireland.
Lastly, I would like to thank my classmate M.A.Awan and two UCC students
Huiyuan Xing and Xi Wu for their initial guidelines and support for this project.
Here, I would like to mention my gratitude for the cooperation and support provided by the MCCI team in Tyndall for the cadence support. This work was
supported in part by Science Foundation Ireland under grant 08/IN.1/I854 and
by the European Commission under the ERASMUS program.
I hope this work will be a stepping stone for all researchers and future work
in the field of Injection-Locked Frequency Dividers.
vii
Contents
1 Introduction
1.1 PLL Synthesizer and ILFD . . . . . . . . . . . . . . . . . . . . . .
1.2 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Background and Previous Work
2.1 LC CMOS Injection Locked Frequency Dividers
2.1.1 LC CMOS ILFD With Tail Injection . .
2.1.2 LC CMOS ILFD with Direct injection .
2.2 Arnold Tongue Scenario . . . . . . . . . . . . .
2.3 Devil’s staircase . . . . . . . . . . . . . . . . . .
2.4 Brute Force Method . . . . . . . . . . . . . . .
2.5 Previous work . . . . . . . . . . . . . . . . . . .
2.5.1 Divide by even number . . . . . . . . .
2.5.1.1 Experimental Characterization
2.5.1.2 Measurement Setup . . . . . .
2.5.2 LabVIEW Algorithms . . . . . . . . . .
2.5.3 Experimental Results . . . . . . . . . .
2.5.3.1 Frequency Sweeping Results .
2.5.3.2 Boundry Following Results . .
2.5.3.3 Boundry Finding Results . . .
2.5.4 Analysis . . . . . . . . . . . . . . . . . .
3 Divide-by-Odd Number
3.1 Developed Model . . . . . . . . . . .
3.2 Experimental Characterization . . .
3.2.1 ILFD on Bread-Board . . . .
3.2.2 Components and Parameters
3.2.3 Differential Signal . . . . . .
3.2.4 Measurement Setup . . . . .
3.2.5 Algorithms . . . . . . . . . .
3.2.6 Experimental Results . . . .
3.3 Symmetric Circuit . . . . . . . . . .
3.3.1 Components and Parameters
ix
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
7
7
9
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
13
13
14
15
16
18
19
19
21
21
22
23
24
24
25
25
26
.
.
.
.
.
.
.
.
.
.
29
29
31
31
32
34
35
36
36
37
37
x
Contents
3.4
3.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . .
Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
38
39
4 Modeling and Simulations
4.1 Modeling and Spice Simulations . . . . . . . . . .
4.1.1 Spice Model . . . . . . . . . . . . . . . . .
4.1.2 MOSFET Models . . . . . . . . . . . . . .
4.1.3 SPICE Runtime Algorithm . . . . . . . .
4.1.4 MATLAB Post-processing Algorithm . . .
4.1.5 SPICE and MATLAB Simulations Results
4.2 Symmetric Circuit . . . . . . . . . . . . . . . . .
4.2.1 Spice Model . . . . . . . . . . . . . . . . .
4.2.2 SPICE and MATLAB Simulations Results
4.3 Analysis . . . . . . . . . . . . . . . . . . . . . . .
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
41
41
42
43
43
43
45
46
47
47
48
5 Conclusion and Future Work
5.1 Conclusion . . . . . . . . . . . . .
5.2 Limitations . . . . . . . . . . . . .
5.3 Future Work . . . . . . . . . . . .
5.3.1 Analytical Model . . . . . .
5.3.2 Monolithic Implementation
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
49
49
50
51
51
51
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
Bibliography
53
A LabVIEW Algorithms
A.1 Frequency Sweeping . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Boundary Following . . . . . . . . . . . . . . . . . . . . . . . . . .
A.3 Boundary Finding . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
57
60
63
B Matlab Post-Processing Code
B.1 Frequency Sweeping . . . . . . . . . . . . . . . . . . . . . . . . . .
B.2 Boundary Following . . . . . . . . . . . . . . . . . . . . . . . . . .
B.3 Boundary Finding . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
70
72
73
C Spice Netlist and Matlab Code
C.1 Spice Netlist . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C.2 Spice Netlist for Symmetric Circuit . . . . . . . . . . . . . . . . . .
C.3 Matlab Post-Processing Code . . . . . . . . . . . . . . . . . . . . .
75
75
76
78
List of Figures
1.1
1.2
A simple frequency synthesizer comprised of a PLL. . . . . . . . .
Jang et al. [26] use a CMOS LC oscillator circuit with multiple
inductors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
2.2
2.3
LC CMOS ILFD With Tail Injection. . . . . . . . . . . . . . . . .
LC CMOS ILFD With Direct Injection. . . . . . . . . . . . . . . .
The bifurcation diagram explaining the locking behavior and the
Arnold tongues . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 LC CMOS ILFD With Direct Injection. . . . . . . . . . . . . . . .
2.5 Devil’s staircase diagram showing wide steps for ρ=2,4,6,8 and narrow steps for ρ=3,5,7. . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Tiebout’s classical direct injection-locked oscillator topology [19]. .
2.7 Measured locking regions in the LC CMOS ILFD with direct injection for ρ=2, 4 and 6 [30]. . . . . . . . . . . . . . . . . . . . . . . .
2.8 LC CMOS ILFD With Direct Injection on Breadboard. . . . . . .
2.9 Measurement Setup. . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Experimental results forthe Frequency Sweeping algorithm applied
to the LC CMOS ILFD with direct injection in Fig. 2.2 . . . . . . .
2.11 Experimental results for the Boundary following algorithm showing
locking regions corresponding to ρ=2, 3, 4, 5, 6 and 7. . . . . . . .
2.12 Experimental results for the boundary finding algorithm showing
locking regions coressponding to ρ=2, 3, 4, 5, 6 and 7. . . . . . . .
8
10
14
15
17
17
18
19
20
22
23
24
25
26
3.1
Modified LC CMOS ILFD with direct injection for Divide-by-Odd
number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.2 ILFD implementation On bread-board. . . . . . . . . . . . . . . . . 31
3.3 Pin assignment of CD4007UBE. . . . . . . . . . . . . . . . . . . . . 32
3.4 RC network for combining Vac and Vdc . . . . . . . . . . . . . . . . 33
3.5 Instrumentation Amplifier for getting differential output. . . . . . . 34
3.6 Pin assignment of LT1229 Instrumentation Amplifier. . . . . . . . 35
3.7 Measurement Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.8 Experimentally measured Arnold tongues corresponding to ρ =2,3,4,5,6
and 7 in the modified circuit of Fig. 3.1 . . . . . . . . . . . . . . . . 37
3.9 Symmetric Circuit of the ILFD with direct injection. . . . . . . . . 38
3.10 Experimental Results for the Symmetric Circuit of the ILFD with
direct injection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
4.1
4.2
4.3
4.4
4.5
H-Spice Circuit schematic of the developed Divide-by-Odd ILFD. .
Spice model for MOS transistors in Figure. 4.1 with zero threshold
modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spice Output ASCII data file presented to Matlab. . . . . . . . . .
Spice simulation results for divide-by-2 and divide-by-3 locking regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Spice simulation results for divide-by-2 and divide-by-3 locking regions without parasitic impedance networks. . . . . . . . . . . . . .
42
43
44
46
46
2
Contents
4.6
4.7
A.1
A.2
A.3
A.4
H-Spice Circuit schematic of the Symmetric Circuit. . . . . . . . .
Spice simulation results for divide-by-2 and divide-by-3 locking regions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Block diagram of the frequency sweeping algorithm. . . . . . . . .
Control panel of the Frequency Sweeping algorithm. . . . . . . . .
Measurement of tongues in Boundary following algorithm. . . . . .
Concept behind finding a boundary point in Boundary following
algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.5 Control panel of boundary finding algorithm. . . . . . . . . . . . .
A.6 The half interval search method concept for the boundary finding
algorithm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.7 Measurement of tongues using the boundary finding algorithm. . .
A.8 Flow chart for the Main Process of the Boundary-Finding Algorithm
Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.9 Flow chart for the left boundary of the Boundary-Finding Algorithm.
A.10 Flow chart for the right boundary of the Boundary-Finding Algorithm.
47
48
58
58
60
62
64
65
66
67
68
69
Contents
3
List of Tables
2.1
Component values of the LC Tank . . . . . . . . . . . . . . . . . .
22
3.1
3.2
Component values of the LC Tank . . . . . . . . . . . . . . . . . .
Component values of the RC Network . . . . . . . . . . . . . . . .
32
34
4
Contents
List of Abbreviations
ILFD
Injection-Locked frequency divider
VCO
Voltage Controlled Oscillator
PLL
Phase Locked Loop
FD
Frequency Divider
FS
Frequency Synthesizer
PD
Phase Detector
LPF
Low Pass Filter
CML
Common Mode Logic
LR
Locking Range
IA
Instrumentation Amplifier
VISA
Virtual Instrument Software Architecture
GPIB
General Purpose Interface Bus
PC
Personal Computer
TSMC Taiwan Semiconductor Manufacturing Company
KHz
kilohertz
GHz
Gigahertz
RF
Radio Frequency
MHz
Megahertz
nf
nanofarad
pf
picofarad
Contents
OpAmp Operational Amplifier
IC
Integrated Circuit
CMOS Complementary Metal Oxide Semiconductor
mW
milliwatts
5
Chapter 1
Introduction
This chapter provides a brief introduction to the project and the context. Section 1.1 provides a brief introduction to applications of PLL based frequency synthesizers while Section 1.2 talks about the objectives of this project, highlighting
some of the previous and current work in the field of ILFD’s.
1.1
PLL Synthesizer and ILFD
A frequency synthesizer is an electronic system for generating a range of frequencies. Frequency dividers (FD) are widely used as building blocks in the implementation of Phase Locked Loops (PLL) based frequency synthesizers for both
wireless and wire line communications [1]. The power consumption of the divider
is an important consideration when it is integrated into a complete system, particularly in the case of portable communication devices. Nowadays, these have a lot
of applications such as GPS systems, radio receivers, radio telephones, mobile telephones satellite receivers, etc. Frequency synthesizers are capable of generating a
required output signal by combining frequency division, frequency multiplication,
and frequency mixing operations. Phase-locked loop based synthesizers are widely
used in current wireless applications.
A phase locked loop (PLL) is a feedback control system. A phase detector
(PD) compares the phases of its two input signals and, depending on the difference between them, it generates a proportional error signal.The error signal then
goes through a low pass filter and afterwards is used as a control voltage for a
voltage-controlled oscillator (VCO) which generates an output signal frequency.
7
8
Introduction
The output signal frequency is then fed back to the phase detector through a
frequency divider, producing a negative feedback loop [2].
Figure 1.1: A simple frequency synthesizer comprised of a PLL.
A simple frequency synthesizer comprised of a PLL is shown in Fig. 1.1.
It contains a phase detector (PD), a low-pass filter (LPF), a voltage-controlled
oscillator (VCO), and a frequency divider (FD) [3]. The output signal frequency
fout is divided to a lower frequency fdiv which is then locked to the phase of a fixed
reference signal with frequency fref . As can be seen from Fig. 1.1, the frequency
divider comprises two sub blocks. One is called a prescaler; it divides by a fixed
number Np . The second one is a programmable divider which divides by a rational
number Nv /M , where Nv and M are positive integers. When the loop is in the
lockes condition, then
Fout =
N
Fref .
M
(1.1)
where N =Np Nv . If M =1, the synthesizer is called an integer-N synthesizer.
Otherwise, if M 6= 1, the synthesizer is called a fractional-N synthesizer. The role
of the prescaler is to divide the output frequency by a positive integer and to pass
this signal to a programmable divider [4]. The prescaler is the focus of the master
thesis work carried out in this project.
An Injection-Locked Frequency Divider (ILFD) is capable of dividing an input
injection signal with a high frequency to produce an output signal with a lower
frequency with a fixed frequency ratio between the injected input signal frequency
and the output signal frequency.
1.2 Objectives
9
The key parameters of an ILFD are:
1. The rotation number ρ: This is the ratio of the input signal frequency to the
output signal frequency.
2. The locking range (LR): For a given rotation number ρ, the range of the
input signal frequency over which the output signal frequency is rationally
locked to the input signal frequency is called the locking range.
3. Phase Noise: The circuit noise can disturb the oscillator’s output phase.
Generally, all oscillators possess an amplitude-limiting phenomenon so, at
the output of the oscillator, phase noise dominates [5].
1.2
Objectives
The use of digital frequency dividers is constrained at high frequencies by their
high power consumption which increases rapidly with frequency [6]. As an alternative, analog frequency dividers have lower power consumption and high speed
and frequency capabilities [7]. FDs can be realized using Common Mode Logic
(CML) [8], [9], dynamic logic [10], Miller dividers [11] and Injection Locked Frequency Dividers (ILFD) [12]. Compared to CML and Miller dividers, the power
consumption of an ILFD does not increase significantly with frequency.
An ILFD is an electronic oscillator which produces an output signal whose
period (equivalently, zero-crossing rate) is rationally related to that of the input
signal [13]. When there is no injected input signal, the oscillator oscillates with a
free-running frequency f0 . When an injection signal Vi is applied with a frequency
fs , then the output signal Vo oscillates with a frequency fd . The ratio of fs /fd
is called the rotation number, denoted by ρ [14]. This locking behavior is due to
the nonlinear phenomenon of synchronization, also known as entrainment or 1 : m
order injection locking [15]–[17].
The advantage of the ILFD is that it has the potential for low power operation
because the relatively small perturbation by the input signal does not significantly
affect the power consumption of the underlying oscillator [18]. However, ILFDs
have two major drawbacks. Firstly, they are poorly understood from a theoretical
point of view, despite a long history of research and significant progress since
the advent of computational nonlinear dynamics [16, 17]. Secondly, the ILFD is
bandpass in nature, meaning that it divides correctly only over a small range of
frequencies. This is related to the entrainment phenomenon; the oscillator locks
to the perturbing input signal with the correct frequency division ratio ρ only over
a limited range of frequencies, the so-called Locking Range (LR).
10
Introduction
Circuit topologies which realize frequency division by even numbers, e.g.divideby-2 prescalers, have been studied extensively in the literature [19]–[25]. In order
to avoid pulling in transceivers, there is a demand from frequency planners for
division by numbers other than two, and in particular, division by odd numbers.
In recent years, frequency division by odd numbers, particularly divide-by-3, has
received increasing attention.
Jang et al. [26] and Lee et al. [27] use CMOS LC oscillator circuits with
multiple inductors. In the circuit schematic shown in Fig. 1.2, the drain current Id
of the MOS M 5 at which the injection voltage Vi is applied contains odd harmonic
frequency components at ωo and 3ωo [26]. The third harmonic component of the
current at 3ω0 sees a higher impedance load composed of two inductors than the
fundamental drain current harmonic component at ω0 . The third harmonic of
the MOS M 5 drain voltage is fed back to the gate of the MOS M 5 through a
parasitic gate-drain capacitor, so that the gate voltage of MOS M 5 has a thirdorder harmonic component. This, in turn, allows the circuit to realize a divide-by-3
locked signal. Most of the chip area and power are consumed by the inductors.
Consequently, this circuits occupies a large chip area due to multiple inductors
and also has a large power consumption.
Figure 1.2: Jang et al. [26] use a CMOS LC oscillator circuit with multiple inductors.
The main objective of this master thesis is to study an existing topology of
LC CMOS ILFD, and specifically to modify it so that it has wide locking regions
1.2 Objectives
11
with odd rotation numbers. In this thesis, we propose a simpler circuit, also
based on a CMOS LC oscillator, but with a single inductor. We describe the
conventional divide-by-2 oscillator on which this work is based and the method
which we have used to characterize its locking behavior. Furthermore, we introduce
our modification to the CMOS LC oscillator with direct injection which makes it
suitable for division-by-odd numbers.
Chapter 2
Background and Previous
Work
This chapter presents background information about ILFDs by explaining the
existing topologies and exploring previous work done in this field.
Section 2.1.1 describes the classical topology of an ILFD with tail injection
while Section 2.1.2 talks about the improved technique of an ILFD with direct injection. Section 2.2 discusses bifurcation theory and the Arnold’s tongues scenario
of locking regions. Section 2.3 describes the method of the devil’s staircase for
characterizing rotation numbers. Section 2.4 explains the brute force method for
finding the boundaries of Arnold tongues. Section 2.5 gives an overview of various
research results in the field of ILFDs prior to this work.
2.1
LC CMOS Injection Locked Frequency Dividers
An injection-locked frequency divider (ILFD) is an oscillator to which a periodic
input is applied.This input signal is regarded as the injection signal. ILFDs are
generally categorized into two basic topologies: One is indirect injection through
the tail and the other is direct injection.
13
14
2.1.1
Background and Previous Work
LC CMOS ILFD With Tail Injection
These days, a widely used LC CMOS differential injection-locked oscillator topology is the LC CMOS ILFD with tail injection [19]. The circuit diagram of an LC
CMOS ILFD with tail injection is shown in Fig. 2.1.
Vi
Vin
M5
Figure 2.1: LC CMOS ILFD With Tail Injection.
The main disadvantages of this classical topology is its large input capacitance
and its small input locking range.Furthermore, the single-ended input is considered
to have less advantages when a VCO and divider are integrated on chip.The small
locking range of the LC CMOS with tail injection is due to the inefficient injection
path through the tail transistor M 5. The injected current of M 5 vanishes into the
capacitance of the tail node when we operate at higher frequencies. Similarly, an
other disadvantage of this classical topology is that M 5 should have a large width
in order to provide the input transconductance and tail DC current. Replacing
the tail transistor (M 5) with an N P N transistor could give the benefit of higher
transconductance. In order to avoid these problems, an LC CMOS ILFD with
direct injection has been developed [19].
2.1 LC CMOS Injection Locked Frequency Dividers
2.1.2
15
LC CMOS ILFD with Direct injection
We consider a direct injection locked frequency divider (ILFD) in this thesis. The
circuit diagram of the LC CMOS ILFD under consideration is shown in Fig. 2.2.
Vi
Figure 2.2: LC CMOS ILFD With Direct Injection.
This LC CMOS ILFD comprises an oscillator and an additional transistor.
The oscillator comprises an LC tank and four transistors (M 1-M 4). The LC tank
has a capacitor in parallel with a series combination of an inductor and a resistor.
The four transistors M1 to M4 include two PMOS transistors and two NMOS
transistors.The four transistors M 1 to M 4 work as a negative resistance network.
The additional transistor M 5 is an NMOS transistor and is used to couple the
injected signal to the LC tank. When no injection signal is applied to M5, the
circuit oscillates with an unforced frequency fo which is also known as the natural
frequency. When we drive our circuit with an injected input signal Vi at frequency
fs then the output signal Vo acquires the frequency fd . The ratio of the input
signal frequency fs to the output signal frequency fd , namely fs /fd is called the
rotation number, denoted by ρ. Under appropriate conditions, the output signal
16
Background and Previous Work
locks to the injected signal in such a way that the frequency of the input signal is
an integer multiple of the frequency of the output signal.
This improved topology with direct injection overcomes the drawbacks of the
classical tail injection topology.The injected signal is provided directly through
M 5, which can be designed much smaller than the tail transistor due to the more
efficient injection scheme. The transistor M 5 acts as a switch which can be realized
by an NMOS transistor or a PMOS transistor [19].
2.2
Arnold Tongue Scenario
Nonlinear dynamics provides a paradigm for frequency entrainment (injection locking), namely the so-called standard circle map or sine map [28]. Consider a first
(dependent) oscillator with an unforced frequency f0 that is driven by a second
(independent) oscillator with frequency fs . If the phase θ of the first oscillator is
sampled at the frequency of the second oscillator, then samples are described by
a discrete time dynamical system of the form
θ[n + 1] = θ[n] + Ω −
k
sin(2πθ[n]),
2π
(2.1)
where Ω= f0 /fs is the ratio of the unforced and injected signals and k is
the strength of the coupling.The behavior of this system is summarized in a two
dimensional bifurcation diagram, as shown in Fig. 2.3. The bifurcation diagram
is organized into regions called Arnold tongues; inside each tongue, the rotation
number is constant.
The abscissa (horizontal axis) in Fig. 2.3 shows the relative frequency of the
injected signal and the ordinate (vertical axis) k is the strength of the coupling
between the input signal and the oscillator. θ is the phase of the first oscillator.
The bifurcation diagram is organized into regions called Arnold tongues; the rotation number ρ is constant inside each tongue.The bifurcation diagram in Fig. 2.3
shows Arnold tongues corresponding to rotation number 5/1, 4/1, 3/1, etc. [28].
In this work, we use a similar way to present the locking range for different
constant rotation numbers, as shown in Fig. 2.4.
The main idea behind the synchronization of an oscillator and the applied
input injected signal can be analyzed in terms of the locking regions which have
a typical V-shape called Arnold tongues.The locking behavior is due to the nonlinear phenomenon of synchronization. Fig. 2.4 shows locking regions in a typical
2.2 Arnold Tongue Scenario
17
Figure 2.3: The bifurcation diagram explaining the locking behavior and the
Arnold tongues .
Figure 2.4: LC CMOS ILFD With Direct Injection.
LC CMOS oscillator. The abscissa is the ratio fs /fd , the normalized injection
frequency. The ordinate is A, the amplitude if the injected signal. The triangular
regions in Fig. 2.4 are called Arnold tongues.These correspond to the ranges of
the input frequency over which the division ratio ρ is constant.The width of a
tongue at a given input amplitude A is known as Locking range (LR). For a given
rotation number ρ, there is a unique tongue which has a left boundary and a right
18
Background and Previous Work
boundary.The input frequency where these two boundaries meet is known as the
center√frequency. For every given rotation number ρ, the center frequency
is given
√
by ρ/ LC. For example, for ρ=2 the center frequency would be 2/ LC. These
locking regions can be determined accurately by a variety of algorithms which we
will discuss in Sec. 2.5.2.
2.3
Devil’s staircase
There is another simple and useful method to characterize the bifurcation diagram.
It is known as the Devil’s staircase. The devil’s staircase is a monotonically increasing function of fs with horizontal levels of finite width at each rational value
of ρ. We can plot the Devil’s staircase by keeping the value of A fixed and taking
a cross section through the bifurcation diagram. As can be seen in Fig. 2.5, the
horizontal steps correspond to the different tongues. In each horizontal step of the
devil’s staircase plot, the ratio ρ is constant [28].
Figure 2.5: Devil’s staircase diagram showing wide steps for ρ=2,4,6,8 and narrow
steps for ρ=3,5,7.
For large values of A, there is overlap between the different tongues. In this
region, the devil’s staircase can be useful to determine whether the tongues overlap
or not. The overlapping of tongues corresponding to different rotation numbers
2.4 Brute Force Method
19
leads to hysteresis effects and chaos [29].
2.4
Brute Force Method
The brute force method is another useful method, and it is the basis of the numerical method described in Sec. 2.5.2, for determining the ranges of the different locking regions of the ILFD. The brute force method calculates the rotation number
on a grid of points which correspond to fixed values of frequency and amplitude.
The distance between two consecutive measurement points is predefined and is
known as the step size. The locking regions of the ILFD can be determined by
calculating the ratio ρ at each point.The interval from the start boundary point
to the end boundary point is known as the locking range for a specific rotation
number. One of the major drawback of this method is the time required to find
the locking regions for different rotation numbers. Also, it does not provide any
information regarding the shapes of the Arnold tongues [29].
2.5
Previous work
Marc Tiebout [19] was the first to describe the CMOS Direct Injection-Locked frequency divider. In his paper [19], the author presented a novel circuit topology for
ILFD’s to achieve a wider locking range, and experimentally verified the features.
The classical Injection-locked frequency divider with direct injection topology by
Tiebout is shown in Fig. 2.6.
Figure 2.6: Tiebout’s classical direct injection-locked oscillator topology [19].
20
Background and Previous Work
Daneshgar, et al. [3], [20], used bifurcation theory and presented a nonlinear
approach to predict the widths of locking regions. They presented a nonlinear
approach based on the applications of bifurcation theory to predict where the
locking range is wider. Daneshgar supported his approach by simulations and
experimental verification of the circuit ILFD.
Daneshgar, et al. [3], [20], focused their research experiments and simulation
on the injection locked frequency diver with tail injection. They did not publish
much on the injection locked frequency divider with direct injection.
Kennedy, et al. [30] carried on the next phase of this research. They reported
a phenomenological study of the LC CMOS Injection Locked frequency divider
with direct injection. In their work, they considered the effects of various factors
on the locking behavior. These factors include the amplitude of the injected signal,
the harmonic components of the injected signal, the size of the switching transistor, and the DC component of the switching transistor. They also presented a new
algorithm for determining the boundary points of the locking regions for characterizing the ILFD behavior [4]. In their work, they analyzed the locking regions
(Arnold’s tongues). The measured Arnold’s tongues produced in this paper [30]
are shown in Fig. 2.7.
Figure 2.7: Measured locking regions in the LC CMOS ILFD with direct injection
for ρ=2, 4 and 6 [30].
The measured Arnold Tongues can be separated into 3 regions. Region 1 corresponds to the low amplitude forcing regime, which is modeled well by the classical Arnold tongue paradigm. Region 2 shows some evidence of overlap. Here, the
width of the divide-by-2 tongue grows rapidly with increasing amplitude, and the
divide-by-4 tongue bends away to make room for it. In Region 3, the tongues are
2.5 Previous work
21
again distinct. Their widths remain almost constant with the increasing amplitude
of the perturbation signal. This region has been called a saturation region [30].
2.5.1
Divide by even number
In this section, we will discuss the divide-by-even number ILFD, which has been
under consideration in previous work. We will describe the experimental characterization of the ILFD under test. Furthermore, we explain the circuit implementation and the measurement setup used for the experiments. We will briefly give
a description about the algorithms used for the experimental characterization of
the locking regions for the ILFD under test. In the end, we will reproduce the previous experimentally measured results for the circuit under test by using various
algorithms and analyze these results.
2.5.1.1
Experimental Characterization
Beyond the theory of the Injection locked frequency divider, an experimental characterization of different topologies of ILFD’s is necessary. In this section, we will
explain and physically realize the circuit topology of the ILFD which has been
under consideration in previous research work.
The circuit under test is the LC CMOS ILFD with direct injection, as shown
in Fig. 2.2.
To get started with the experimental characterization of the ILFD under
test we built a physical prototype of the circuit with discrete components on a
breadboard. The breadboard implementation of the LC CMOS ILFD with direct
injection is shown in Fig. 2.8.
In our design, we use Texas Instruments CD4007UBE CMOS DUAL COMPLEMENTARY PAIR PLUS INVERTER for the implementation of the five transistors (M 1-M 5). The CD4007UBE comprises three PMOS transistors and three
NMOS transistors.
In the circuit implementation on the breadboard, two CD4007UBE chips are
used. On the first chip, two PMOS transistors (M1 and M2) and two NMOS
transistors (M3 and M4) form the core of the ILFD.These two cross-coupled pairs
of CMOS inverters act as a negative resistance. On the second CD4007UBE
chip the fifth NMOS transistor M 5 is implemented which acts as an input switch
through which the injected signal is coupled. M 5 is implemented on another chip
because when it is required to increase the size of the NMOS transistor, it can be
22
Background and Previous Work
Figure 2.8: LC CMOS ILFD With Direct Injection on Breadboard.
done by using NMOS transistors available on the second chip. It is implemented
by connecting three NMOS transistors in parallel.The input transistor M 5 couples
the injection signal Vi through an RC bias network. The values of the components
of the LC tank are shown in the Table 2.1. These values were used in previous
research [30] and are used in this work also.
Component
Resistor R
Capacitor C
Inductor L
Value
235
57
1246
Units
Ω
pF
µH
Table 2.1: Component values of the LC Tank
The circuit is powered by two DC power supplies. One power supply provides
9V DC as V DD while the other power supply provides the DC bias component
for the injected input signal. The latter can produce an offset ranging from 0V to
9V DC.
2.5.1.2
Measurement Setup
The experimental set-up in the laboratory is shown in Fig. 2.9
2.5 Previous work
23
Figure 2.9: Measurement Setup.
In the measurement setup, we are using an Agilent 33250A function generator to provide the sinusoidal component of the injected signal. The generator is
controlled by the computer, which is used to set the frequency fs and amplitude A
of the input sinusoidal signal. The ILFD under test is labeled Nonlinear Oscillator
in Figure 3.7. We are using an Agilent 53132A universal counter to calculate the
ratio between the frequencies of the input signal and the output signal and also
determining the boundary points of the locking regions. We observe the input
and output signals using a Tektronix TDS3034B oscilloscope. We connect a PC
to the instruments with GPIB cables. The instrument control, data acquisition,
and processing algorithms are programmed using LabView. The acquired data is
then post-processed using Matlab to calculate the Arnold tongues corresponding
to different locking regions
2.5.2
LabVIEW Algorithms
LabVIEW is the abbreviation for Laboratory Virtual Instrumentation Engineering
Workbench. LabView is a system design platform which makes use of a visual programming language. LabVIEW can perform a variety of tasks such as instrument
control, data acquisition, and industrial automation. Over the years, a number
of different methods and tools have been used by researchers to characterize the
locking behavior of ILFD’s. Some of these were explained briefly in the previous sections. To analyze and measure the characteristics and locking behavior of
ILFD’s over large amplitude and frequency ranges, an efficient LabVIEW algorithm should be used. There are three LabVIEW algorithms which the author
studied and analyzed for finding the boundary points and the characteristics of
the locking behavior of the ILFD under test. These are;
1. Frequency Sweeping
2. Boundary Following
24
Background and Previous Work
3. Boundary Finding.
In the Appendix A, a brief description of all the three LabView algorithms
is given for the understanding of the reader.
2.5.3
Experimental Results
In the previous section three LabVIEW algorithms were mentioned. In this section,
we present results for these algorithms when applied to the LC CMOS ILFD with
direct injection shown in Fig. 2.2. The results are produced for the different divide
ratios by post processing using Matlab.
2.5.3.1
Frequency Sweeping Results
Experimentally measured results plotted using the frequency sweeping algorithm
are shown in the Fig. 2.10. The frequency interval is 5 kHz and amplitude interval
is 0.1V . The injection input signal has a DC bias of 6.03V and is applied to
the input transistor M 5 with single length and single width. From the plot, it
is clear that the divide-by-even regions are wider and the divide-by-odd regions
are narrower. The divide-by-3 region disappears when the amplitude is above 3V .
Therefore, the LC CMOS ILFD with direct injection under test can divide by even
division ratios but is not good at dividing by odd numbers. The Matlab code used
for post processing the acquired data is shown in Appendix B.
Figure 2.10: Experimental results forthe Frequency Sweeping algorithm applied
to the LC CMOS ILFD with direct injection in Fig. 2.2 .
2.5 Previous work
2.5.3.2
25
Boundry Following Results
The experimentally measured results using the Boundary following algorithm are
shown in Fig. 2.11. The plot exhibits similar tongues to the frequency sweeping
algorithm as expected. The divide-by-even locking regions are wide and the divideby-odd locking regions are very narrow. The Matlab code used for post processing
is shown in Appendix B.
Figure 2.11: Experimental results for the Boundary following algorithm showing
locking regions corresponding to ρ=2, 3, 4, 5, 6 and 7.
2.5.3.3
Boundry Finding Results
The experimentally measured results using the boundary finding algorithm are
shown in Fig. 2.12. From the plot it can be seen that the divide-by-even number locking regions are much wider than the divide-by-odd locking regions. The
tongues becomes almost vertical when the injected input signal amplitude is larger
than 3.5 V . The Matlab code used for post processing is shown in Appendix B.
26
Background and Previous Work
Figure 2.12: Experimental results for the boundary finding algorithm showing
locking regions coressponding to ρ=2, 3, 4, 5, 6 and 7.
2.5.4
Analysis
In previous section, we presented experimental measured results from the three
labVIEW algorithms showing the locking behavior of the LC CMOS ILFD with
direct Injection. From the three sets of results, it can be seen that the division
ratios ρ=2,4,6,8 (divide-by-even) have wide locking ranges. The division ratios
ρ=3,5,7 (divide-by-odd) are very narrow and disappear with increasing input signal
amplitude. Moreover the Divide-by-2 and divide-by-4 locking regions for the LC
CMOS ILFD with direct injection are wider then the LC CMOS ILFD with tail
injection [4]. Furthermore, the slopes of the boundaries of the divide regions
increase and become almost verticall when the injected input amplitude goes above
3.5 V . This phenomenon was first observed experimentally and reported in [4] and
has been reproduced by the author.
From the experimentally measured results, it can be concluded that the device
under test, the LC CMOS ILFD with direct injection shown in Fig. 2.2, can divide
2.5 Previous work
27
by ρ=2,4,6,8 very well. But it is not as effective at dividing by ρ=3,5,7. This
motivates the design of a variant of this circuit which will advance the state of the
art by being able to divide as effectively by odd numbers as by even ones.
Chapter 3
Divide-by-Odd Number
The use of resonant CMOS frequency dividers with direct injection in frequency
synthesizers has increased in recent years due to their lower power consumption
compared to conventional digital prescalers. Numerous circuit topologies have
been proposed, most of which have been optimized for division by even numbers,
especially divide-by-2. It has been more difficult to realize division by odd numbers, such as divide-by-3. This chapter describes a simple modification to a CMOS
injection locked frequency divider (ILFD) with direct injection, which gives it a
wide locking range both in the “divide-by-odd number” mode and in the conventional “divide-by-even number” regime, thereby opening up applications which
require frequency division by an odd number.
This chapter presents the circuit architecture and experimental validation of
its operations. Section 3.1 proposes a modified ILFD with direct injection. Section 3.2 explains the circuit architecture, the measurement setup, the algorithms
used for experimentally characterizing the ILFD under test and the experimentally
measured results. Section 3.3 shows the symmetric circuit architecture and the
experimental results for it and in the last Section 3.4 these results are analyzed.
3.1
Developed Model
We consider a direct injection locked frequency divider (ILFD) in this work. The
circuit diagram of the modified LC CMOS ILFD under consideration is shown in
Fig. 3.1.
29
30
Divide-by-Odd Number
Vi
C5
Figure 3.1: Modified LC CMOS ILFD with direct injection for Divide-by-Odd
number.
The modified LC CMOS ILFD comprise an oscillator with an additional
transistor and capacitor. The oscillator comprises an LC tank and four transistors.
The LC tank has a capacitor in parallel with a series combination of an inductor
and a resistor. The four transistors M 1 to M 4 include two P M OS transistor
and two N M OS transistors.The four transistors M 1 to M 4 work as a negative
resistance network. The additional transistorM 5 is an N M OS transistor and is
used to couple the injected signal to the LC tank(so-called direct injection). We
introduce an additional capacitor between the gate and drain of M 5. When no
injection signal is applied to M 5, the circuit oscillates with an unforced frequency
f0 . When we drive our circuit with an injected input signal Vi at frequency fs ,
the output signal V0 has a frequency fd . The ratio of the input signal frequency
fs to the output signal frequency fd , namely fs /fd , is called the rotation number,
denoted by ρ. Under appropriate conditions, the output signal locks to the injected
signal in such a way that the frequency of the input signal is an integer multiple of
frequency of the signal. With this circuit, we can get both even (divide-by-2) and
odd (divide-by-3) rotation numbers over ranges of the input frequency of similar
width.
3.2 Experimental Characterization
3.2
31
Experimental Characterization
Beyond the theory of Injection locked frequency divider, an experimental characterization of the developed ILFD is necessary. In this section, we explain and
physical realization of the ILFD under consideration. Furthermore, the experimental setup which is used in the laboratory for observing the locking behavior of
the ILFD under test will be explained.
3.2.1
ILFD on Bread-Board
To get started with the experimental characterization of the ILFD under test, we
built a physical prototype of the circuit with discrete components on a breadboard.
Fig. 3.2 shows the modified LC CMOS ILFD with direct injection on a breadboard.
Figure 3.2: ILFD implementation On bread-board.
In our design, we use Texas Instruments CD4007UBE CMOS DUAL COMPLEMENTARY PAIR PLUS INVERTER for the implementation of the five transistors (M 1-M 5). The CD4007UBE comprises three PMOS transistors and three
NMOS transistors.The pin assignment of the CD4007UBE, as provided on the
data sheet, is shown in the Fig. 3.3.
In the circuit implementation on the breadboard, two CD4007UBE chips are
used. On the first chip, two PMOS transistors (M1 and M2) and two NMOS
transistors (M3 and M4) are used to form the core of the ILFD.These two cross
coupled pairs of CMOS inverters act as a negative resistance. On the second
CD4007UBE chip, the fifth NMOS transistor M 5 is implemented; this acts as an
32
Divide-by-Odd Number
Figure 3.3: Pin assignment of CD4007UBE.
input switch through which the injected signal is coupled. M 5 is implemented on
another chip. When it is required to increase the size of the NMOS transistorM 5,
this is achieved by connecting three NMOS transistors in parallel. An additional
capacitor C5 connects the gate to the drain of the input transistor M 5.
3.2.2
Components and Parameters
We are using CD4007UBE transistors manufactured by Texas Instruments. The
additional capacitance C5 is 560 pF . The values of the components in the RLC
tank are shown in the Table 3.1
Component
Resistor R
Capacitor C
Inductor L
Value
235
57
1246
Units
Ω
pF
µH
Table 3.1: Component values of the LC Tank
The injection input signal voltage Vi is applied through an RC bias network,
which is shown in the Fig. 3.4.
The injected input signal is generated by combining a sinusoidal AC signal
wave with a DC component, using a resistor and a capacitor. This resistor and
3.2 Experimental Characterization
33
Figure 3.4: RC network for combining Vac and Vdc .
capacitor network is used because we cannot directly combine two different voltage
sources. In the circuit diagram, the input injected signal Vin is a sinusoidal voltage
with 6.03V DC offset, whose amplitude and frequency can be controlled separately.
While performing the experiment, the injection input signal was separated into two
parts. The first part consists of an AC sinusoidal signal wave Vac and the second
part adds a DC component Vdc of 6.03 V . These two parts were combined using
a resistor and a capacitor network. Equation (3.1) shows how the resistor and
capacitor network combines the two signals:
Vin = Vdc +
R
1 × Vac ,
R + jωC
(3.1)
1
If the values of R and C are sufficiently large, we can ignore the term jωC
,
and, at frequencies of interest, i.e. 100kHz<fs <2MHz, the RC network has no
effect on the ac component Vac , i.e:
R
≈1
1
R + jωC
(3.2)
The input sinusoidal voltage signal Vi is applied with a 6.03V DC offset. The
parameters of the RC bias network are as shown in the table 3.2.
34
Divide-by-Odd Number
Component
Resistor R
Capacitor C
DC Offset Vdc
Value
100
57
6.03
Units
KΩ.
pF
V.
Table 3.2: Component values of the RC Network
The circuit is powered by two DC power supplies. One power supply provides
9V DC as V DD while the other power supply provides the DC bias component
for the injected input signal. The latter is adjustable to produce an offset ranging
from 0V to 9V DC.
3.2.3
Differential Signal
At first, the output signal which is required is the single-ended output of the LC
tank. Afterwards, the differential signal is also analyzed to measure the differential
signal between the two nodes of the LC tank. To achieve this, an instrumentation
amplifier was built using discrete components on a breadboard. The instrumentation amplifier’s circuit diagram is shown in Fig. 3.5.
Figure 3.5: Instrumentation Amplifier for getting differential output.
The instrumentation amplifier is implemented by using three LT1229 Dual
100MHz Current Feedback Amplifiers maunfactured by Linear Technology. The
pin assignment of the LT1229, as provided by the data sheet, is shown in Fig. 3.6.
The instrumentation amplifier is powered by ± 15V DC. This instrumentation
amplifier adds the two single-ended outputs and gives a single differential output:
3.2 Experimental Characterization
35
Figure 3.6: Pin assignment of LT1229 Instrumentation Amplifier.
Vout = Va − Vb
3.2.4
(3.3)
Measurement Setup
The experimental set-up in the laboratory is shown in Fig. 3.7.
Figure 3.7: Measurement Setup.
In the measurement setup, we are using an Agilent 33250A function generator
to provide the sinusoidal component of the injected signal. The ILFD under test
is the Nonlinear Oscillator in Fig. 3.7. We are using an Agilent 53132A universal
counter to calculate the ratio between the frequencies of the input signal and the
36
Divide-by-Odd Number
output signal and also the boundary points of the locking regions. We observe the
input and output signals using a Tektronix TDS3034B oscilloscope. We connect a
PC to the instruments with GPIB cables. The instrument control, data acquisition, and processing algorithms are programmed in LabVIEW. The acquired data
is post processed using Matlab to observe the Arnold tongues corresponding to
different locking regions.
3.2.5
Algorithms
In our work, we use the boundary finding algorithm implemented in LabVIEW
which is explained in the Sec. A.3, in order to characterize the ILFD over large
ranges of frequencies and amplitudes of the injected signal. For different values of
rotation number (i.e. 2,3,4,5,6,7), the LabVIEW program generates an output file
which consists of the boundary points of the locking regions corresponding to the
selected rotation numbers.
Afterwards, we use Matlab to plot the boundary points for these rotation
numbers.
3.2.6
Experimental Results
The experimentally measured Arnold tongues corresponding to ρ =2,3,4,5,6,7 were
post processed using Matlab and are shown in Fig. 3.8.
The frequency fs of the input signal is plotted on the abscissa of the twodimensional bifurcation diagram and the amplitude A on the ordinate. The approximately triangular regions, called Arnold tongues, correspond to ranges of the
input over which the rotation number ρ (equivalently, the division ratio) is constant. The width of a tongue at a given input amplitude is the Locking Range
(LR). By contrast with the standard circuit, tongues corresponding to even and
odd division ratios have similar widths in the modified circuit. This means qualitatively that the circuit can divide by odd numbers as well as by even ones.
In particular, the locking range for divide-by-3 is comparable in size to that for
divide-by-2.
3.3 Symmetric Circuit
37
Figure 3.8: Experimentally measured Arnold tongues corresponding to ρ
=2,3,4,5,6 and 7 in the modified circuit of Fig. 3.1 .
3.3
Symmetric Circuit
In order to simplify the analytical analysis of the circuit, the circuit is made
symmetric by adding an injection through a PMOS and a capacitor C6.The new
developed symmetric circuit for direct injection locking Frequency divider is shown
in Fig. 3.9. The proposed changes to previous Asymmetric ILFD with direct
injection are highlighted with red lines.M 6 is complementary to M 5, and C6 is
equal to C5. Essentially, the ILFD is driven now symmetrically.
3.3.1
Components and Parameters
I am using CD4007UBE transistors manufactured by Texas Instruments. The
additional capacitance C5 and C6 are 560 pf. The parameters of Components of
LC tank are similar to the Asymmetric ILFD.
38
Divide-by-Odd Number
Figure 3.9: Symmetric Circuit of the ILFD with direct injection.
I am applying the input signal Vin as differential inputs through two RC
networks. I am applying the -Vin input signal as a sinusoidal voltage with a 6.03 v
DC offset at the gate of M 5. Similarly I apply the +Vin input signal as a sinusoidal
voltage with a 2.97 V DC offset at the gate of M 6. The parameters of components
of RC networks are similar to the Asymmetric ILFD.
The -Vin input signal is generated by using a simple inverting amplifier
(LT1229) to get the 180 degree phase shifted signal.
3.3.2
Experimental Results
The experimentally measured Arnold tongues corresponding to ρ =2,3,4,5,6,7 were
post processed using Matlab and are shown in Fig. 3.10.
3.4 Analysis
39
Figure 3.10: Experimental Results for the Symmetric Circuit of the ILFD with
direct injection.
3.4
Analysis
From Fig. 3.10, it can been seen that the tongues for the divide regions corresponding to ρ = 2 and 3 are of similar width. The divide region for 3 is significantly wider in this work than in previous works which did not include C5 and
C6 . Therefore, the proposed model can divide both by even and odd numbers.
This phenomena was first observed experimentally and then reproduced in simulations.The phenomenon has been reported in a conference paper [32] and a patent
application [34].
Chapter 4
Modeling and Simulations
In this chapter, we will discuss the simulations of the divide-by-odd number LC
CMOS ILFD with direct injection. Section 4.1 describes the Spice model and
the MOSFET model used. It talks about the Spice algorithm used for capturing
the locking behavior of the ILFD and describes the corresponding Matlab post
processing algorithm. Finally, it shows the Spice simulation results. Section 4.2
describes the implementation of the Symmetric circuit of the LC CMOS ILFD
with direct injection by explaining the schematic and simulation results. Finally,
section 4.3 gives an overall analysis of the simulation results.
4.1
Modeling and Spice Simulations
In the simulation part of this project, we built a model circuit using Spice, which
is intended to replicate the experiments. Spice can predict the circuit behavior
and works in the same way as the Frequency Sweeping method which we described
earlier. Spice produces its output in the form of an ASCII listing. The listing consists of columns of numbers corresponding to calculated outputs V oltages and/or
Currents. Therefore, a MATLAB program is needed to post process the output
of Spice in order to plot the bifurcation diagrams.
41
42
4.1.1
Modeling and Simulations
Spice Model
SPICE is a general purpose open source analogue electronic circuit simulator. It
is a powerful program that is used in integrated circuit and board-level design to
check the integrity of circuit designs and to predict circuit behavior.
The Spice model under consideration is shown in Fig. 4.1. The schematic is
the same as in Fig. 3.1 except for the parasitic output network. In our experiments,
we use Texas Instruments CD4007UBE CMOS DUAL COMPLEMENTARY PAIR
PLUS INVERTER, which have 3 complementary logic inverters. Each inverter has
an input capacitance and an output load capacitance and resistance. Therefore, for
matching the experimental results to simulations we add parasitic networks at both
outputs in our Spice model. While performing simulations, the most important
factor is the MOSFET model. In this project, the basic aim was to match the
simulations to experiments for divide-by-odd numbers. Therefore, many types of
MOSFET models were tried to get the best results.
C5
560pF
C3
180pF
R3
160K
R2
98.7
R4
C4 160K
180pF
Figure 4.1: H-Spice Circuit schematic of the developed Divide-by-Odd ILFD.
The complete Spice code/Spice net-list for the circuit schematic shown in
Fig. 4.1 is given in Appendix C.
4.1 Modeling and Spice Simulations
4.1.2
43
MOSFET Models
In the simulation, the most important component is the MOSFET model. A
transistor model is classified according to the level of sophistication, e.g. level 1,
2 or 3. The higher the level, the more precise and detailed the MOSFET model
is. The sizes of the transistors in the CD4007UBE used for experiments have been
measured by Tyndall National Institute. In this project, in order to match the
simulations to experimental result, many types of MOSFET models were tried to
get the best results. The transistor model we chose for our simulations is a Level-1
MOSFET model with the factor GAMMA=0, as shown in Fig. 4.2.
Figure 4.2: Spice model for MOS transistors in Figure. 4.1 with zero threshold
modulation.
4.1.3
SPICE Runtime Algorithm
In the SPICE algorithm, two variables are used. These are the injection frequency
finj and the amplitude of Vinj . In order to capture the ILFD’s locking behavior, we
sweep the input voltage Vinj from 0.1V to 5V and the frequency finj from 300kHz
to 2000kHz. We then carry out transient simulations and store the results in
ASCII format in an output file. The ASCII format output file is shown in Fig 4.3.
4.1.4
MATLAB Post-processing Algorithm
The output file from H-Spice gives us the details (e.g. voltage and time) of each
point of the selected output waveforms.
The main idea of post-processing using MATLAB is to calculate the frequen-
44
Modeling and Simulations
Figure 4.3: Spice Output ASCII data file presented to Matlab.
cies and frequency ratios as follows :
1. It collects data from the Spice output file in the form of the output voltage
data corresponding to one value of the input frequency.
2. Perform the Fast Fourier Transform and map the voltage data from the time
domain to the frequency domain.
3. Find the peak in the frequency domain and record this frequency as the
output frequency fd .
4. The frequency ratio is equal to the input frequency fs divided by the output
frequencyfd .
Important Digital Signal Processing knowledge is also used in MATLAB:
1. The Fast Fourier Transform is used to determine the frequency content of a
digital signal or the frequency response of a digital system.
2. The input to the Fourier Transform is a uniformly-sampled discrete-time
signal and the result of the transform is a discrete function of ω.
3. The output of the Fast Fourier Transform is periodic with period 2π. The
real frequencies in the range 0 tofs (sampling frequency) are mapped to ω
in the range 0 to 2π.
4.1 Modeling and Spice Simulations
45
4. The output of the Fast Fourier Transform is a vector of complex numbers
that is symmetrical about ω = π.
The key MATLAB functions used are as follows:
1. dlmread reads the numerical data from the Spice output data file which
contains the ASCII data, as shown in Fig 4.3. At the top of the Spice
Output data file, there is some simulation information which is not required
for our analysis. The first column (time) is also unnecessary for the analysis.
Therefore, MATLAB reads the data from the first line of the numerical data
directly. In this case, the read range in the dlmread function is [166 100156
1 1]. [166 100156] is the number of lines containing relevent numeric data,
and [1 1] denotes the second column..
2. fft(x): Fast Fourier Transform of the array x.
3. To find the maximum element in array A, we use [C, I] = max(A). It will
find the maximum value element in array A, then return the maximum value
to C and assign the index of the maximum value to I.
Complete MATLAB code is listed in Appendix C.
4.1.5
SPICE and MATLAB Simulations Results
Brute force transient simulations were run over a grid of points in the A-fs plane of
the two-dimensional bifurcation diagram and the rotation number ρ was calculated
by post-processing the resulting time series using Matlab, as described above. The
results are summarized in Fig. 4.4.
Spice simulation results using Level-1 MOSFET models without considering
the parasitic input and output impedance networks are shown in Fig. 4.5. From
this Figure, it can be seen that, without considering the parasitic input and output impedance networks, the center frequency for the tongues shift towards the
right. This causes a noticeable mismatch between the experimental and simulation
results. By adding parasitic input and output impedance networks to our Spice
model, we can reduce this mismatch to a large extent.
Qualitatively, the widths of the divide-by-2 and divide-by-3 regions in the
simulations are similar to those found in the physical experimental implementation, confirming our experimental observations that the circuit can divide by odd
numbers as well as by even numbers.
46
Modeling and Simulations
C a p a c it o r c o n n e c t e d S in g le M 5 , in c lu d in g R L C L , 7 V D C b ia s ,
2 .5
A m p litu d e
2
1 .5
1
0 .5
0
3
4
5
6
7
F re q u e n c y
8
9
10
11
x 10
5
Figure 4.4: Spice simulation results for divide-by-2 and divide-by-3 locking regions.
Figure 4.5: Spice simulation results for divide-by-2 and divide-by-3 locking regions
without parasitic impedance networks.
4.2
Symmetric Circuit
In the simulation part of this project, we built a model circuit using Spice of
the symmetric circuit, which is intended to replicate the experiments. Spice can
predict the circuit behavior and works in the same way as the Frequency Sweeping
which we introduced earlier. Spice produces its output in the form of an ASCII
listing. The listing consists of columns of numbers corresponding to calculated
outputs V oltages and/or Currents. Therefore, MATLAB program is needed to
analyze the output of Spice.
4.2 Symmetric Circuit
4.2.1
47
Spice Model
The Spice circuit model under consideration of the symmetric circuit is shown
in Fig. 4.6. The schematic is the same as in Fig. 3.9 except the output parasitic network. In our experiments, we use Texas Instruments CD4007UBE CMOS
DUAL COMPLEMENTARY PAIR PLUS INVERTER, which have 3 complementary logic inverters. Each inverter has an input capacitance at input and an output
load capacitance and resistance. Therefore, for matching the experimental results
to simulations we add parasitic network at both outputs in our Spice model. While
performing simulations, the most important factor is the MOSFET model. In this
project, the basic aim was to match the simulations to experiments for divide-byodd numbers. Therefor many types of MOSFET models were tried to get the best
results.
MN6
C6
Vs
R5
2.97V
Figure 4.6: H-Spice Circuit schematic of the Symmetric Circuit.
The complete Spice code/Spice net-list for the circuit schematic shown in
Fig. 4.6 is given in Appendix C.
4.2.2
SPICE and MATLAB Simulations Results
Brute force transient simulations were run over a grid of points in the A-fs plane
of the two-dimensional bifurcation diagram and the rotation number ρ was calculated by post-processing the resulting time series using Matlab, as described
earlier. The model includes the input and output parasitic network. The results
are summarized in Fig. 4.7.
48
Modeling and Simulations
Figure 4.7: Spice simulation results for divide-by-2 and divide-by-3 locking regions.
4.3
Analysis
Qualitatively, the modified ILFD exhibits both divide-by-2 and divide-by-3 behavior, which has been observed experimentally and via Spice simulations. From
the Symmetric circuit simulations, the divide-by-2 and divide-by-3 regions lie in
almost the same input frequency range as was observed in the Spice simulations
for the Asymmetric circuit. The implementation of the design in Spice and the
simulated results shows that the developed LC CMOS ILFD with direct injection
can perform both divide-by-even and divide-by-odd numbers.
Chapter 5
Conclusion and Future Work
This chapter presents conclusions of the project work and also suggests potentially
fruitful directions for future work in the field of ILFD’s.
Section 5.1 concludes the project work with a description of the most important achievements. Section 5.2 talks about the limitations and drawbacks found
during the work on this project. Section 5.3 discusses the post project ideas which
can lead to some interesting future research based on this project in the field of
ILFD’s.
5.1
Conclusion
Injection-Locked frequency dividers is a well-studied topic and has been under
research for many years. In recent years, a lot of research work has taken place.
M.P Kennedy’s group in Tyndall National Institute has been working on InjectionLocked frequency dividers for many years. This masters thesis work is a continuation of the previous research in order to study deeply and to analyze the
performance of Injection-Locked frequency dividers with direct injection.
This masters thesis work was carried out over a period of twenty-four weeks.
In the first phase of the project, the author learned the background about ILFDs,
the existing circuit behavior, the experimental setup, and SPICE. In the second
phase, the author studied the LabVIEW algorithms and used these algorithms to
reproduce various earlier experimental observations and SPICE simulations. In
the final phase of the project, the author developed a modified LC CMOS ILFD
49
50
Conclusion and Future Work
with direct injection which is capable of both divide-by-even and divide-by-odd
numbers. This phenomenon was first observed experimentally and then validated
by simulations.
Three LabVIEW algorithms were tested on the ILFD under test for characterizing its locking behavior. Compared to other algorithms, the boundary finding
algorithm is more efficient and accurate for measuring the boundary points of the
locking regions. This algorithm is very easy to use. For future work in the field of
ILFD’s, this algorithm can be used as a certified tool. Using the boundary finding
algorithm, many earlier experimental observations and phenomena were reproduced; for example, the dependence of the locking range on the forward body bias
and the amplitude of the input injected signal, as well as the switch size. During
the experimental work in this project, the equipment, circuit board, transistors
and instruments were different from previous works. Therefore, after getting,
the same results as previously observed, we verified the robustness of the circuits
behavior and the efficiency of the boundary finding algorithm. Similarly, the simulations also matched the experimentally observed results very closely. Therefore,
the Spice model provides a strong base for future work in the field of Injectionlocked frequency divider, especially for developing a mathematical model for the
ILFD.
For reasons associated with frequency planning and power consumption, there
is interest in developing ILFDs that are capable of dividing by numbers other than
two. Several divide-by-3 ILFDs have been developed in recent years, but these are
significantly more complex from an implementation point of view than comparable
divide-by-2 ILFDs.
We have developed a simple modification of a standard “divide-by-even number” Direct Injection CMOS LC ILFD which enables it also to divide by odd
numbers. The design concept has been validated experimentally and by SPICE
simulations. This masters thesis work has been reported at the ICECS 2012 Conference [32]. We have also applied for a patent for the idea [34].
5.2
Limitations
A few limitations of this project should also be mentioned here.
In the experiment, to get precise results, and to see the waveforms on the oscilloscope it is necessary to add an instrumentation amplifier before the final output,
as discussed in the experimental characterization section of chapter three. This
aspect of the differential signal operation was not implemented in the experiments.
5.3 Future Work
51
Consequently, some unexpected results occurred, especially in the overlap regions. These imprecise operations would lead to algorithm errors and then make
incorrect estimates of the locking regions.
Moreover, the boundary finding algorithm was used in a relatively low frequency range (less than 5MHz). Hence, the performance in the high frequency
range should be tested and validated in the future.
5.3
5.3.1
Future Work
Analytical Model
The long-term goal of this research work is to build an accurate mathematical
model of the divide-by-odd circuit in order to optimize its locking behavior. To
develop this mathematical model, future work should take both experiments and
simulation into consideration, and produce a simple mathematical model with
few nonlinear equations. Therefore, it requires a precise measuring method and
hardware in the experiment and a more accurate SPICE model to replicate the
locking mechanism.
We are in the process of developing a theoretical explanation of the locking
mechanism underlying this ILFD with direct injection. For this purpose, we are
working with another modified version of the ILFD with direct injection. This new
ILFD model and the analytical explanation of the underlying locking phenomenon
have been submitted for publication [33].
5.3.2
Monolithic Implementation
In the future, we are prototyping an integrated circuit implementation of the
divide-by-odd ILFD with direct injection in the multi-GHz frequency range. We
are going to implement this circuit using the TSMC 65nm Cadence design environment. The target for our Cadence design is the 24 GHz ISM band that goes
from 24.0 to 24.25 GHz. The center frequency is 24.125 GHz. The results of this
follow-on project, when complete, will be reported elsewhere.
Bibliography
[1] J. Craninckx and M. Steyaert, “Wireless CMOS Frequency Synthesizer Design”
London, U.K.: Kluwer, 1998.
[2] Wikimedia
Foundation,
“Frequency
http://en.wikipedia.org/wiki/Frequency-synthesize, 2012.
synthesizer”
[3] Daneshgar, De Feo and Kennedy, “Observations concerning the locking range
in a complementary differential LC injection-locked frequency divider-Part I:
Qualitative analysis” IEEE Trans. Circuit and Systems-Part I, vol. 57, no. 1,
pp. 179–188, Jan. 2012.
[4] M.P. Kennedy, H. Mo and X. Dong. “Experimental Characterization of Arnold
Tongues in Injection- Locked CMOS LC Frequency Dividers with Tail and
Direct Injection.” In Proc. ECCTD 2011, pp. 484–487.
[5] H. Lee and Hajimiri. “Oscillator Phase Noise: A Tutorial” IEEE JOURNAL
OF SOLID-STATE CIRCUITS, VOL. 35, NO. 3, MARCH 2000.
[6] B. Razavi, “Challenges in portable RF transceiver design” IEEE Circuits
Devices Mag., vol. 12, no. 9, pp. 12–25, Sep. 1996.
[7] M. M. Ghahramani, S. Daneshgar, M. P. Kennedy, and O. De Feo, “Optimizing
the design of an injection-locked frequency divider by means of a nonlinear
analysis” in Proc. Eur. Conf. Circuit Theory Des., Seville, Spain, Aug. 2007,
pp. 571–574.
[8] J. Craninckx and M. Steyaert, “A 1.75 GHz/3 V dual-modulus divide-by128/129 prescaler in 0.7µ m CMOS” in Proc. ESSCIRC, Sept.1995, pp. 254–
257.
[9] D. Pfaff and Q. Huang, “A quarter-micron CMOS 1 GHz VCO/prescaler-set
53
54
Bibliography
for very low power applications” in IEEE Custom Integrated Circuits Conf.
Dig. Tech. Papers, May 1999, pp.649–652.
[10] Q. Huang and R. Rogenmoser, “Speed optimization of edge-triggered CMOS
circuits for gigahertz single-phase clocks” IEEE J. Solid-State Circuits, vol.
31, pp. 456–463, Mar. 1996.
[11] J. Lee and B. Razavi, “A 40 GHz frequency divider in 0.18 µm CMOS
technology” in Symp. VLSI Circuits Dig. Tech. Papers, June 2003, pp. 259–
262.
[12] S. Verma, H.R. Rategh, and T.H. Lee. “A unified model for injection-locked
frequency dividers” IEEE J. Solid-State Circuits, vol. 38, no. 6, pp. 1015–1027,
Jun. 2003.
[13] B. Razavi, “A study of injection locking and pulling in oscillators” IEEE J.
Solid-State Circuits, vol. 39, no. 9, pp. 1415–1424, Sep. 2004.
[14] M.P. Kennedy, K.R. Krieg, and L.O. Chua. “The devil’s staircase: the electrical engineer’s fractal” IEEE Trans. Circuits and Systems, vol. 36, no. 8, pp.
1133–1139, Aug. 1989.
[15] R. Adler, “ A study of locking phenomena in oscillators” Proc. IRE Waves
Electrons, vol. 34, no. 6, pp. 351–357, Jun. 1946.
[16] A. Pikovsky, “ Rosenblum, and J. Kurths, Synchronization. Cambridge” U.K.:
Cambridge Univ. Press, 2001.
[17] M. V. Bartuccelli, J. H. B. Deane, and G. Gentile, “Frequency locking in an
injection-locked frequency divider equation” Proc. R. Soc. London A, Math.
Phys. Eng. Sci., vol. 465, no. 2101, pp. 283–306, Jan. 2009.
[18] H.R. Rategh and T.H. Lee. “Superharmonic injection locked oscillators as
low power dividers” In Prof. Symp. VLSI Circuits Dig., pp. 132–135. Jun 1998
[19] M. Tiebout. “A CMOS direct injection-locked oscillator topology as highfrequency low-power frequency divider” IEEE J. Solid-State Circuits, vol. 39,
no. 7, pp. 1170–1174, Jul. 2004.
[20] S. Daneshgar, O. De Feo and M.P. Kennedy. “Observations Concerning
the Locking Range in the Complementary Differential LC Injection-Locked
Frequency Divider-Part II: Design Methodology” IEEE Trans. Circuits and
Systems—Part I, vol. 58, no. 4, pp. 765–776, Apr. 2011.
Bibliography
55
[21] Y.-H. Chuang, S.-H. Lee, R.-H. Yen, S.-L. Jang, J.-F. Lee, and M.-H. Juang,
“A wide locking range and low voltage CMOS direct injection locked frequency
divider” IEEE Microw. Wireless Compon. Lett, vol. 16, no. 5, pp. 299–301,
May 2006.
[22] S.-L. Jang and C.-F. Lee, “A wide locking range LC-tank injection locked
frequency divider” IEEE Microw. Wireless Compon. Lett., vol. 17, no. 8, pp.
613–615, Aug. 2007.
[23] S. Daneshgar, “Analytical Method to Predict Locking Range in InjectionLocked Frequency Dividers” PhD thesis, University College Cork, April 2010.
[24] A. Buonomo and A. Lo Schiavo. “An analytical approach to the study of
injection-locked frequency dividers” IEEE Trans. on Circuits and Sys.-I (in
press).
[25] A. Buonomo and A. Lo Schiavo. “Nonlinear dynamics of divide-by-2 injectionlocked frequency dividers” Int. J. Circuit Theory Appl. (submitted).
[26] Sheng-Lyang Jang, Chien-Feng Lee, Wei-Hsung Yeh. “A Divide-by-3 Injection
Locked Frequency Divider With Single-Ended Input” IEEE MICROWAVE
AND WIRELESS COMPONENTS LETTERS, VOL. 18, NO. 2, FEBRUARY
2008.
[27] I.-T. Lee, C.-H. Wang and S.-I. Liu. “Current-reused divide-by-3 injectionlocked frequency divider in 65 nm CMOS” ELECTRONICS LETTERS 1st
September 2011, Vol. 47, No. 18.
[28] J.A. Glazier and A. Libchaber. “Quasi-Periodicity and Dynamical Systems:
An Experimentalist’s View” IEEE Trans. Circuits and Systems, vol. 35, no. 7,
pp. 790–809, Jul. 1988.
[29] Final Report of Xi Wu . “Injection-Locked Frequency Divider” Department
of Electrical and Electronic Engineering,UCC, March 2012.
[30] M.P. Kennedy, X. Dong and H. Mo. “Phenomenological Study of an InjectionLocked CMOS LC Frequency Divider with Direct Injection” In Proc. ECCTD
2011, pp. 480–483.
[31] Final Report of Huiyuan Xing . “Injection-Locked Frequency Divider” Department of Electrical and Electronic Engineering,UCC, March 2012.
[32] M.S. Asghar, M.A. Awan and M.P Kennedy. “A “Divide-by-Odd Number” Direct Injection CMOS LC Injection-Locked Frequency Divider” In Proc.ICECS
56
Bibliography
2012, pp. 488-491, Seville, Spain, 09-12 Dec. 2012.
[33] A. Buonomo, A. Lo Schiavo, M. A. Awan, M.S. Asghar and M.P Kennedy.
“A CMOS Injection-Locked Frequency Divider Optimized for Divide-by-Two
and Divide-by-Three Operation” IEEE Trans. Circuits and Systems-Part II,
**(*):***, ***. 2013 (submitted, ** December 2012).
[34] “Divide-By-Three Injection-Locked Frequency Divider”, M.P Kennedy, M.S.
Asghar, M.A. Awan, A. Buonomo and A. Lo Schiavio, US patent application,
filed December 2012.
Appendix A
LabVIEW Algorithms
A.1
Frequency Sweeping
The frequency sweeping algorithm is the first LabVIEW algorithm which we will
analyze and use to characterize the ILFD under test. Frequency sweeping is a
type of brute force method to measure the locking behavior and to determine the
boundary points of the locking regions. The LabVIEW block diagram and the
control panel of the frequency sweeping algorithm are shown in Figures A.1 and
A.2 respectively [31].
In the frequency sweeping algorithm, the values of the parameters can be set
in the control panel. Before running the algorithm, the following parameters need
to be set;
1. Provide the device information such as VISA (Virtual Instrument Software
Architecture) or GPIB address (General Purpose Interface Bus) which are
the interface addresses of the devices that are connected to the PC.
2. Choose, if required, the DC offset, units, and shape of the waveform of the
injected input signal.
3. Select the Start, stop and step frequencies of the desired frequency sweep.
4. Set the stop and start Vpp values for the injected input signal.
5. Set an appropriate instruction and function which will set the counter’s mea57
58
LabVIEW Algorithms
Figure A.1: Block diagram of the frequency sweeping algorithm.
Figure A.2: Control panel of the Frequency Sweeping algorithm.
surement mode. For example, if we want the counter to measure the boundary points for the output frequency then we set the instruction to measure
and the function to frequency 2.
A.1 Frequency Sweeping
59
6. An output file name is to be provided which will contain the measurement
results from the counter. This file will be stored at the completion of the
algorithm in the same directory as the frequency sweeping algorithm.
7. To ensure that the instruments have sufficient time for calculations and measurements, a millisecond delay is to be set.This is the delay time between
writing the injected signal and reading back the output ratio.
The algorithm and working of the frequency sweeping program are explained
as follows:
1. First the sweep frequency range and interval are chosen which should be
equal to the grid points on the X-axis. Similarly, choose the sweep amplitude
range and interval which should be equal to the grid points on the Y-axis.
The step size for the Vpp values is set by default to 0.1 V . The user can alter
it according to their own requirements.
2. The algorithm will run from the start frequency to the stop frequency with
the first provided value of Vpp . After it reaches the stop frequency, it will
add a step (which is 0.1V in our case ) to the previous Vpp value and then
sweep again from the start to the stop frequency.This will continue until the
value of Vpp becomes greater then the predefined stop value of Vpp .
3. The algorithm will stop when the final value of Vpp is greater than the prescribes stop value or the frequency ratio is greater then 6.
4. At the end, the program will generate an output file containing the measured
frequency points and the frequency ratios, respectively, and save it in the
path of the frequency sweeping algorithm.
The frequency sweeping program runs over the whole range of frequencies
and amplitudes. This takes a huge amount of time for a single experiment. This
is a drawback of this algorithm. We used the frequency sweeping algorithm to
characterize the locking regions for ρ=2,3,4,5,6. We set the start frequency to 300
kHz and the stop frequency is 2000 kHz with a step size of 5 kHz. The Vpp was set
to step from 0.1V to 5V with a default step size of 0.1 V . Now we can estimate
the time required for the frequency sweep algorithm to run over the whole range
of frequencies and amplitudes:
+1=341 points
Number of frequency points= 2000kHz−300kHz
5kHz
−0.1V
Number of amplitude points= 5V0.1V
+1=50 points
Total sweeping points=341 × 50=17050 points
60
LabVIEW Algorithms
17050
Total time= 1sec/point
=17050sec=4.74hours
As the chosen frequency interval step size is 5 kHz, many points inside the
interval will be missed by the algorithm. If we reduce the step size, then the
running time of the program will increase enormously. This will miss lots of points
inside an interval. If the frequency step is reduced further, the running time will
be significantly larger again. Frequency sweeping is suitable for measuring the
overlap between consecutive tongues over a small range of input frequencies with
a small injected amplitude [31].
A.2
Boundary Following
Boundary following is a more efficient approach to measuring the boundaries of
the Arnold Tongue locking regions [30]. The boundary following algorithm has
been designed specifically to characterize the locking regions and the tongues of an
ILFD. Previous students [30] have designed an effective way to find the boundaries
of Arnold Tongues. The fact that each boundary point is close enough to the other
boundary point gives rise to the idea of a local search for boundary points. By
taking very small steps, boundary points for tongues can be measured as shown
in Fig. A.3
Figure A.3: Measurement of tongues in Boundary following algorithm.
The rotation number is constant inside the each tongue, which makes boundary following a bit difficult. For example, it is very difficult to decide which
specific frequency point is the first point of the respective rotation number for the
left boundary. Similarly for the right boundary, which specific frequency point is
the last incidence for the target rotation number. Therefore, an assumed boundary concept is used. In this algorithm, the assumed boundary consists of points
with a rotation number that are a fixed difference of 0.001 from the actual rotation
A.2 Boundary Following
61
number. For example, for the divide-by-2 boundary, the left boundary points are
equal to 1.999 and the right boundary frequency points are equal to 2.001.
Before running the algorithm, the following parameters need to be set;
1. Provide the device information such as VISA (Virtual Instrument Software
Architecture) or GPIB address (General Purpose Interface Bus) which are
the interface addresses of the devices connected to the PC.
2. Choose the Start and free-running frequencies.
3. Set the stop and start Vpp values for the input injected signal and a start
division value.
4. Set an appropriate instruction and function which will set the counter’s measurement mode.
5. An output file name is to be provided (which by default is in the date and
time format) which will contain the measurement results from the counter.
This file will be stored at the completion of the algorithm in the same directory as the boundary following algorithm.
The algorithm and working of the boundary following program are explained
as follows:
1. When the algorithm is started, it searches for the first left boundary point
from the point with the start frequency and the max Vpp (user specified),
which should be on the left side of the left boundary.
2. The algorithm finds the point within a fixed difference of 0.08 from the assumed boundary by jumping the frequency up and down. It uses three different step sizes, fo /25, fo /50, fo /100, where fo is the free-running frequency
of the ILFD measured in advance by the user. This is shown schematically
in Fig. A.4.
3. A half-interval search strategy is used by stepping the input frequency up
fo
and down until the boundary point is found. The half search interval is 25
1
× 2n , where we increment n at every step.
4. If the measured point is within 0.005 of the boundary point or the interval
is less then 30 Hz, then the stop condition is reached.
5. When the algorithm reaches its stop condition, it records the input frequency
62
LabVIEW Algorithms
point of the boundary point and continues finding the next boundary point
by taking the last input frequency as the start frequency.
6. Once the left boundary has been found, the algorithm starts finding the right
boundary using a half interval search.
7. The algorithm finds the boundary points for the rotation numbers from first
till the seventh.
Figure A.4: Concept behind finding a boundary point in Boundary following algorithm.
The main advantage of the boundary following algorithm is its speed and
accuracy for finding boundary points. For every tongue, it takes only 10 minutes.
We ran the boundary following algorithm to characterize the locking regions for
ρ=2,3,4,5,6,7. We set the start frequency to 250 kHz and the free-running frequency is 100 kHz. The amplitude is set to be from 0.1V to 5 V with a default
step size of 0.1 V . When the interval is less then 30 Hz, the boundary search
stops. The instruments take half a second to complete each jump. For the ILFD
with direct injection, the first boundary point for divide-by-2 is approximately
300kHz. We can estimate the time taken by the boundary following algorithm for
one complete experiment to run over whole range of frequencies and amplitudes
as follows:
f0
)=4 kHz)×
First interval( 25
1
2n <30Hz→n=8
Number of boundary points on each tongue=100
Number of jumps for first boundary point≈
300−250
+8=21
4
Number of jumps for rest of points≈4(estimated)+8=12
Total number of jumps for one tongue=21+12×99=1209
A.3 Boundary Finding
63
Total time for one tongue=1209× 0.5sec
jump =604.5sec=10 min
The advantages of the boundary following algorithm are its speed and accuracy. If the user wants to measure the boundary points of tongues for two very
different rotation numbers (e-g,2 or 8), then the speed and accuracy decrease. The
use of small steps taken by algorithm is not necessary. The boundary following algorithm finds the point within range a 0.08 form the assumed boundary, but then
after the first step of the half interval search, the algorithm will use a larger step
(fo /50 = 4kHz). Due to the above mentioned drawbacks in the boundary following
algorithm, the improved Boundary finding algorithm was developed [31].
A.3
Boundary Finding
In order to overcome the drawbacks of the boundary following algorithm a new
LabVIEW algorithm was designed, known as the boundary finding algorithm.
Before running the algorithm, the following parameters need to be set:
1. Provide the device information such as VISA (Virtual Instrument Software
Architecture) or GPIB address (General Purpose Interface Bus) which are
the interface addresses of the devices connected to the PC.
2. Choose the DC Offset if required, the Units and the shape of the waveform
of the input injected signal.
3. Set the stop, start and the step values for the amplitude Vpp of the input
injected signal.
4. enter the target rotation numbers in a list, for example, if user wants to
calculate the division ratio for 2,3,4 then these should be typed respectively.
5. Set an appropriate instruction and function which will set the counter’s measurement mode.
6. An output file name is to be provided (which by default is in date and time
format) which will contain the measurement results from the counter. This
file will be stored at the completion of the algorithm in the same directory
as the boundary finding algorithm.
The control panel of the boundary finding algorithm is shown in Fig. A.5
figure.
64
LabVIEW Algorithms
Figure A.5: Control panel of boundary finding algorithm.
The algorithm and operation of the boundary finding program are explained
as follows:
1. In the beginning of the boundary finding algorithm, the input injected signal
coming from the signal generator’s output is turned Off by default . Then
the algorithm calculates the free running frequency of the ILFD under test.
2. The algorithm starts searching for the left boundary points from the frequency point fo ×D and the stop value of Vpp , where D is the first division
number or ratio ρ inserted by the user in the division list. The difference
between the searched point and the real boundary point is d×boundarydelta.
The default value of boundarydelta is 0.001, but can be altered by the user
according to the needs.
3. A half interval search method is used by the algorithm to search the boundary
points. The interval is fo ×D−1kHz
, where n goes from 0 to n-1. The purpose
2n
of the 1kHz offset is to make sure that the first jump is within the range
of the signal generator. For example, if the start point were in the locking
region then the algorithm will jump to the left side and the input frequency
would become 0 kHz after the first jump. The half interval search is shown
conceptually in Fig. A.6.
4. The first interval in the half interval search method is fo ×D-1kHz. Prior to
taking the first interval jump, the algorithm determines whether the current
point is on the left side or the right side of the boundary. If the point is on
the left side then the algorithm will jump from the current point to the right;
otherwise, if it is on the right side, then the algorithm will jump towards the
A.3 Boundary Finding
65
left side. In other words, the algorithm increments the input frequency by
the first interval. After the first jump is completed, the algorithm will reduce
the second interval jump by half. In a similar way, the algorithm keeps on
jumping right and left until it finds the exact boundary point.
5. When the assumed boundary point is within a difference of D× dif f erencedelta
from the measured boundary point, or the interval becomes less than 1Hz,
then the stop condition is reached.
6. The algorithm then goes on finding the other boundary points with the same
start frequency of fo ×D.
7. When the left boundary points are found then the algorithm starts finding
the right boundary points in a similar way.
Figure A.6: The half interval search method concept for the boundary finding
algorithm.
The Boundary Finding Algorithm for the divide regions of the divide-by-2
and divide-by-4 regions are shown in Fig. A.7.
The boundary finding algorithm is a more general purpose algorithm unlike
the boundary following algorithm, which can operate on all ILFD’s. Boundary
finding is more accurate due to the fact that the new boundary point does not
depend on the previously measured boundary points. As compared to the boundary following algorithm, it takes 16 min, which makes it a bit slower. We ran
the boundary finding algorithm for the divide-by-2 locking region to calculate the
time. We set the free-running frequency to 200 kHz. In the half interval search
method, when the interval is less the 1kHz then each boundary point stops and it
is assumed that the instrument takes half second before the next jump;
66
LabVIEW Algorithms
Figure A.7: Measurement of tongues using the boundary finding algorithm.
First interval(≈400kHz)×
1
2n <1Hz→n=19
Number of boundary points per tongue=100
Number of jumps for first boundary point=19
Total number of jumps for one tongue=19 ×100=1900
Total time for one tongue=1900× 0.5sec
jump =950sec=16 min
The Boundary Finding Algorithm has fewer parameters to be set by the user
as compared to the Boundary Following Algorithm. The user types in the Division
ratio values for which they want to find the boundary points in the Division list
in any order [30]. Flow charts of boundary finding algorithm are shown in Figures
A.8- A.10.
A.3 Boundary Finding
67
Figure A.8: Flow chart for the Main Process of the Boundary-Finding Algorithm
Flow.
68
LabVIEW Algorithms
Figure A.9: Flow chart for the left boundary of the Boundary-Finding Algorithm.
A.3 Boundary Finding
69
Figure A.10: Flow chart for the right boundary of the Boundary-Finding Algorithm.
Appendix B
Matlab Post-Processing
Code
B.1
Frequency Sweeping
%%%plot
figure
axis([0.0e3 3000e3 0 5.0]);
hold on;
y=[0.1:0.1:5.0
0.1:0.1:5.0]’;
% Freq2 = load(’2.000 13.54.04.03.2012.txt’);
%
% plot(Freq2(:,1),y(:,1),’.-r’);
% plot(Freq2(:,2),y(:,2),’.-r’);
Freq2 = load(’devide by 2.txt’)
for i=1:50
for j=1:2
plot(Freq2(i,j),y(i,j),’-rx’);
end
end
70
B.1 Frequency Sweeping
Freq3 = load(’devide by 3.txt’);
for i=1:29
for j=1:2
plot(Freq3(i,j),y(i,j),’.b-’);
end
end
%
% %legend(’red % by 2’,’Blue % by 3’);
Freq4 = load(’devide by 4.txt’);
for i=1:50
for j=1:2
plot(Freq4(i,j),y(i,j),’.-r’);
end
end
% %
Freq5 = load(’devide by 5.txt’);
for i=1:50
for j=1:2
plot(Freq5(i,j),y(i,j),’.-g’);
end
end
Freq6 = load(’devide by 6.txt’);
for i=1:50
for j=1:2
plot(Freq6(i,j),y(i,j),’.k-’);
end
end
%
% Freq7 = load(’7.000 15.41.25.05.2012.txt’);
% for i=1:2
%
for j=1:20
%
plot(Freq7(i,j),y(i,j),’.-k’);
%
end
% end
grid
title(’LC CMOS ILFD with direct injection locking regions’);
xlabel(’Frequency/Hz’);
ylabel(’Amplitude’);
%end code
71
72
B.2
Matlab Post-Processing Code
Boundary Following
%%%plot
figure
axis([0.0e3 2500e3 0 5.0]);
hold on;
y=[2.0:-0.1:0.1
0.1:0.1:2.0];
% Freq2 = load(’2.000 13.54.04.03.2012.txt’);
%
% plot(Freq2(:,1),y(:,1),’.-r’);
% plot(Freq2(:,2),y(:,2),’.-r’);
Freq2 = load(’16.41_25.05.2012 2.000.txt’);
for i=1:2
for j=1:20
plot(Freq2(i,j),y(i,j),’.-b’);
end
end
legend (’blue % by 2’, ’Black % by 3’,’Red % by 5’,’Blue % by 6’ )
Freq3 = load(’16.41_25.05.2012 3.000.txt’);
for i=1:2
for j=1:20
plot(Freq3(i,j),y(i,j),’.-k’);
end
end
Freq4 = load(’16.41_25.05.2012 4.000.txt’);
for i=1:2
for j=1:20
plot(Freq4(i,j),y(i,j),’.-r’);
end
end
Freq5 = load(’16.41_25.05.2012 5.000.txt’);
for i=1:2
for j=1:20
plot(Freq5(i,j),y(i,j),’.-b’);
end
end
Freq6 = load(’16.41_25.05.2012 6.000.txt’);
B.3 Boundary Finding
for i=1:2
for j=1:20
plot(Freq6(i,j),y(i,j),’.-k’);
end
end
grid
title(’LC CMOS ILFD with direct injection locking regions’);
xlabel(’Frequency/Hz’);
ylabel(’Amplitude’);
B.3
Boundary Finding
%%%plot
figure
axis([0.0e3 2500e3 0 5.0]);
hold on;
y=[2.0:-0.1:0.1
2.0:-0.1:0.1];
% Freq2 = load(’2.000 13.54.04.03.2012.txt’);
%
% plot(Freq2(:,1),y(:,1),’.-r’);
% plot(Freq2(:,2),y(:,2),’.-r’);
Freq2 = load(’02.000 12.34.25.05.2012.txt’);
for i=1:2
for j=1:20
plot(Freq2(i,j),y(i,j),’-rx’);
end
end
Freq3 = load(’03.000 12.51.25.05.2012.txt’);
for i=1:2
for j=1:20
plot(Freq3(i,j),y(i,j),’.b’);
73
74
Matlab Post-Processing Code
end
end
%legend(’red % by 2’,’Blue % by 3’);
Freq4 = load(’4.000 15.03.25.05.2012.txt’);
for i=1:2
for j=1:20
plot(Freq4(i,j),y(i,j),’.-r’);
end
end
Freq5 = load(’5.000 15.16.25.05.2012.txt’);
for i=1:2
for j=1:20
plot(Freq5(i,j),y(i,j),’.-b’);
end
end
Freq6 = load(’6.000 15.29.25.05.2012.txt’);
for i=1:2
for j=1:20
plot(Freq6(i,j),y(i,j),’.-k’);
end
end
Freq7 = load(’7.000 15.41.25.05.2012.txt’);
for i=1:2
for j=1:20
plot(Freq7(i,j),y(i,j),’.-k’);
end
end
grid
title(’LC CMOS ILFD with direct injection locking regions’);
xlabel(’Frequency/Hz’);
ylabel(’Amplitude’);
Appendix C
Spice Netlist and Matlab
Code
C.1
Spice Netlist
**RLCLsingM5_Capacitor_Gamma0
.GLOBAL 0
.OPTION POST=1 ingold=2 numdgt=10 DVDT=4 LVLTIM=3 RMAX=5e-3
.OPTIONS NOWARN warnlimit=0
.param Freq =300k
.param v1=2.3
.TRAN 10ns 200us START=100us SWEEP Freq 300k 1100k 5k
.print
vc=PAR(’(V(1)-V(2))’)
**main circuit
*vdd vdd 0 9
Vdgpw1 Vdd 0 PWL (0 0 1e-5 9 1meg)
Vs vs 0 SIN (0 v1 Freq)
Vdc vdc 0 7
R2 vi vdc 9.87e4
C2 vs vi 1e-6
75
76
Spice Netlist and Matlab Code
R1 1 3 234
L1 3 2 1.2468e-3
C1 1 2 7.5e-11
C3 1 0 180E-12
R3 1 0 200000
C4 2 0 180E-12
R4 2 0 200000
mp1 1
mp2 2
mn3 1
mn4 2
mn5 1
C5 vi
2 vdd vdd PMOSt L=10e-6 W=60e-6
1 vdd vdd PMOSt L=10e-6 W=60e-6
2 0 0 NMOSt L=10e-6 W=30e-6
1 0 0 NMOSt L=10e-6 W=30e-6
vi 2 0 NMOSt L=10e-6 W=30e-6
1 560e-12
* ----------------------------------------------------------------------*
C.2
Spice Netlist for Symmetric Circuit
*****Symmetric ILFD*******
.GLOBAL 0
.OPTION POST=1 ingold=2 numdgt=10 DVDT=4 LVLTIM=3 RMAX=5e-3
.OPTIONS NOWARN warnlimit=0
.param Freq =350k
.param Vac=0.0
.TRAN 10ns 200us START=100us SWEEP Freq 350k 1500k 10k
.print
vc=PAR(’(V(1)-V(2))’)
**main circuit
*vdd vdd 0 9
Vdgpw1 Vdd 0 PWL (0 0 1e-5 9 1meg)
C.2 Spice Netlist for Symmetric Circuit
77
Vs vs 0 SIN (0 Vac Freq)
Vdc vdc 0 7
R2 vi vdc 9.87e4
C2 vs vi 1e-6
E6 vs1 0 value=(’(V(Vdd)-V(vi)) ’)
R3 vim 0 9.87e4
C3 vs1 vim 1e-6
R1 1 3 234
L1 3 2 1.2468e-3
C1 1 2 7.5e-11
C4 1 0 110E-12
R3 1 0 200000
C5 2 0 110E-12
R4 2 0 200000
mp1 1
mp2 2
mn3 1
mn4 2
mn5 1
C6 vi
2 vdd vdd PMOSt L=10e-6 W=60e-6
1 vdd vdd PMOSt L=10e-6 W=60e-6
2 0 0 NMOSt L=10e-6 W=30e-6
1 0 0 NMOSt L=10e-6 W=30e-6
vi 2 0 NMOSt L=10e-6 W=30e-6
1 560e-12
mn6 1 vim 2 vdd PMOSt L=10e-6 W=60e-6
C7 vim 2 560e-12
* ---------------------------------------------------------------------.MODEL NMOSt NMOS LEVEL=1 GAMMA=0 XJ=0
+TOX=1200E-9 PHI=0.6 RS=0 KP=111E-6 VTO=2.0 LAMBDA=0.01
+RD=0 CBD=2.0E-12 CBS=2.0E-12 PB=0.8 CGSO=0.1E-12
+CGDO=0.1E-12 IS=16.64E-12 N=1 NSUB=5E+15
.MODEL PMOSt PMOS LEVEL=1 GAMMA=0 XJ=0
+TOX=1200E-9 PHI=0.6 RS=0 KP=55E-6 VTO=-1.5 LAMBDA=0.04
78
Spice Netlist and Matlab Code
+RD=0 CBD=4.0E-12 CBS=4.0E-12 PB=0.8 CGSO=0.2E-12
+CGDO=0.2E-12 IS=16.64E-12 N=1 NSUB=5E+15
* ---------------------------------------------------------------------.PROBE
.END
C.3
Matlab Post-Processing Code
%%%%%%%%%%%%
%%load spice
clc
clear all
range1 = [150 1 10150 1 ];
%range1 = [402 1 10402 1 ];
for j=1; %Vpp 0.1 0.3 0.5 0.7
for i = 1:115; %FreqInj
%
M{j,i} = dlmread(’foranalysis.lis’,’\t’,range1);
M{j,i}= dlmread(’00.lis’,’’,range1)
%
range1 = range1+[10015 0 10015 0 ] ; %3015=3157-157+15
end
range1 = range1 + [170 0 170 0];
end
save(’00.mat’, ’M’);
FreqInj = 350e3:10e3:1500e3; %input frequency############
Ts =10e-9;
Fs = 1/Ts;
for j=1;
for i = 1:115; %#########
TInj = 1/FreqInj(i);
a = M{j,i};
spectrumRaw = fft(a(:,1));
C.3 Matlab Post-Processing Code
freqArray = 0: (Fs/2)/(ceil(length(spectrumRaw)/2)-1)
79
: Fs/2;
[y1, y2] = max(abs(spectrumRaw(1:1:ceil(length(spectrumRaw)/2))));
f(j,i)=freqArray(y2);
Ratio(j,i)=FreqInj(i)/f(j,i)
end
end
save(’00.mat’, ’Ratio’);
%%%%%%%%COmbining Ratios%%%%%%%%%
clc
clear all
fid=fopen(’ratio.txt’,’wt’)
load 00.mat
for i=1:1:115
fprintf(fid,’%d
end
fprintf(fid, ’\n’)
\’,Ratio(i))
load 05.mat
for i=1:1:115
fprintf(fid,’%d
end
fprintf(fid, ’\n’)
\’,Ratio(i))
load 10.mat
for i=1:1:115
fprintf(fid,’%d
end
fprintf(fid, ’\n’)
\’,Ratio(i))
load 15.mat
for i=1:1:115
fprintf(fid,’%d
end
\’,Ratio(i))
%%%%%%%Ratio Plot%%%%%%%
%%%%%%%%%%%%%%%%%%%%%%%%
80
Spice Netlist and Matlab Code
%%%%
PLOT RATIO %%%%
%%%%%%%%%%%%%%%%%%%%%%%%
Ratio=load(’ratio.txt’)
FreqInj1 = 350e3:10e3:1500e3;%input frequency
y1= 0.0:0.5:2.5;
refineratio1=zeros(06,115);
for j=1:6;
for i=1:115;
if abs(Ratio(j,i)-2)<= 0.00001;
refineratio1(j,i)=2;
else
if abs(Ratio(j,i)-3)<= 0.000001;
refineratio1(j,i)=3;
end
end
end
end
figure
grid
axis([350e3 1100e3 0 2.5])
title(’Capacitor connected Single M5,including RLCL, 7V DC bias, ’,’FontSize’,
xlabel(’Frequency’,’FontSize’,13)
ylabel(’Amplitude’,’FontSize’,13)
hold on
for j =1:6;
for i = 1:115;
if refineratio1(j,i)==2;
plot(FreqInj1(i),y1(j),’-ko’)
else
if refineratio1(j,i)==3;
plot(FreqInj1(i),y1(j),’-ro’)
end
end
end
end