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Translinear Peak Detector Circuit for Sinusoidal Signal Wannaya Ngamkham*, Thip Manmek** and Chariya Wongtaychatham*** * Faculty of Electrical Engineering Mahanakorn University of Technology, Bangkok 10530 Thailand Email: [email protected] ** School of Electrical Engineering and Telecommunications The University of New South Wales Sydney 2052 Australia , Email: [email protected] *** Faculty of Engineering King Mongkut’s Institute of Technology Ladkrabang Bangkok 10520 Thailand, Email: [email protected] ABSTRACT This paper presents a design of a fast peak detector circuit for constant frequency sinusoidal signal based on the translinear principle. This detector is based on the concept of orthogonal function set. The proposed circuit has a very simple, compact structure and handles load changes quickly with fast response because no filtering circuit is used. It consists of a π/2 phase shifter, absolute value circuits, current mirrors and a block of squarer, adder and square-rooter. The last building block offers a markedly distinguished feature as it, in a very compact configuration, can perform several mathematical operations. To verify the theoretical analysis, the circuit simulation results are given. They show good agreement with the theory and operate within the frequency range of five decades. Inherently, the circuit is well suited for the IC implementation. Keywords: Peak detector, Translinear circuit. 1. INTRODUCTION A sinusoidal amplitude detector or peak detector finds a wide range of applications in instrumentation and power systems [1]-[3]. The purpose of a sinusoidal peak detector is to generate a dc output voltage which is proportional to the peak value of the input sinusoidal signal. Due to the waveforms of a power system, voltage and current are sinusoidal. The sinusoidal peak detector is broadly used in certain electrical equipment. A typical technique to design a peak detector employs, along with filtering circuits, opamps as the active elements [4], [6]. However, it may degrade the transient response of the sinusoidal peak detector. Hence, the transient performance of equipment that uses the typical technique can be improved by using the sinusoidal peak detector with fast transient response [5]. Therefore, the shortcomings are obviously a large configuration but a small operating frequency range and, not less importantly, a slow response due to the filtering. In this paper, new development of an analog peak detector is presented with the goal to alleviate the above problems. The proposed peak detector operates in the currentmode [6-9] with the bipolar transistors used as the active elements. The circuit consists of a π/2 phase shifter, two absolute value circuits, current mirrors and a building block of squarer, adder and square-rooter. The π/2 phase shifter, producing a cosine-signal from a sine input, incorporates with the absolute value circuits. Then, the output is supplied to a circuit performing multiple tasks of squaring, adding and square- rooting. The final output is the peak value of the input signal. The detailed circuit description will be given in the next section. In terms of frequency range, the proposed circuit operation covers a wide range of as many as five decades. In addition, the circuit has few passive components, and a simple structure. Therefore this is very suitable for the IC implementation. Because, this implementation is very straightforward and easily to apply application in many area such as power system area. The circuit performance has been verified by computer simulation. Satisfaction has been achieved due to close agreement between the simulation results and the theory as to be seen in Section 3. Vi(t) π Phase shifter 2 V ′i(t) Multiplier 2 Square rooter Vo(t) Multiplier 1 Fig.1: Basic principle to design a peak detector 2. CIRCUIT DESCRIPTION It should be informative to lay a background for the proposed development. It is to be done just that. Shown in Figure 1 is the basic diagram of the orthogonal peak detector reported in [10] which intends to operate in the voltage-mode From Figure1, let Vi(t) be a sinusoidal input signal, where Vi (t ) = A sin (ωt ) (1) Where A is the peak magnitude of the input voltage. When Vi(t) passes through the π/2 phase shifter, the following output is produced π Vi' (t ) = A sin ωt + 2 = A cos(ωt ) A 2 sin 2 (ωt ) + A2 cos 2 (ωt ) = A (3) From (3), the final output yields the input peak value as desired. In principle, the operation can be carried out in all four quadrants. However, for the sake of more simplicity, a slight modification is considered for the current-mode operation. As seen in Figure 2, a building block of absolute value circuits has been included. π Ii ( t ) = 2 phase shifter X = Acos(ωt ) A cos (ωt ) Absolute value circuits Asin(ωt ) Asin(ωt ) Z = X 2 +Y 2 Io(t)=A Y = Asin(ωt ) Fig. 2: Building block of current-mode peak detector A 2 sin(ωt ) + A 2 cos 2 (ωt ) = A (4) I bi The magnitude and phase of the above transfer function can be extracted, respectively, as follows jwCVT - 2 I bi =1 jwCVT + 2 I bi (6) CV ω ∠T ( jω ) = π − 2 tan −1 T 2 I bi (7) From (7), it is clear that the phase can be adjusted by varying the bias current. Therefore, a phase shift of π 2 radians can be achieved by choosing an appropriate choice Ibi. Then, for an input I i (t ) = A sin (ωt ) , the following output is obtained I i′(t ) = A cos(ωt ) I y (t ) = I i′(t ) = A cos(ωt ) (9) The other output Ix(t) is obtained in the same manner. I x (t ) = I i (t ) = A sin(ωt ) (10) +Vcc Q10 Q11 Q14 Q13 I (t) x Ib Ii(t) Q18 Q8 Q19 Q14 Q17 Q5 I′i(t) (5) (8) Both Ii(t) and I i′(t ) are then sent to the absolute value circuit [6]. One possibility is schematically shown in Figure4. The circuit operation can be easily described by first considering part of the circuit in the dashed-box. As usual, it is assumed that all the transistors possess the same current gains β , and β >> 1. Now when I i′(t ) in (8) is positive, the Wilson current mirror (Q5, Q6, Q7) will handle the output of Q10. When I i′(t ) is negative, the Darlington cascade (Q8, Q9) will convey the output current. This absolute-value version of I i′(t ) is then mirrored and shown in the figure as Iy(t) Q9 I ′(s ) sCVT − 2 I bi T (s ) = i = I i (s ) sCVT + 2 I bi I i′ (t ) Fig.3: All pass filter The diagram has a great variety of circuit realization. Possible realization of each block in the figure is to be discussed as follows. First, the realization of the phase shifter makes use of an all pass filter (APF) implemented with a second generation current controlled conveyor (CCCII) and a single capacitor [11]. The building block is shown in Figure 3. The transfer function, T(s), of this APF can be easily found as Z X I i (t ) For this current mode, the amplitude of the signal output is simply obtained and represented as follows I o (t ) = CCCII (2) Passing the input and its quadrature signal through all the mathematical operation blocks, namely the multiplier, adder and square-rooter to yield the following output Vo (t ) = Y C Q15 Q7 Q6 Q16 Fig. 4: Absolute value circuits Iy(t) The last section is shown is Figure5 acting, all in one, as multiplier, adder and square-rooter. With the usual assumptions of current gains and transistor matching condition, then applying the translinear principle results in the following relationship among the collector currents of Q1 - Q4 I o (t ) = IX Substitution of the above collector currents with those specified in Figure 5, where CM represents the building block of current mirror circuits, gives I X I X = ( I o − IY )( I o + IY ) = I o2 − IY2 Io-IY Q1 Io Q2 IY IY CM1 (12) 2IY Io+IY Rewriting (12) to obtain Io Q3 Q4 (13) I o = I X2 + IY2 Replacing Ix and Iy with those in (9) and (10) yields the final output Fig.5: Circuit performing I o = I X2 + IY2 +Vcc IX(t) Io(t) IY(t) Ib Ii(t) Z Y X Vo(t) Ii(t) R I′i(t) Ibi Absolute value circuits -Vcc Squarer, adder and squre-rooter circuit C π 2 Phase shifter cicuit Fig.6: Complete translinear peak detector 3. COMPUTER SIMULATION All the above configurations are used to realize a peak detector. The complete circuit is schematically shown in Figure 6. The circuit simulation employs the bipolar transistors having the same models as those used in [9]. Simulation with 1 Hz-sine wave inputs of 10 µA, 20 µA and 30 µA peak values and the bias current Ib = 10 µA gives the results shown in Figure 7. The three quite level traces of output currents demonstrate stable peak values. Then the high frequency inputs of 1 MHz with 1mA, 2mA and 3mA peak values and the bias current Ib =1mA are applied to the circuit. The results in Figure 8 illustrate similar reliable performance. (14) Therefore, the final output produces the peak value, A as expected. (11) Ic1 Ic3 = Ic2 Ic4 A 2 sin 2 (ωt ) + A 2 cos 2 (ωt ) Fig. 7: Simulation results for 1 Hz-input signals As can be seen from Figure 7 and Figure 8, it is clear that the theoretical principle hold for the operation in both very low and high frequencies. It means that the proposed method is insensitive to the frequency variation. easy to application in various areas such as power electronics area [12]. Notice that the derivation is achieved with the thermal voltage VT in the picture as seen in (6)-(8). However, there are a variety of methods to solve the problem. A simple one to compensate for the temperature sensitivity is given in [13]. 5. Fig. 8: Simulation results for 1 MHz-input signals For application in power system, the input current from 0-10mA produced by an ac voltage 220V, 50Hz under varying load resistance. Figure. 9 show the operation range of this detector. The solid line is its linearity characteristic in theory, and the dotted line is the simulation result. Fig.9: Linear characteristic of the proposed peak detector As can be seen from figure 9 the amplitude of varying current signal can be detected accurately and linearly. When the peak value of input current is very small, the output of the detector had error value. This inaccuracy value may be ensuing when the current bias in the circuit is very small. As a consequence the circuit cannot operate completely. 4. CONCLUSIONS A design of a peak detector circuit operating in the current-mode and employing the translinear principle is presented. The proposed peak detector based on the orthogonal method which has no filter. Thus, the transient response delay of this detector is less than one-fourth of cycle. The technique offers several advantages which support the IC implementation. These include a compact structure as well as remarkably accurate performance. The operating frequency range covers up to as many as five decades. Therefore, this circuit has a very small size which is REFERENCES [1] M. Zuffada, R. Alini, P. Colletti, et. al., “A singlechip 9-32 mb/s read/write channel for disk drive applications,” Solid-State Circuits, IEEE Journal of, vol. 30, pp.650-659, June 1995. [2] H. Eren,, J. Goh, “Signal extraction from magnetic flow meters for density measurements,” Instrumentation and Measurement Technology Conference, , IMTC/94 IEEE, vol. 3, pp.1213-1216, 1994 [3] M. S. Obaidat, and D. S. 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