Download EiceDRIVER™ 1EDI Compact Family

Ei ceD RI V ER™
High voltage gate driver IC
1EDI Com p act Fam il y
1200V single channel driver IC
1EDIxxI12AF, 1EDIxxN12AF, 1EDIxxI12MF
Application Note AN2014-06
BDTIC
About this document
Scope and purpose
This application note explains the general gate driver features in more detail and describes how to use them
in an application.
Intended audience
This document is intended for application circuit designers and concept engineers in power electronics.
Table of Contents
1
Introduction ............................................................................................................... 2
2
2.1
2.2
2.3
2.4
2.5
Input Features ............................................................................................................ 3
Input supply and under voltage lock out (UVLO) ............................................................................... 3
Pull-up and pull-down resistor for input signals ............................................................................... 4
Input signal filtering (active filter) ...................................................................................................... 4
VCC1 scaled input threshold voltage.................................................................................................. 5
Application usage of IN+ and IN- ........................................................................................................ 5
3
3.1
3.2
3.3
3.4
Output Features.......................................................................................................... 7
Output supply and under voltage lock out (UVLO) ............................................................................ 7
Active shutdown .................................................................................................................................. 7
Separate source/sink output variants ................................................................................................ 8
Combined output with clamp variants .............................................................................................. 8
4
4.1
4.2
4.3
Design Aspects .......................................................................................................... 10
Output supply capacitor selection ................................................................................................... 10
Gate resistor selection ...................................................................................................................... 10
Power dissipation estimation ........................................................................................................... 12
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1
Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Introduction
1
Introduction
The Infineon EiceDRIVER™ 1EDI Compact family consists of single channel high voltage gate driver ICs with
integrated Coreless Transformer (CLT) Technology and a maximum offset voltage of 1200 V.
The 1EDI Compact Driver ICs are available in a compact PG-DSO-8 (150 mil) package and provide either
separated source/sink outputs or a single output with an additional clamping function. The under voltage
lock out levels of this family are mainly designed for IGBT operation. There are two optimized products
available with levels for Power MOSFETs.
Table 1
1EDI Compact product family members
Product Name
Peak output current
(Source/Sink)
Output variant
Propagation
delay
Under voltage
lock out VCC2
(typ) ns
(off/on) V - Type
BDTIC
(min) A
(typ) A
1EDI05I12AF
0.5/0.5
0.95/0.9
Source/Sink
300
11.1/12.1 – IGBT
1EDI20I12AF
2.0/2.0
3.5/3.0
Source/Sink
300
11.1/12.1 – IGBT
1EDI40I12AF
4.0/4.0
7.0/6.0
Source/Sink
300
11.1/12.1 – IGBT
1EDI60I12AF
6.0/6.0
11/9.0
Source/Sink
300
11.1/12.1 – IGBT
1EDI10I12MF
1.0/1.0
1.75/1.5
Out/Clamp
300
11.1/12.1 – IGBT
1EDI20I12MF
2.0/2.0
3.5/3.0
Out/Clamp
300
11.1/12.1 – IGBT
1EDI30I12MF
3.0/3.0
5.5/4.5
Out/Clamp
300
11.1/12.1 – IGBT
1EDI20N12AF
2.0/2.0
3.5/3.0
Source/Sink
105
8.6/9.4 – MOS
1EDI60N12AF
6.0/6.0
11/9.0
Source/Sink
105
8.6/9.4 – MOS
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Application Note AN2014-06
2
Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Input Features
2
Input Features
This section describes the under voltage lock out for the input supply, pull-up and pull-down resistors of
logic inputs, signal filtering and the application usage of the input pins.
VCC1
1
IN+
2
UVLO
VCC1
GND1
input
filter
&
active
filter
TX
input
filter
BDTIC
Figure 1
IN-
3
GND1
4
Block diagram of input section
The gate driver IC input section consists of the following functional blocks

input under voltage lock out circuit

signal filtering

pull-up resistor for inverting-input

pull-down resistor for non-inverting-input

signal transmission to isolated output section
2.1
Input supply and under voltage lock out (UVLO)
The input supply range has absolut maximum ratings of -0.3 V to 18 V. Static operation beyond these
voltages damages internal structures and is therefore considered a forbidden area.
VVCC1
forbidden area
abs max
op max
operating area
VUVLOH1
VUVLOL1
off
t
Figure 2
Input supply areas and UVLO threshold
At a crossing of the VUVLOH1 threshold during a positive ramp at VCC1 pin the input section starts to operate by
evaluating the input signals IN+ and IN- and transmits their current state to the output section. During VVCC1
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Application Note AN2014-06
3
Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Input Features
ramp down and crossing of the VUVLOL1 threshold the input section will send a final off signal regardless of the
IN+ or IN- state. VUVLOL1 and VUVLOH1 form a hysteresis which offers stable operation even at low levels.
Any voltage overshoot above the absolute maximum limit can damage the driver circuits. In this area, the
current consumption increases dramatically and in combination with the voltage at that point it results in a
violation of the maximum allowed input power loss.
2.2
Pull-up and pull-down resistor for input signals
The input pull-up or pull-down resistors ensure an off state in case the corresponding input is not
connected. These resistors have a minimum value of 25 kΩ. Even with the maximum allowed voltage at
VCC1 pin the input current due to these resistors stays below 1 mA.
The pull-up and pull-down resistors are designed to be connected to an external supply or ground potential
for permanent activation of the individual driver input.
BDTIC
2.3
Input signal filtering (active filter)
The input section of the driver IC implements a signal filtering on both input signal pins to suppress short
pulses triggered by external influence.
tPDOFF
tPDOFF
tIN+>tMININ+
tIN+<tMININ+
IN+
tIN->tMININ-
tIN-<tMININ-
IN-
OUT
tPDON
Figure 3
tPDON
Input pulse suppression and turn-on / turn-off propagation delay
Every pulse at IN+ shorter than tMININ+ will be filtered and is not transmitted to the output chip. Longer pulses
will be sent to the output with the shown propagation delay tPDON and tPDOFF. The same behavior is
implemented at IN-. Every pulse shorter than tMININ- will be omitted and longer pulses transmitted with the
same propagation delay. The 1EDI Compact family offers two dedicated input filter times resulting also in
two different propagation delay times.
Table 2
Typical filter and propagation delay times
Product name
Input filter time (typ)
tMININ+,tMININ-
Propagation delay time (typ)
tPDON, tPDOFF
1EDI05I12AF, 1EDI20I12AF, 1EDI40I12AF,
1EDI60I12AF, 1EDI10I12MF, 1EDI20I12MF,
1EDI30I12MF
240 ns
300 ns
1EDI20N12AF, 1EDI60N12AF
45 ns
105 ns
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Application Note AN2014-06
4
Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Input Features
2.4
VCC1 scaled input threshold voltage
The threshold voltages of both input pins IN+ and IN- are scaled with the voltage level of VVCC1 allowing an
operating range of 3 V to 17 V.
VIN,L
VIN,H
VIN,H,15V
10
VVCC1,max
UVLO
No driver
operation
BDTIC
5
VIN,L,15V
VIN,H,5V
VIN,L,5V
Figure 4
15
10
5
VCC1
VCC1 scaled input threshold voltage of IN+ and IN-
Beginning from the input under voltage lock out level, threshold levels for IN+ and IN- are scaled to VVCC1. The
typical high input threshold is 70 % of VVCC1 and the low input threshold is at 30 % of VVCC1.
The inputs are always rated up to 17 V even if the VCC1 pin is supplied with a lower voltage level. In this
mode the input currents are up to 30 % higher than the maximum specified values of the data sheet.
2.5
Application usage of IN+ and IN-
Having an inverting and a non-inverting input signal brings advantages to the vast application possibilities.
A
B
VCC1
IN - LVDS
IN+
EN
IN-
/IN
VCC1
IN+
GND1
C
IN
Figure 5
IN HS
VCC1
IN+
IN-
IN-
GND1
GND1
VCC1
VCC1
IN+
SD
D
IN LS
IN+
IN-
IN-
GND1
GND1
Input IN+ and IN- usage
Apart from using both inputs with a differential signal (A) (VCC1 and GND1 levels) using only one input signal
for actual switch control leaves the second input available for functions like Enable (B), Shutdown (C) or
Interlock (D).
A) Differential signal
Applying a logic level differential signal on both IN+ and IN- with the positive level of VCC1 pin and the
negative level of GND1 pin improves common mode noise rejection.
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Application Note AN2014-06
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Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Input Features
B) Enable
Using the IN+ pin as enable signal leaves the IN- to control the output PWM with an inverted logic input
signal. The enable signal can be shared between gate driver ICs of a complete inverter to start operation
with a single control signal.
C) Shutdown
Using the IN- pin as shutdown signal leaves the IN+ to control the output PWM with a non-inverted logic
input signal. The shutdown signal can be shared between gate driver ICs of a complete inverter to interrupt
operation with a single control signal.
D) Interlock
Interlocking is often used in half bridge configuration to avoid a shoot through current from the high voltage
DCbus supply. Connecting the following input signal pins of the top and bottom driver IC together inhibits a
static turn on on both channels at the same time.
BDTIC

top driver non-inverting input (IN+) with the bottom driver inverting input (IN-)

bottom driver non-inverting input (IN+) with the top driver inverting input (IN-)
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Application Note AN2014-06
6
Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Output Features
3
Output Features
This section describes the gate driver output section of the variants with separate source/sink outputs and
variants with output and active miller clamp functionality.
3.1
Output supply and under voltage lock out (UVLO)
The output supply range has a positive absolute maximum rating of 35 V for separate output variants and
20 V for variants with active miller clamp function. Separate output variants are therefore capable of
providing a bipolar gate voltage to a connected power switch.
Table 3
Output under voltage lock out voltage threshold levels
BDTIC
Parameter
Symbol
Value
Unit
IGBT variant maximum turn on level
VUVLOH2,IGBT
12.7
V
IGBT variant minimum turn off level
VUVLOL2,IGBT
10.5
V
MOS/GaN variant maximum turn on level
VUVLOH2,MOS
10.0
V
MOS/GaN variant minimum turn off level
VUVLOL2,MOS
8.0
V
Under voltage lock out thresholds are depending on the power switch optimization of the gate driver
variant either IGBT or MOS based, but do not limit the functionality to these components.
3.2
Active shutdown
The active shutdown function is a protection feature of the driver. It is designed to avoid a free floating gate
of a connected power switch to trigger a turn on. An external RGE usually covers this protection. The active
shutdown function is implemented in all variants and renders the use of this external resistor unnecessary.
VCC2 (not supplied)
5
UVLO
&
RX
OUT+
RGON
OUT-
RGOFF
6
Shoot
through
protection
simplyfied active
shutdown circuit
7
RGE
GND2
8
Figure 6
Block diagram of separate output variant showing active shutdown
In case of supply voltage failure at the VCC2 pin, the output section of the driver operates in the active
shutdown mode. Then the driver uses the floating voltage of the connected gate to supply this internal
circuit. The maximum pull down current in this mode is approx. 10 % of the rated output current of the
individual driver variant. This solution is by far stronger than an otherwise used RGE.
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Application Note AN2014-06
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Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Output Features
3.3
Separate source/sink output variants
With separated outputs for current sourcing and sinking in a gate driver IC individual gate resistors can be
used for turning a power switch on and off.
+5V
VCC1
+15V
VCC2
1µ
10R
100n
OUT+
SGND
GND1
IN
3R3
IN+
OUT-
IN-
GND2
BDTIC
Figure 7
Circuit example for separate output variants
This configuration saves a bypass diode for each power switch used. It also helps reducing the gate loop by
minimizing the number of components between the gate driver and the power switch. It minimizes as well
the required PCB space. An additional benefit of two separated gate resistors is the power loss distribution.
Because each of the two resistors are only active during turn on or turn off the power loss in each individual
resistor is also only half compared to a single gate resistor solution.
+5V
VCC1
+15V
VCC2
1µ
100n
10R
OUT+
SGND
GND1
IN
Figure 8
3R3
IN+
OUT-
IN-
GND2
1µ
-8V
0V
Circuit example for separate output variants for bipolar supply
The variants with separate outputs are also able to operate upto 35 V between VCC2 and GND2 pins. This
allowes a gate switching with for example 0 V to + 15 V, -8 V to + 15 V or – 15 V to + 15 V. The connection of
any voltage supply needs to connect the positive voltage to VCC2 pin, the negative voltage to GND2 pin and
the reference supply pin to the emitter of an IGBT. This common ground level is then unknown to the driver
IC and therefore the UVLO protection is referenced to the negative supply.
3.4
Combined output with clamp variants
In these variants a common output for turn-on and turn-off is combined with a separate pin for active miller
clamping. They are also optimized for single supply voltage of up to 20 V between VCC2 and GND2 pins.
+5V
VCC1
1µ
100n
10R
SGND
OUT
GND1
IN
Figure 9
+15V
VCC2
IN+
CLAMP
IN-
GND2
Circuit example for clamp variants
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Application Note AN2014-06
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Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Output Features
The active miller clamping function reduces the risk of a parasitic turn on during a high dvCE/dt transition at
the connected IGBT. Displacement currents through the intrinsic gate-collector (Cgc) and gate-emitter (Cge)
capacitances can lead to a voltage increase at vGATE. If the voltage reaches the IGBT threshold a dynamic turn
on of the power switch occurs. It stays on until the regular discharge path through RG can reduce the gate
voltage again.
VCC2
5
Cgc
dvCE
dt
OUT
VCC2
6
RG
BDTIC
To
logic
2V
From logic
CLAMP
7
Cge
vGATE
GND2
8
1EDI-MF
Figure 10
Output block diagram for clamp variants
The implemented clamp function of the 1EDI Compact monitors the gate voltage during driver off state. It
activates the additional discharge path between CLAMP and GND2 as soon as the gate voltage is discharged
below 2 V. The clamping circuit stays active until the driver is turned on again. Optimize the circuit layout for
low inductance routing between gate and CLAMP pin to achieve the most effective clamping result.
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Application Note AN2014-06
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Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Design Aspects
4
Design Aspects
This section describes aspects of gate resistor and output supply capacitor selection. It also covers a power
dissipation estimation for a selected design.
4.1
Output supply capacitor selection
A general design rule for the location of the driver output supply capacitor is always to place it as close to
the IC as possible. Additionally the value of the capacitor needs to be big enough to limit the voltage drop
during the power switch turn on. To calculate a first approximation for this capacitor value, use the
following equation:
BDTIC
𝐶2 =
𝐼𝑄2 ∙ 𝑡𝑝 + 𝑄𝐺
∙ 1.2
∆𝑉𝐶𝐶
(1)
IQ2 is the gate driver supply current, tP the periode of the switching frequency, QG the total gate charge at the
selected operating condition and ΔVCC the maximum allowable voltage variation. The additional margin of
20 % covers typical tolerances of capacitor and gate charge parameter.
Calculating this for the 100 A Module FP100R12KT4 with QG = 800 nC, a switching frequency of fsw = 15 kHz
and an acceptable voltage variation of ΔVCC = 0.5 V results in
2𝑚𝐴 ∙ 67µ𝑠 + 800𝑛𝐶
∙ 1.2;
500𝑚𝑉
𝐶2 = 2.24µ𝐹
𝐶2 =
4.2
(2)
Gate resistor selection
To optimize the gate resistor selection it is recommended to have the appropriate gate charge diagram of
the used IGBT and the output characteristic of the gate driver ready. Both diagrams are depending on
operation conditions such as DC-link voltage (VDC), collector current (IC) and operating temperature. The
following representational diagrams show typical behaviors of an IGBT and the 1EDI Compact driver output
without scale. The MOSFET based gate driver outputs can be simplified as dynamic resistors (rDS,source ; rDS,sink)
with a voltage drop (VDS,source; VDS,sink) during switching. The total gate charge (QG) and the Miller charge (QM)
can be extracted from the gate charge diagram using the given gate driver supply V(VCC2-GND2) and DC-link
voltage.
VCC2
VDC
VCC2 level
VDS,source
rDS,source
CGC
rDS
VMiller
T1
RG,ON IG,source
QM
OUT+
OUT-
QG
RG,OFF IG,sink
rDS,sink
IG
VGE
VDS,sink
CGE
VGE
VCC2-GND2
IC
GND2 level
GND2
level
GND2
Figure 11
Q
VCC2
level
V
Simplyfied gate circuit, IGBT gate charge diagram and driver output characteristic
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Application Note AN2014-06
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Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Design Aspects
In the initial phase of an IGBT turn on event the gate is discharged and at the level of the GND2 pin. This is
marked with (1) in the figure below. Therefore the total gate supply voltage is split between the inner gate
driver resistance (rDS,source) and the turn on gate resistor (RG,ON). The graphical solution show the initial gate
current (IG(1)). This maximum current can also be used to select the appropriate pulse current class for the
gate resistor.
VCC2
VDC
VCC2 level
VDS,source
rDS,source
CGC
rDS
VMiller
(1)
T1
RG,ON IG,source
OUT+
OUT-
IG
VGE
IG(1)
QM
QG
VG
RG(VCC2)
rDS,sink
VDS,sink
VCC2-GND2
IC
CGE
VGE
(1)
Q
VDS
GND2 level
GND2
level
GND2
Figure 12
VRG
VGE = 0V
BDTIC
RG,OFF IG,sink
VCC2
level
V
Simplyfied gate circuit turn on event: Initial phase
Immediately after the initial phase the gate current starts to fall, following the crossing point of the output
characteristic curve and the parallel translated gate resistor line while the gate-emitter voltage (VGE) charges
up.
VCC2
VDC
VCC2 level
VDS,source
rDS,source
CGC
VDS,sink
(2)
IG(1)
QM
QG
VG
RG,OFF IG,sink
rDS,sink
rDS
VMiller (2)
T1
RG,ON IG,source
OUT+
OUT-
IG
VGE
CGE
VCC2-GND2
IC
VGE
Q
RG(VCC2-VM)
GND2 level
VDS
GND2
level
GND2
Figure 13
RG(VCC2)
IG(2)
VRG
VGE = VMiller
VCC2 - VMiller
VCC2
level
V
Simplyfied gate circuit turn on event: at Miller plateau
Beginning with the Miller plateau, marked with (2) above, the gate-emitter voltage remains nearly constant
while the transistor is reducing the collector-emitter voltage to its saturation level. Given the condition at
that phase the resulting gate current is constant, allowing a collector-emitter voltage transition time (tON)
calculation with the following formula:
(𝑅𝐺,𝑂𝑁 + 𝑟𝐷𝑆,𝑠𝑜𝑢𝑟𝑐𝑒(2) )
∙ 𝑄𝑀
(𝑉𝐶𝐶2 − 𝑉𝑀 )
1
=
∙𝑄
𝐼𝐺(2) 𝑀
𝑡𝑂𝑁 =
𝑡𝑂𝑁
(3)
Tuning the value of a gate resistor requires extensive knowledge of all the parasitics in the gate circuit. It is
therefore an iterative process of adjusting between switching losses and EMI.
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Application Note AN2014-06
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1EDI Compact Family
1200V single channel driver IC
Design Aspects
4.3
Power dissipation estimation
Apart from the power losses in the gate resistor during switching of any power switch, there is also
considerable power loss inside the driver IC. Every package can achive a maximum power dissipation at a
certain operating condition without violating the maximum junction temperature. The internal power loss
of the output section (POUT) of the 1EDI Compact driver can be estimated as follows:
𝑃𝑂𝑈𝑇 = 𝑃𝑄 + 𝑃𝑠𝑜𝑢𝑟𝑐𝑒 + 𝑃𝑠𝑖𝑛𝑘
(4)
PQ is the operating power loss of the driver output stage. It is easily calculated by the operating supply
current (IQ2) and the supply voltage between VCC2 and GND2 pins:
𝑃𝑄 = 𝐼𝑄2 ∙ (𝑉𝐶𝐶2 − 𝐺𝑁𝐷2)
(5)
BDTIC
The turn-on (Psource) and turn-off (Psink) losses can be estimated using the resistive voltage divider between
inner gate driver resistance (RDS) and outer gate resistor (RG) with the total gate charge (QG) and switching
frequency (fsw):
𝑅𝐷𝑆,𝑠𝑜𝑢𝑟𝑐𝑒
𝑅𝐷𝑆.𝑠𝑜𝑢𝑟𝑐𝑒 + 𝑅𝐺,𝑂𝑁
𝑅𝐷𝑆,𝑠𝑖𝑛𝑘
1
= 2𝑄𝐺 ∙ 𝑓𝑠𝑤 ∙ (𝑉𝐶𝐶2 − 𝐺𝑁𝐷2) ∙
𝑅𝐷𝑆.𝑠𝑖𝑛𝑘 + 𝑅𝐺,𝑂𝐹𝐹
1
𝑃𝑠𝑜𝑢𝑟𝑐𝑒 = 2𝑄𝐺 ∙ 𝑓𝑠𝑤 ∙ (𝑉𝐶𝐶2 − 𝐺𝑁𝐷2) ∙
𝑃𝑠𝑖𝑛𝑘
(6)
The inner gate driver resistance for the 1EDI family members can be selected from the following table:
Table 4
Gate driver output resistance
Driver type
RDS,source output resistance
RDS,sink output resistance
Typ []
worst case []
typ []
worst case []
1EDI60I12AF
0.75
1.4
0.75
1.7
1EDI40I12AF
1.13
2.2
1.13
2.7
1EDI20I12AF
2.25
4.3
2.25
5.0
1EDI05I12AF
9.00
16
9.00
17
1EDI30I12MF
1.50
2.8
1.50
3.4
1EDI20I12MF
2.25
4.3
2.25
5.0
1EDI10I12MF
4.50
8.6
4.50
10
1EDI60N12AF
0.75
1.4
0.75
1.7
1EDI20N12AF
2.25
4.3
2.25
5.0
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Application Note AN2014-06
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Rev 1.01, 2014-10-23
1EDI Compact Family
1200V single channel driver IC
Design Aspects
References
[1] Infineon Technologies: Datasheet; 1EDIxxI12AF, 1EDIxxN12AF, 1EDIxxI12MF; Infineon Technologies,
Germany
[2] Infineon Technologies: Application Note; Gate resistor for power devices; Infineon Technologies,
Germany
[3] Dokuments and product information www.infineon.com/eicedriver-compact
Revision History
BDTIC
Major changes since the last revision
Page or Reference
Description of change
all
Initial version
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BDTIC
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AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolGaN™, CoolMOS™, CoolSET™, CoolSiC™, CORECONTROL™, CROSSAVE™, DAVE™, DI-POL™, DrBLADE™,
EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, ISOFACE™, IsoPACK™, iWafer™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OPTIGA™, OptiMOS™, ORIGA™, POWERCODE™, PRIMARION™, PrimePACK™,
PrimeSTACK™, PROFET™, PRO-SIL™, RASIC™, REAL3™, ReverSave™, SatRIC™, SIEGET™, SIPMOS™, SmartLEWIS™, SOLID FLASH™, SPOC™, TEMPFET™,
thinQ!™, TRENCHSTOP™, TriCore™.
Other Trademarks
Advance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM
Limited, UK. ANSI™ of American National Standards Institute. AUTOSAR™ of AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CATiq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of
Microsoft Corporation. HYPERTERMINAL™ of Hilgraeve Incorporated. MCS™ of Intel Corp. IEC™ of Commission Electrotechnique Internationale. IrDA™ of
Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of
Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc.,
USA. muRata™ of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies,
Inc. Openwave™ of Openwave Systems Inc. RED HAT™ of Red Hat, Inc. RFMD™ of RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of
Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA,
Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence
Design Systems, Inc. VLYNQ™ of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex
Limited.
Last Trademarks Update 2014-07-17
www.infineon.com
Edition 2014-10-23
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2014 Infineon Technologies AG.
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