Download THS4509-Q1

THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
WIDEBAND LOW-NOISE LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIER
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Fully Differential Architecture
Centered Input Common-Mode Range
Minimum Gain of 2 V/V (6 dB)
Bandwidth: 1900 MHz
Slew Rate: 6600 V/µs
1% Settling Time: 2 ns
HD2: –75 dBc at 100 MHz
HD3: –80 dBc at 100 MHz
OIP2: 73 dBm at 70 MHz
OIP3: 37 dBm at 70 MHz
Input Voltage Noise: 1.9 nV/√Hz (f > 10 MHz)
Noise Figure: 17.1 dB
Output Common-Mode Control
Power Supply:
– Voltage: 3 V (±1.5 V) to 5 V (±2.5 V)
– Current: 37.7 mA
Power-Down Capability: 0.65 mA
APPLICATIONS
•
•
•
•
5-V Data Acquisition Systems High Linearity
ADC Amplifier
Wireless Communication
Medical Imaging
Test and Measurement
RELATED PRODUCTS
DEVICE
THS4509
MINIMUM
GAIN
COMMON-MODE
RANGE OF INPUT(1)
6 dB
0.75 V to 4.25 V
DESCRIPTION
The THS4509 is a wideband, fully differential
operational
amplifier
designed
for
5-V
data-acquisition systems. It has very low noise at
1.9 nV/√Hz, and extremely low harmonic distortion of
–75-dBc HD2 and –80-dBc HD3 at 100 MHz with
2 Vpp, G = 10 dB, and 1-kΩ load. Slew rate is very
high at 6600 V/µs and with settling time of 2 ns to 1%
(2-V step), it is ideal for pulsed applications. It is
designed for minimum gain of 6 dB but is optimized
for gain of 10 dB.
To allow for dc coupling to analog-to-digital
converters (ADCs), its unique output common-mode
control circuit maintains the output common-mode
voltage within 3-mV offset (typ) from the set voltage,
when set within 0.5 V of mid-supply, with less than
4-mV differential offset voltage. The common-mode
set point is set to mid-supply by internal circuitry,
which may be overdriven from an external source.
The input and output are optimized for best
performance with their common-mode voltages set to
mid-supply. Along with high-performance at low
power-supply voltage, this makes for extremely
high-performance single-supply 5-V data-acquisition
systems. The combined performance of the THS4509
in a gain of 10 dB driving the ADS5500 ADC,
sampling at 125 MSPS, is 81-dBc SFDR and
69.1-dBc SNR with a –1-dBFS signal at 70 MHz.
The THS4509 is offered in a quad 16-pin leadless
QFN package (RGT) and is characterized for
operation over the full automotive temperature range
from –40°C to 125°C.
morF
05 Ω
ecruoS
VNI 001
(1) Assumes a 5-V single-ended power supply
8.96
Ω
843
Ω
V 5.2
Ω
784
001
22.0
9.94
µ F
Ω
8.96
9054 SHT
Ω
Ω
784
MC
Ω
Ω 3.65
1:1
Ω
TV
UO
05To
tseT
tnempiuqE
Ω
nepO
V 5.2−
843
Ω
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.BDTIC.com/TI
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
QFN – RGT
ORDERABLE PART NUMBER
Reel of 3000
TOP-SIDE MARKING
THS4509QRGTRQ1
OOSQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VS– to VS+
Supply voltage
6V
VI
Input voltage
±VS
VID
Differential input voltage
IO
Output current
4V
(1)
200 mA
Continuous power dissipation
See Dissipation Rating Table
TJ
Maximum junction temperature
TA
Operating free-air temperature range
–40°C to 125°C
Tstg
Storage temperature range
–65°C to 150°C
ESD ratings
(1)
150°C
Human-Body Model (HBM)
2000 V
Charged-Device Model (CDM)
1500 V
Machine Model (MM)
100 V
The THS4509 incorporates a (QFN) exposed thermal pad on the underside of the chip. This acts as a heatsink and must be connected
to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature, which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about
utilizing the QFN thermally enhanced package.
DISSIPATION RATINGS
2
PACKAGE
θJC
θJA
RGT (16)
2.4°C/W
39.5°C/W
POWER RATING
TA ≤ 25°C
TA = 85°C
2.3 W
225 mW
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
DEVICE INFORMATION
EGAKCAP TGR
)WEIV POT(
V–S
61
51
41
31
CN
1
21
V
–NI
2
11
V
+NI
3
01
–TV
UO
+TV
UO
MC
4
9
5
6
7
DP
MC
8
V+S
TERMINAL FUNCTIONS
TERMINAL
NAME
DESCRIPTION
NO.
NC
1
No internal connection
VIN–
2
Inverting amplifier input
VOUT+
3
Noninverted amplifier output
CM
4,9
Common-mode voltage input
VS+
5, 6, 7, 8
Positive amplifier power-supply input
VOUT–
10
Inverted amplifier output
VIN+
11
Noninverting amplifier input
PD
12
Power down, PD = logic low puts part into low-power mode, PD = logic high or open for normal operation
VS–
13, 14, 15, 16
Negative amplifier power supply input
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
3
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
SPECIFICATIONS, VS+ – VS– = 5 V
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, G = 10 dB, CM = open, VO = 2 Vpp, RF = 349 Ω,
RL = 200 Ω differential, TA = 25°C, single-ended input, differential output, input and output referenced to mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC Performance
Small-signal bandwidth
G = 6 dB, VO = 100 mVpp
2.0
G = 10 dB, VO = 100 mVpp
1.9
G = 14 dB, VO = 100 mVpp
600
G = 20 dB, VO = 100 mVpp
275
Gain-bandwidth product
G = 20 dB
Bandwidth for 0.1-dB flatness
G = 10 dB, VO = 2 Vpp
Large-signal bandwidth
G = 10 dB, VO = 2 Vpp
Slew rate (differential)
Rise time
Fall time
2-V step
Settling time to 1%
Settling time to 0.1%
f = 10 MHz
Second-order harmonic distortion
Third-order harmonic distortion
MHz
3
GHz
300
MHz
1.5
GHz
6600
V/µs
0.5
ns
0.5
ns
2
ns
10
ns
–104
f = 50 MHz
–80
f = 100 MHz
–68
f = 10 MHz
–108
f = 50 MHz
–92
f = 100 MHz
dBc
C
dBc
–81
Second-order intermodulation distortion
200-kHz tone spacing,
RL = 499 Ω
fC = 70 MHz
fC = 140 MHz
–64
Third-order intermodulation distortion
200-kHz tone spacing,
RL = 499 Ω
fC = 70 MHz
–95
fC = 140 MHz
–78
200-kHz tone spacing,
RL = 100 Ω, referenced to
50-Ω output
fC = 70 MHz
78
Second-order output intercept point
fC = 140 MHz
58
200-kHz tone spacing,
RL = 100 Ω, referenced to
50-Ω output
fC = 70 MHz
43
Third-order output intercept point
fC = 140 MHz
38
1-dB compression point
GHz
–78
fC = 70 MHz
12.2
fC = 140 MHz
10.8
dBc
dBc
dBm
dBm
dBm
Noise figure
50-Ω system, 10 MHz
17.1
dB
Input voltage noise
f > 10 MHz
1.9
nV/√Hz
Input current noise
f > 10 MHz
2.2
pA/√Hz
DC Performance
Open-loop voltage gain (AOL)
68
Input offset voltage
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
Average offset current drift
(1)
4
dB
TA = 25°C
1
4
mV
TA = –40°C to 125°C
1
5
mV
TA = –40°C to 125°C
2.6
TA = 25°C
8
15.5
TA = –40°C to 125°C
8
18.5
TA = –40°C to 125°C
20
TA = 25°C
1.6
3.6
TA = –40°C to 125°C
1.6
7
TA = –40°C to 125°C
4
C
A
V/°C
B
A
A
nA/°C
B
A
A
nA/°C
B
Test levels: A = 100% tested at 25°C, overtemperature limits by characterization and simulation; B = Limits set by characterization and
simulation; C = Typical value only for information.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
SPECIFICATIONS, VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, G = 10 dB, CM = open, VO = 2 Vpp, RF = 349 Ω,
RL = 200 Ω differential, TA = 25°C, single-ended input, differential output, input and output referenced to mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
Input
Common-mode input range high
1.75
Common-mode input range low
–1.75
Common-mode rejection ratio
V
90
B
dB
Differential input impedance
1.35 || 1.77
MΩ || pF
C
Common-mode input impedance
1.02 || 2.26
MΩ || pF
C
Output
Maximum output voltage high
Each output with 100 Ω to TA = 25°C
mid-supply
TA = –40°C to 125°C
Minimum output voltage low
Each output with 100 Ω to TA = 25°C
mid-supply
TA = –40°C to 125°C
Differential output voltage swing
1.2
1.4
1.1
1.4
4.8
TA = –40°C to 125°C
V
–1.4
–1.2
–1.4
–1.1
5.6
A
V
V
4.4
Differential output current drive
RL = 10 Ω
96
mA
Output balance error
VO = 100 mV, f = 1 MHz
–49
dB
Closed-loop output impedance
f = 1 MHz
0.3
Ω
Small-signal bandwidth
700
MHz
Slew rate
110
V/µs
1
V/V
mV
C
Output Common-Mode Voltage Control
Gain
Output common-mode offset
from CM input
1.25 V < CM < 3.5 V
5
CM input bias current
1.25 V < CM < 3.5 V
±40
CM input voltage range
–1.5 to 1.5
CM input impedance
V
23 || 1
CM default voltage
C
A
kΩ || pF
0
V
Power Supply
Specified operating voltage
3
Maximum quiescent current
Minimum quiescent current
5
5.25
TA = 25°C
37.7
40.9
TA = –40°C to 125°C
37.7
41.9
TA = 25°C
34.5
37.7
TA = –40°C to 125°C
33.5
37.7
Power-supply rejection (PSRR)
Power Down
V
mA
A
mA
90
dB
Enable voltage threshold
Assured on above 2.1 V + VS–
>2.1 + VS–
V
Assured off below 0.7 V + VS–
<0.7 + VS–
V
Input bias current
C
Referenced to Vs–
Disable voltage threshold
Powerdown quiescent current
C
TA = 25°C
0.65
0.9
TA = –40°C to 125°C
0.65
1
PD = VS–
Input impedance
100
50 || 2
mA
Measured to output on
55
ns
Turn-off time delay
Measured to output off
10
s
www.BDTIC.com/TI
Submit Documentation Feedback
Product Folder Link(s): THS4509-Q1
A
A
kΩ || pF
Turn-on time delay
Copyright © 2008, Texas Instruments Incorporated
C
C
5
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
SPECIFICATIONS, VS+ – VS– = 3 V
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, G = 10 dB, CM = open, VO = 1 Vpp, RF = 349 Ω,
RL = 200 Ω differential, TA = 25°C, single-ended input, differential output, input and output referenced to mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
AC Performance
Small-signal bandwidth
G = 6 dB, VO = 100 mVpp
1.9
G = 10 dB, VO = 100 mVpp
1.6
G = 14 dB, VO = 100 mVpp
625
G = 20 dB, VO = 100 mVpp
260
Gain-bandwidth product
G = 20 dB
Bandwidth for 0.1-dB flatness
G = 10 dB, VO = 1 Vpp
Large-signal bandwidth
G = 10 dB, VO = 1 Vpp
Slew rate (differential)
Rise time
Fall time
2-V step
Settling time to 1%
Settling time to 0.1%
f = 10 MHz
Second-order harmonic distortion
Third-order harmonic distortion
MHz
3
GHz
400
MHz
1.5
GHz
3500
V/µs
0.25
ns
0.25
ns
1
ns
10
ns
–107
f = 50 MHz
–83
f = 100 MHz
–60
f = 10 MHz
–87
f = 50 MHz
–65
f = 100 MHz
dBc
C
dBc
–54
Second-order intermodulation distortion
200-kHz tone spacing,
RL = 499 Ω
fC = 70 MHz
fC = 140 MHz
–54
Third-order intermodulation distortion
200-kHz tone spacing,
RL = 499 Ω
fC = 70 MHz
–77
fC = 140 MHz
–62
Second-order output intercept point
200-kHz tone spacing
RL = 100 Ω
fC = 70 MHz
72
fC = 140 MHz
52
Third-order output intercept point
200-kHz tone spacing
RL = 100 Ω
fC = 70 MHz
1-dB compression point
GHz
fC = 140 MHz
–77
38.5
30
fC = 70 MHz
2.2
fC = 140 MHz
0.25
dBc
dBc
dBm
dBm
dBm
Noise figure
50-Ω system, 10 MHz
17.1
dB
Input voltage noise
f > 10 MHz
1.9
nV/√Hz
Input current noise
f > 10 MHz
2.2
pA/√Hz
DC Performance
Open-loop voltage gain (AOL)
Input offset voltage
TA = 25°C
Average offset voltage drift
Input bias current
TA = 25°C
Average bias current drift
Input offset current
Average offset current drift
(1)
6
TA = –40°C to 125°C
68
dB
1
mV
2.6
V/°C
6
A
TA = –40°C to 125°C
20
nA/°C
TA = 25°C
1.6
TA = –40°C to 125°C
4
C
A
nA/°C
Test levels: A = 100% tested at 25°C, overtemperature limits by characterization and simulation; B = Limits set by characterization and
simulation; C = Typical value only for information.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
SPECIFICATIONS, VS+ – VS– = 3 V (continued)
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, G = 10 dB, CM = open, VO = 1 Vpp, RF = 349 Ω,
RL = 200 Ω differential, TA = 25°C, single-ended input, differential output, input and output referenced to mid-supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TEST
LEVEL (1)
Input
Common-mode input range high
0.75
V
Common-mode input range low
–0.75
V
Common-mode rejection ratio
80
B
dB
Differential input impedance
1.35 || 1.77
MΩ || pF
C
Common-mode input impedance
1.02 || 2.26
MΩ || pF
C
Output
Maximum output voltage high
Each output with 100 Ω to
mid-supply
TA = 25°C
0.45
V
Minimum output voltage low
Each output with 100 Ω to
mid-supply
TA = 25°C
–0.45
V
1.8
V
Differential output voltage swing
Differential output current drive
RL = 10 Ω
50
mA
Output balance error
VO = 100 mV, f = 1 MHz
–49
dB
Closed-loop output impedance
f = 1 MHz
0.3
Ω
570
MHz
60
V/µs
1
V/V
mV
C
Output Common-Mode Voltage Control
Small-signal bandwidth
Slew rate
Gain
Output common-mode offset
from CM input
1.25 V < CM < 3.5 V
4
CM input bias current
1.25 V < CM < 3.5 V
±40
CM input voltage range
–1.5 to 1.5
CM input impedance
20 || 1
CM default voltage
C
A
V
kΩ || pF
0
V
3
V
Power Supply
Specified operating voltage
Quiescent current
TA = 25°C
Power-supply rejection (PSRR)
34.8
mA
A
70
dB
C
V
Power Down
Referenced to Vs–
Enable voltage threshold
Assured on above 2.1 V + VS–
>2.1 + VS–
Disable voltage threshold
Assured off below 0.7 V + VS–
<0.7 + VS–
Power-down quiescent current
Input bias current
0.46
PD = VS–
Input impedance
65
50 || 2
V
mA
A
Measured to output on
100
ns
Turn-off time delay
Measured to output off
10
s
www.BDTIC.com/TI
Submit Documentation Feedback
Product Folder Link(s): THS4509-Q1
C
kΩ || pF
Turn-on time delay
Copyright © 2008, Texas Instruments Incorporated
C
7
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
TYPICAL CHARACTERISTICS
TYPICAL AC PERFORMANCE: VS+ – VS– = 5 V
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
differential, G = 10 dB, single-ended input, input and output referenced to midrail
Small-Signal Frequency Response
Figure 1
Large Signal Frequency Response
Harmonic Distortion
Intermodulation Distortion
Output Intercept Point
Figure 2
HD2, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 3
HD3, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 4
HD2, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 5
HD3, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 6
HD2, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 7
HD3, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 8
HD2, G = 10 dB
vs Output Voltage
Figure 9
HD3, G = 10 dB
vs Output Voltage
Figure 10
HD2, G = 10 dB
vs Common-Mode Output Voltage
Figure 11
HD3, G = 10 dB
vs Common-Mode Output Voltage
Figure 12
IMD2, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 13
IMD3, G = 6 dB, VOD = 2 VPP
vs Frequency
Figure 14
IMD2, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 15
IMD3, G = 10 dB, VOD = 2 VPP
vs Frequency
Figure 16
IMD2, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 17
IMD3, G = 14 dB, VOD = 2 VPP
vs Frequency
Figure 18
OIP2
vs Frequency
Figure 19
OIP3
vs Frequency
Figure 20
0.1-dB Flatness
Figure 21
S-Parameters
vs Frequency
Figure 22
Transition Rate
vs Output Voltage
Figure 23
Transient Response
Figure 24
Settling Time
Figure 25
Rejection Ratio
vs Frequency
Figure 26
Output Impedance
vs Frequency
Figure 27
Overdrive Recovery
Figure 28
Output Voltage Swing
vs Load Resistance
Figure 29
Turn-Off Time
Figure 30
Turn-On Time
Figure 31
Input Offset Voltage
vs Input Common-Mode Voltage
Figure 32
Open-Loop Gain and Phase
vs Frequency
Figure 33
Input Referred Noise
vs Frequency
Figure 34
Noise Figure
vs Frequency
Figure 35
Quiescent Current
vs Supply Voltage
Figure 36
Power-Supply Current
vs Supply Voltage in Power-Down Mode
Figure 37
Output Balance Error
vs Frequency
Figure 38
CM Input Impedance
vs Frequency
Figure 39
CM Small-Signal Frequency Response
Figure 40
CM Input Bias Current
vs CM Input Voltage
Figure 41
Differential Output Offset Voltage
vs CM Input Voltage
Figure 42
Output Common-Mode Offset
vs CM Input Voltage
Figure 43
8
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
22
22
VOD = 2 VPP
20
16
Large Signal Gain − dB
G = 20 dB
18
Small Signal Gain - dB
G = 20 dB
VOD = 100 mVPP
20
G = 14 dB
14
12
G = 10 dB
10
8
G = 6 dB
6
18
16
G = 14 dB
14
12
G = 10 dB
10
8
G = 6 dB
6
4
4
2
2
0
0
0.1
0.1
1
10
100
1000
f - Frequency - MHz
10000
10
100
f − Frequency − MHz
1
Figure 1.
HD2 vs FREQUENCY
HD3 vs FREQUENCY
−60
G = 6 dB,
VOD = 2 VPP
−70
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
10000
Figure 2.
−60
RL = 100 W
−80
−90
RL = 200 W
−100
RL = 1 kW
−110
RL = 500 W
−120
G = 6 dB,
VOD = 2 VPP
−70
−80
RL = 100 W
−90
RL = 1 kW
−100
RL = 500 W
−110
RL = 200 W
−120
10
100
f − Frequency − MHz
1
1000
1
10
100
f − Frequency − MHz
Figure 3.
1000
Figure 4.
HD2 vs FREQUENCY
HD3 vs FREQUENCY
−60
−60
G = 10 dB,
VOD = 2 VPP
−70
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
1000
RL = 200 W
−80
RL = 100 W
−90
−100
RL = 1 kW
−110
RL = 500 W
−120
G = 10 dB,
VOD = 2 VPP
−70
−80
RL = 500 W
−90
RL = 1 kW
−100
RL = 100 W
−110
RL = 200 W
−120
1
10
100
f − Frequency − MHz
1000
1
Figure 5.
10
100
f − Frequency − MHz
1000
Figure 6.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
9
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
HD2 vs FREQUENCY
HD3 vs FREQUENCY
−60
G = 14 dB,
VOD = 2 VPP
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
−60
−70
RL = 100 W
−80
RL = 200 W
RL = 500 W
−90
−100
−110
RL = 1 kW
G = 14 dB,
VOD = 2 VPP
−70
−80
RL = 100 W
−90
RL = 1 kW
−100
RL = 200 W
−110
RL = 500 W
−120
−120
10
100
f − Frequency − MHz
1
1000
1
1000
10
100
f − Frequency − MHz
Figure 7.
Figure 8.
HD2 vs OUTPUT VOLTAGE
HD3 vs OUTPUT VOLTAGE
-60
-60
3nd Order Harmonic Distortion - dBc
2 nd -Order Harmonic Distortion - dBc
f = 64 MHz
-70
f = 64 MHz
-80
f = 32 MHz
-90
f = 16 MHz
-100
f = 8 MHz
-110
-120
f = 32 MHz
-80
f = 8 MHz
-90
-100
-110
f = 16 MHz
-120
0
1
2
VOD - VPP
3
4
0
1
3
4
Figure 9.
Figure 10.
HD2 vs COMMON-MODE OUTPUT VOLTAGE
HD3 vs COMMON-MODE OUTPUT VOLTAGE
-20
-20
3rd Order Harmonic Distortion − dBc
VCM = -1 V to 1 V
VOD = 2 VPP
G = 10 dB
RL = 200 W
-40
150 MHz
-60
100 MHz
64 MHz
-80
32 MHz
-100
16 MHz
4 MHz
1 MHz
-120
VCM = -1 V to 1 V
VOD = 2 VPP
G = 10 dB
RL = 200 W
-30
-40
-50
-60
150 MHz
-70
100 MHz
-80
64 MHz
-90
32 MHz
-100
16 MHz
-110
1 MHz
4 MHz
-120
-1
0.2 0.4 0.6 0.8
-0.8 -0.6 -0.4 -0.2 0
VIC − Common-Mode Output Voltage − V
1
-1
-0.8 -0.6 -0.4 -0.2 0
0.2 0.4 0.6
VIC − Common-Mode Output Voltage − V
Figure 11.
10
2
VOD - VPP
0
2nd Order Harmonic Distortion − dBc
-70
0.8
1
Figure 12.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−60
Gain = 6 dB,
VOD = 2 VPP Envelop
-40
RL = 200 W
IMD3 − Intermodulation Distortion − dBc
IMD 2 - Intermodulation Distortion - dBc
-30
RL = 100 W
-50
-60
-70
RL = 500 W
-80
RL = 1 kW
-90
Gain = 6 dB,
VOD = 2 VPP Envelope
−65
RL = 200 Ω
−70
RL = 1 kΩ
−75
−80
−85
−90
−95
RL = 500 Ω
−100
-100
0
50
100
f - Frequency - Mhz
150
0
200
100
f − Frequency − MHz
50
Figure 13.
IMD2 vs FREQUENCY
200
IMD3 vs FREQUENCY
-60
Gain = 10 dB,
VOD = 2 VPP Envelope
-40
IMD 3 − Intermodulation Distortion - dBc
IMD 2 - Intermodulation Distortion - dBc
150
Figure 14.
-30
RL = 200 W
RL = 100 W
-50
-60
-70
RL = 500 W
-80
RL = 1 kW
-90
Gain = 10 dB,
VOD = 2 VPP Envelope
-65
RL = 100 W
RL = 200 W
-70
-75
-80
-85
RL = 1 kW
-90
RL = 500 W
-95
-100
-100
0
50
100
150
f - Frequency - Mhz
0
200
50
100
F - Frequency - MHz
150
Figure 15.
Figure 16.
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−30
200
−60
Gain = 14 dB,
VCO = 2 VPP Envelope
−40
−50
IMD 3 − Intermodulation Distortion − dBc
IMD 2− Intermodulation Distortion − dBc
RL = 100 Ω
RL = 200 W
RL = 100 W
−60
−70
RL = 500 W
−80
RL = 1 kW
−90
RL = 100 W
Gain = 14 dB
VOD = 2 VPP Envelope
−65
−70
RL = 200 W
−75
−80
−85
−90
RL = 1 kW
−95
RL = 500 W
−100
0
−100
50
100
150
f − Frequency − MHz
200
0
Figure 17.
50
100
150
f − Frequency − MHz
200
Figure 18.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
11
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
OIP2 vs FREQUENCY
OIP3 vs FREQUENCY
45
Gain = 6 dB
85
Gain = 14 dB
80
75
70
65
Gain = 10 dB
60
55
50
45
41
39
Gain = 10 dB
37
35
33
31
50
100
150
f − Frequency − MHz
Gain = 14 dB
29
27
40
0
Gain = 6 dB
43
OIP − Output Intercept Point − dBm
3
OIP 2 − Output Intercept Point − dBm
90
25
200
0
50
100
150
f − Frequency − MHz
Figure 19.
200
250
Figure 20.
0.1-dB FLATNESS
S-PARAMETERS vs FREQUENCY
10.2
0
S21
VOD = 2VPP
-10
S-Parameters - dB
Signal Gain − dB
10.1
10
-20
S11
-30
-40
S22
-50
9.9
-60
S12
-70
9.8
0.1
1
10
100
f − Frequency − MHz
1
1000
Figure 21.
TRANSITION RATE vs OUTPUT VOLTAGE
1000
TRANSIENT RESPONSE
1.5
V OD − Differential Output V oltage − V
7000
Rise
Transistion Rate − V/ ms
100
Figure 22.
8000
6000
Fall
5000
4000
3000
2000
1000
1
0.5
0
VOD = 2 Vstep
−0.5
−1
−1.5
0
0
0.5
1.5
2.5
3
3.5
1
2
VOD - Differential Outrput Voltage - VSTEP
4
Figure 23.
12
10
f - Frequency - MHz
t − Time − 500 ps/div
Figure 24.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
SETTLING TIME
REJECTION RATIO vs FREQUENCY
5
100
VOD = 2 Vstep
4
90
PSRR−
80
Rejection Ratio −dB
2
1
0
−1
−2
PSRR+
70
60
CMRR
50
40
30
−3
20
−4
10
−5
0
0.01
t − Time − 500 ps/div
0.1
1
10
f − Frequency − MHz
Figure 25.
Figure 26.
OUTPUT IMPEDANCE vs FREQUENCY
1
5
1
4
0.8
3
Input
0.4
2
Output
1
0.2
0
0
−1
−0.2
−2
−0.4
−3
−0.6
−4
−0.8
−1
−5
10
100
f − Frequency− MHz
1000
t − Time − 200 ns/div
Figure 27.
Figure 28.
OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
TURN-OFF TIME
2
VOD − Differential Ouput Voltage − V
VOD - Differential Output Voltage - V
7
6
5
4
3
2
1
0
10
100
0.6
Input V oltage − V
V OD− Differential Output Voltage − V
Z o − Output Impedance − Ω
10
1
1000
OVERDRIVE RECOVERY
100
0.1
0.1
100
5
4
1.6
Output
1.2
3
PD
0.8
2
0.4
1
0
0
Power Down Input − V
Percent of Final Value − %
3
1000
t − Time − 2 ms/div
RL - Load Resistance - W
Figure 29.
Figure 30.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
13
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
INPUT OFFSET VOLTAGE vs
INPUT COMMON-MODE VOLTAGE
5
1.6
4
PD
1.2
3
0.8
2
Output
0.4
1
0
0
40
V IO − Input Offset V oltage − mV
2
Power Down Input − V
VOD − Differential Output V oltage − V
TURN-ON TIME
35
30
25
20
15
10
5
0
−5
−2.5 −2 −1.5 −1 −0.5
0 0.5
1
1.5
Input Common-Mode Voltage − V
t − Time − 50 ns/div
Figure 31.
10
70
-20
Gain
-50
Phase
-80
40
-110
30
-140
20
-170
10
-200
Vn − Voltage Noise − nV/ Hz
80
INPUT REFERRED NOISE vs FREQUENCY
1000
I n − Current Noise − pA/ Hz
40
Open Loop Phase − degrees
Open Loop Gain − dB
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
50
100
-230
0
100
1
10 k
1M
100 M
In
10
Vn
1
10
10 G
100
f − Frequency − Hz
Figure 33.
1k
10 k
100 k
f − Frequency − Hz
10 M
1M
Figure 34.
NOISE FIGURE vs FREQUENCY
QUIESCENT CURRENT vs SUPPLY VOLTAGE
20
40
19 Gain = 6 dB
18
TA = 25°C
50 - W System
I Q − Quiescent Current − mA
NF − Noise Figure − dB
2.5
Figure 32.
90
60
2
17
Gain = 10 dB
16
15
Gain = 14 dB
14
13
Gain = 20 dB
12
TA = -40°C
35
±1.35 V
TA = 85°C
30
11
25
10
0
50
100
150
f − Frequency − MHz
200
1
Figure 35.
14
1.5
2
VS - Supply Voltage - V
2.5
Figure 36.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
POWER-SUPPLY CURRENT
vs SUPPLY VOLTAGE IN POWER-DOWN MODE
OUTPUT BALANCE ERROR vs FREQUENCY
800
10
TA = 85°C
0
Output Balance Error − dB
Power Supply Current − µ A
700
TA = 25°C
600
500
400
TA = −40°C
300
200
−10
−20
−30
−40
−50
100
0
0
0.5
1
1.5
VS − Supply Voltage − V
2
−60
0.1
2.5
Figure 37.
Figure 38.
CM INPUT IMPEDANCE vs FREQUENCY
CM SMALL-SIGNAL FREQUENCY RESPONSE
100
1
100 mVPP
0
-1
10
-2
CM Gain − dB
CM Input Impedance − k Ω
1000
10
100
f − Frequency − MHz
1
1
-3
-4
-5
-6
-7
0.1
-8
-9
0.01
0.1
1
10
100
f − Frequency − MHz
-10
0.1
1000
10
100
1000
f − Frequency − MHz
Figure 39.
Figure 40.
CM INPUT BIAS CURRENT vs CM INPUT VOLTAGE
DIFFERENTIAL OUTPUT OFFSET VOLTAGE vs
CM INPUT VOLTAGE
5
Differential Output Offset Voltage − mV
300
CM Input Bias Current − µ A
1
200
100
0
−100
−200
−300
−2.5
−2 −1.5 −1
−0.5 0
0.5 1
CM Input Voltage − V
1.5
2
2.5
4
3
2
1
0
−1
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
CM Input Voltage − V
Figure 41.
Figure 42.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
15
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
OUTPUT COMMON-MODE OFFSET vs
CM INPUT VOLTAGE
50
Output Common−Mode Offset − mV
40
30
20
10
0
−10
−20
−30
−40
−50
−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
CM Input Voltage − V
Figure 43.
16
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
TYPICAL AC PERFORMANCE: VS+ – VS– = 3 V
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, CM = open, VOD = 1 Vpp, RF = 349 Ω,
RL = 200 Ω differential, G = 10 dB, single-ended input, input and output referenced to midrail
Small-Signal Frequency Response
Figure 44
Large-Signal Frequency Response
Figure 45
HD2, G = 6 dB, VOD = 1 VPP
vs Frequency
Figure 46
HD3, G = 6 dB, VOD = 1 VPP
vs Frequency
Figure 47
HD2, G = 10 dB, VOD = 1 VPP
vs Frequency
Figure 48
HD3, G = 10 dB, VOD = 1 VPP
vs Frequency
Figure 49
HD2, G = 14 dB, VOD = 1 VPP
vs Frequency
Figure 50
HD3, G = 14 dB, VOD = 1 VPP
vs Frequency
Figure 51
IMD2, G = 6 dB, VOD = 1 VPP
vs Frequency
Figure 52
IMD3, G = 6 dB, VOD = 1 VPP
vs Frequency
Figure 53
IMD2, G = 10 dB, VOD = 1 VPP
vs Frequency
Figure 54
IMD3, G = 10 dB, VOD = 1 VPP
vs Frequency
Figure 55
IMD2, G = 14 dB, VOD = 1 VPP
vs Frequency
Figure 56
IMD3, G = 14 dB, VOD = 1 VPP
vs Frequency
Figure 57
OIP2
vs Frequency
Figure 58
OIP3
vs Frequency
Figure 59
S-Parameters
vs Frequency
Figure 61
Transition Rate
vs Output Voltage
Figure 62
Harmonic Distortion
Intermodulation Distortion
Output Intercept Point
0.1-dB Flatness
Figure 60
Transient Response
Figure 63
Settling Time
Figure 64
Output Voltage Swing
vs Load Resistance
Figure 65
Rejection Ratio
vs Frequency
Figure 66
vs Frequency
Figure 68
Overdrive Recovery
Figure 67
Output Impedance
Turn-Off Time
Figure 69
Turn-On Time
Figure 70
Output Balance Error
vs Frequency
Figure 71
Noise Figure
vs Frequency
Figure 72
CM Input Impedance
vs Frequency
Figure 73
Differential Output Offset Voltage
vs CM Input Voltage
Figure 74
Output Common-Mode Offset
vs CM Input Voltage
Figure 75
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
17
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
22
22
VOD = 100 mVPP
20
VOD = 1 VPP
20
G = 20 dB
Small Signal Gain − dB
18
Large Signal Gain − dB
G = 14 dB
14
12
G = 10 dB
10
8
G = 6 dB
6
4
16
G = 14 dB
14
12
G = 10 dB
10
8
G = 6 dB
6
4
2
2
0
0
1
10
100
f - Frequency - MHz
1000
10000
Figure 45.
HD2 vs FREQUENCY
HD3 vs FREQUENCY
−50
−60
−70
−80
R L = 100Ω
−90
RL= 1 kΩ
R L = 200 Ω
−100
−110
R L = 500 Ω
10
100
G = 6 dB,
VOD = 1 VPP
−40
−50
−60
RL = 100 W
−70
RL = 200 W
−80
−90
RL = 1 kW
f − Frequency − MHz
10
100
f − Frequency − MHz
Figure 46.
Figure 47.
1
HD2 vs FREQUENCY
HD3 vs FREQUENCY
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
G = 10 dB,
VOD = 1 VPP
−70
−80
R L = 200 Ω
−90
−100
−120
1
R L = 1 kΩ
R L = 500 Ω
G = 10 dB,
COD = 1 VPP
−50
−60
−70
RL = 1 kW
−80
RL = 500 W
−90
RL = 200 W
−100
10
100
f − Frequency − MHz
1000
1
Figure 48.
18
1000
−40
−60
−110
10000
−100
1000
−40
−50
1000
RL = 500 W
−120
1
10
100
f− Frequency − MHz
1
Figure 44.
G = 6 dB,
VOD = 1 VPP
−40
0.1
3rd Order Harmonic Distortion − dBc
0.1
2nd Order Harmonic Distortion − dBc
G = 20 dB
18
16
100
10
f − Frequency − MHz
1000
Figure 49.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
HD2 vs FREQUENCY
HD3 vs FREQUENCY
−40
G = 14 dB,
VOD = 1 VPP
−50
3rd Order Harmonic Distortion − dBc
2nd Order Harmonic Distortion − dBc
−40
−60
R L = 100 Ω
−70
−80
R L = 200 Ω
−90
−100
R L = 500 Ω
−110
R L= 1 kΩ
−120
G = 14 dB,
VOD = 1 VPP
−50
−60
RL = 100 W
−70
RL = 200 W
−80
RL = 500 W
−90
RL = 1 kW
−100
10
1
100
1000
f − Frequency − MHz
10
100
f − Frequency − MHz
Figure 50.
Figure 51.
1
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−30
Gain = 6 dB,
VOD = 1 VPP
−40
IMD3 − Intermodulation Distortion − dBc
IMD2 − Intermodulation Distortion − dBc
−30
RL = 500 W
RL = 1 kW
−50
−60
RL = 100 W
−70
RL = 200 W
−80
−90
−100
0
Gain = 6 dB,
VOD = 1 VPP Envelope
−40
RL = 100 W
−50
−60
RL = 1 kW
RL = 500 W
−70
−80
−90
RL = 200 W
−100
50
100
f − Frequency − MHz
150
200
0
50
100
150
f − Frequency − MHz
Figure 52.
Figure 53.
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−30
200
−30
Gain = 10 dB,
VOD = 1 VPP Envelope
−40
IMD3 − Intermodulation Distortion − dBc
IMD − Intermodulation Distortion − dBc
2
1000
RL = 500 W
−50
−60
RL = 1 kW
RL = 100 W
−70
RL = 200 W
−80
−90
−100
Gain = 10 dB,
VOD = 1 VPP Envolope
−40
−50
RL = 100 W
−60
RL = 500 W
−70
RL = 1 kW
−80
−90
RL = 200 W
−100
0
50
100
f − Frequency − MHz
150
200
0
Figure 54.
50
100
150
f − Frequency − MHz
200
Figure 55.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
19
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−30
Gain = 14 dB,
VOD = 1 VPP Envelope
−40
IMD3 − Intermodulation Distortion − dBc
IMD 2 − Intermodulation Distortion − dBc
−30
RL = 500 W
−50
−60
RL = 1 kW
RL = 100 W
−70
RL = 200 W
−80
−90
Gain = 14 dB,
VOD = 1 VPP Envelope
−40
RL = 100 W
−50
−60
RL = 500 W
−70
RL = 1 kW
−80
RL = 200 W
−90
−100
−100
0
50
100
150
f − Frequency − MHz
200
0
50
100
150
f − Frequency − MHz
Figure 56.
Figure 57.
OIP2 vs FREQUENCY
OIP3 vs FREQUENCY
80
45
OIP3 − Output Intercept Point − dBm
Gain = 6 dB
OIP2 − Output Intercept Point − dBm
200
75
70
65
60
Gain = 10 dB
55
50
Gain = 14 dB
45
40
35
Gain = 6 dB
40
Gain = 10 dB
35
30
25
Gain = 14 dB
20
15
30
0
150
100
f − Frequency − MHz
50
0
200
50
Figure 58.
150
100
f − Frequency − MHz
200
250
Figure 59.
0.1-dB FLATNESS
S-PARAMETERS vs FREQUENCY
10.2
0
VOD = 1 VPP
S21
-10
10.1
S-Parameters - dB
Signal Gain − dB
-20
10
S11
-30
-40
S22
-50
9.9
-60
S12
9.8
0.1
1
10
100
f − Frequency − MHz
1000
10000
-70
1
Figure 60.
20
10
100
f = Frequency - MHz
1000
Figure 61.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
TRANSITION RATE vs OUTPUT VOLTAGE
TRANSIENT RESPONSE
0.6
VOD − Differential Output Voltage - V
4000
Rising
3000
2500
Falling
2000
1500
1000
500
0
0
0.5
0.4
0.3
VOD = 1 Vstep
0.2
0.1
0
−0.1
−0.2
−0.3
−0.4
−0.5
−0.6
0.2
1.4
1
1.2
0.4
0.6
0.8
VOD − Differential Output Voltage - VSTEP
t − Time − 500 ps/div
Figure 62.
Figure 63.
SETTLING TIME
OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
5
2.5
Percent of Final Voltage - V
VOD - Differential Output Voltage - V
VOD = 1 Vstep
4
3
2
1
0
−1
−2
−3
−4
2
1.5
1
0.5
0
−5
100
RL - Load Resistance - W
0
t − Time − 500 ps/div
Figure 64.
Figure 65.
REJECTION RATIO vs FREQUENCY
OVERDRIVE RECOVERY
3
90
0.6
V OD − Differential Output Voltage - V
PSRR−
80
CMRR
Rejection Ratio −dB
70
60
PSRR+
50
40
2.5
2
Input
0.4
1.5
1
0.2
0.5
Output
0
0
−0.5
30
−0.2
−1
−1.5
20
10
0
0.01
1000
Input Voltage - V
SR − Transition Rate − V/ µ s
3500
−0.4
−2
−2.5
−3
0.1
1
10
100
f − Frequency − MHz
−0.6
1000
Figure 66.
t − Time − 200 ns/div
Figure 67.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
21
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
OUTPUT IMPEDANCE vs FREQUENCY
TURN-OFF TIME
3
1
10
1
2.5
0.8
Output
1.5
0.4
PD
1
0.2
0.1
0.5
0
0.1
1
10
f − Frequency− MHz
0
1000
100
t – Time – 2 ms/div
Figure 68.
Figure 69.
TURN-ON TIME
OUTPUT BALANCE ERROR vs FREQUENCY
0
PD
0.8
2
1.5
0.6
Output
1
0.4
0.2
0
Output Balance Error − dB
2.5
1
Power Down Input − V
VOD − Differential Ouput Voltage - V
10
3
1.2
−10
−20
−30
−40
0.5
−50
0
−60
0.1
1
t − Time − 50 ns/div
Figure 71.
NOISE FIGURE vs FREQUENCY
CM INPUT IMPEDANCE vs FREQUENCY
20
1000
100
50 - W System
Gain = 6 dB
CM Input Impedance − k Ω
18
NF − Noise Figure − dB
10
100
f − Frequency − MHz
Figure 70.
19
17
Gain = 10 dB
16
15
Gain = 14 dB
14
13
12
10
1
0.1
Gain = 20 dB
11
10
0
50
100
150
f − Frequency − MHz
200
0.01
0.1
Figure 72.
22
2
0.6
Power Down Input − V
VOD − Differential Ouput Voltage - V
Z o − Output Impedance − Ω
100
1
100
10
f − Frequency − MHz
1000
Figure 73.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
DIFFERENTIAL OUTPUT OFFSET VOLTAGE vs
CM INPUT VOLTAGE
OUTPUT COMMON-MODE OFFSET vs
CM INPUT VOLTAGE
50
Output Common−Mode Offset − mV
Differential Output Offset V oltage − mV
5
4
3
2
1
0
−1
−1.5
−1
−0.5
0
0.5
CM Input Voltage − V
1
1.5
40
30
20
10
0
−10
−20
−30
−40
−50
−1.5
Figure 74.
−1
−0.5
0
0.5
CM Input Voltage - V
1
1.5
Figure 75.
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
23
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
TEST CIRCUITS
The THS4509 is tested with the following test circuits
built on the EVM. For simplicity, power-supply
decoupling is not shown – see layout in the
applications section for recommendations. Depending
on the test conditions, component values are
changed per the following tables, or as otherwise
noted. The signal generators used are ac coupled
50-Ω sources and a 0.22-µF capacitor and a 49.9-Ω
resistor to ground are inserted across RIT on the
alternate input to balance the circuit. A split power
supply is used to ease the interface toV common test
equipment, but the amplifier can be operated single
supply, as described in the applications section, with
no impact on performance.
of the network analyzer is 50 Ω. RIT and RG are
chosen to impedance match to 50 Ω, and to maintain
the proper gain. To balance the amplifier, a 0.22-F
capacitor and 49.9-Ω resistor to ground are inserted
across RIT on the alternate input.
The output is probed using a high-impedance
differential probe across the 100-Ω resistor. The gain
is referred to the amplifier output by adding back the
6-dB loss due to the voltage divider on the output.
morF
05 Ω
ecruoS
RF
RG
RIT
6 dB
348 Ω
165 Ω
61.9 Ω
10 dB
348 Ω
100 Ω
69.8 Ω
14 dB
348 Ω
56.2 Ω
88.7 Ω
20 dB
348 Ω
16.5 Ω
287 Ω
Note the gain setting includes 50-Ω source
impedance. Components are chosen to achieve
gain and 50-Ω input termination.
Table 2. Load Component Values
RL
RO
ROT
ATTEN
100 Ω
25 Ω
open
6 dB
200 Ω
86.6 Ω
69.8 Ω
16.8 dB
499 Ω
237 Ω
56.2 Ω
25.5 dB
1k Ω
487 Ω
52.3 Ω
31.8 dB
Note the total load includes 50-Ω termination by
the test equipment. Components are chosen to
achieve load and 50-Ω line termination through a
1:1 transformer.
Due to the voltage divider on the output formed by
the load component values, the amplifier's output is
attenuated. The column ATTEN in Table 2 shows the
attenuation expected from the resistor divider. When
using a transformer at the output, as shown in
Figure 77, the signal sees slightly more loss, and
these numbers are approximate.
µF
9.94
MC
V−S
Ω
derusaeM tuptuO
hgiH1htiW
Ω ereH
Ω 00e
cnadepmI
eborP laitnereffiD
nepO
22.0
µF
RF
Figure 76. Frequency Response Test Circuit
Distortion and 1-dB Compression
The circuit shown in Figure 77 is used to measure
harmonic distortion, intermodulation distortion, and
1-db compression point of the amplifier.
A signal generator is used as the signal source and
the output is measured with a spectrum analyzer. The
output impedance of the signal generator is 50 Ω. RIT
and RG are chosen to impedance-match to 50 Ω, and
to maintain the proper gain. To balance the amplifier,
a 0.22-F capacitor and 49.9-Ω resistor to ground are
inserted across RIT on the alternate input.
A low-pass filter is inserted in series with the input to
reduce harmonics generated at the signal source.
The level of the fundamental is measured, then a
high-pass filter is inserted at the output to reduce the
fundamental so that it does not generate distortion in
the input of the spectrum analyzer.
The transformer used in the output to convert the
signal from differential to single ended is an
ADT1-1WT. It limits the frequency response of the
circuit so that measurements cannot be made below
approximately 1 MHz.
VNI
RF
RG
RTI
V+S
RO
The circuit shown in Figure 76 is used to measure the
frequency response of the circuit.
A network analyzer is used as the signal source and
as the measurement device. The output impedance
+S
RTI
Ω
morF
05 Ω
ecruoS
Frequency Response
RTI
RF
9054 SHT
RG
9.94
GAIN
RG
9.94
22.0
Table 1. Gain Component Values
VNI
R G9054 SHT
22.0
9.94
µ F
RO
MC
RTI
V−S
Ω
1:1
RTO
TV
UO
05To
tseT
tnempiuqE
Ω
nepO
22.0 µ F
RF
Figure 77. Distortion Test Circuit
24
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
The 1-dB compression point is measured with a
spectrum analyzer with 50-Ω double termination or
100-Ω termination as shown in Table 2. The input
power is increased until the output is 1 dB lower than
expected. The number reported in the table data is
the power delivered to the spectrum analyzer input.
Add 3 dB to refer to the amplifier output.
S-Parameter, Slew Rate, Transient Response,
Settling Time, Output Impedance, Overdrive,
Output Voltage, and Turn-On/Turn-Off Time
CM Input
The circuit shown in Figure 79 is used to measure the
frequency response and input impedance of the CM
input. Frequency response is measured single ended
at VOUT+ or VOUT– with the input injected at VIN, RCM =
0 Ω, and RCMT = 49.9 Ω. The input impedance is
measured with RCM = 49.9 Ω with RCMT = open, and
calculated by measuring the voltage drop across RCM
to determine the input current.
The circuit shown in Figure 78 is used to measureF
s-parameters, slew rate, transient response, settling
time, output impedance, overdrive recovery, output
voltage swing, and turn-on/turn-off times of the
amplifier. For output impedance, the signal is injected
at VOUT with VIN left open and the drop across theF
49.9-Ω resistor is used to calculate the impedance
seen looking into the amplifier’s output.
22.0
9.94
m
RG
RTI
9.94
W
9.94
V+S
9.94
Ω
9.94
Ω
+TV
UO
µ F
22.0
m
9.94
Ω
9.94
MC
R TI
MC
V−S
W
RMC
VNm
I orF
mho-05
ecruos
V–S
W
R
R
TMC
F
Figure 79. CM Input Test Circuit
05To
tseT
tn
e
m
p
i
u
qE
V
Ω
The circuit shown in Figure 80 is used to measure the
CMRR and PSRR of VS+ and VS–. The input is
switched appropriately to match the test being
performed.
−TUO
RTI
oT
mho-05
tseT
UO
tn+eTV
m
piuqE
VUO
–T
R G9054SHT
22.0
W
CMRR and PSRR
RF
RG9054 SHT
F
V+S
R TI
Because S21 is measured single ended at the load
with 50-Ω double termination, add 12 dB to refer to
the amplifier’s output as a differential signal.
VNI
morF
05 Ω
ecruoS
R
RG
843
V+S
nepO
22.0 µ F
RF
Figure 78. S-Parameter, SR, Transient Response,
Settling Time, ZO, Overdrive Recovery, VOUT
Swing, and Turn-On/Turn-Off Test Circuit
+ RRSP
VNI
morF
05 Ω
RRMC
ecruoS
Ω
V+S
001
9.94
Ω
54SHT
001 90Ω
− RRSP
MC
V−S
8.96
Ω
V−S
843
Ω
tuptuO
derusaeM
9.94 Ω 001 ΩereH
hgiH htiW
ecnadepmI
nepO laitnereffiD
22.0 µ F eborP
Ω
Figure 80. CMRR and PSRR Test Circuit
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
25
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
APPLICATION INFORMATION
APPLICATIONS
dednE-elgniS
tupnI
VS
The following circuits show application information for
the THS4509. For simplicity, power supply decoupling
capacitors are not shown in these diagrams. See
section THS4509 EVM for recommendations. For
more detail on the use and operation of fully
differential op amps see the application report
Fully-Differential Amplifiers (SLOA054) .
RF
laitnereffiD
tupnI
RG
V
+NI
V
–NI
laitnereffiD
tuptuO
V+S
RG
+
–
–TV
UO
– +
+TV
UO
9054SHT
V–S
RF
Figure 81. Differential Input to Differential Output
Amplifier
Depending on the source and load, input and output
termination can be accomplished by adding RIT and
RO.
Single-Ended Input to Differential Output
Amplifier
The THS4509 can be used to amplify and convert
single-ended input signals to differential output
signals. A basic block diagram of the circuit is shown
in Figure 82 (CM input not shown). The gain of the
circuit is again set by RF divided by RG.
26
laitnereffiD
tuptuO
+
RG
–
–TV
UO
SHT9054
–
+
+TV
UO
VS
Differential Input to Differential Output Amplifier
The THS4509 is a fully differential op amp, and can
be used to amplify differential input signals to
differential output signals. A basic block diagram of
the circuit is shown in Figure 81 (CM input not
shown). The gain of the circuit is set by RF divided by
RG.
RF
RG
RF
Figure 82. Single-Ended Input to Differential
Output Amplifier
Input Common-Mode Voltage Range
The input common-model voltage of a fully differential
op amp is the voltage at the '+' and '–' input pins of
the op amp.
It is important to not violate the input common-mode
voltage range (VICR) of the op amp. Assuming the op
amp is in linear operation the voltage across the input
pins is only a few millivolts at most. So finding the
voltage at one input pin will determine the input
common-mode voltage of the op amp.
Treating the negative input as a summing
voltage is given by Equation 1:
ö æ
æ
RG
RF
÷ + çVNI - ´
VCI = ççTVUO + ´
÷
ç
R G +R F
R G +R F ø è
è
node, the
ö
÷
÷
ø
(1)
To determine the VICR of the op amp, the voltage at
the negative input is evaluated at the extremes of
VOUT+.
As the gain of the op amp increases, the input
common-mode voltage becomes closer and closer to
the input common-mode voltage of the source.
Setting the Output Common-Mode Voltage
The output common-mode voltage is set by the
voltage at the CM pin(s). The internal common-mode
control circuit maintains the output common-mode
voltage within 3-mV offset (typ) from the set voltage,
when set within 0.5 V of mid-supply, with less than
4-mV differential offset voltage. If left unconnected,
the common-mode set point is set to mid-supply by
internal circuitry, which may be overdriven from an
external source. Figure 83 is representative of the
CM input. The internal CM circuit has about 700 MHz
of –3-dB bandwidth, which is required for best
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
performance, but it is intended to be a dc bias input
pin. Bypass capacitors are recommended on this pin
to reduce noise at the output. The external current
required to overdrive the internal resistor divider is
given by Equation 2:
IEXT =
2VCM - (VS + - VS - )
50 kW
RS
RG
R
VgiS
lan
R
F
V+S
T
RO
VMC
VaiBV
s
(2)
=
R G9054SHT
MC
RS
R
V–S
VMC
VMC
VMC
R
V+S
W
TXIE
lanretni ot
tiucric MC
MC
k 05
W
In Figure 85 the source is referenced to ground and
so is the input termination resistor. RPU is added to
the circuit to avoid violating the VICR of the op amp.
The proper value of resistor to add can be calculated
from Equation 3:
RUP =
Figure 83. CM Input Circuit
Single-Supply Operation (3 V to 5 V)
To facilitate testing with common lab equipment, the
THS4509 EVM allows split-supply operation, and the
characterization data presented in this data sheet
was taken with split-supply power inputs. The device
can easily be used with a single-supply power input
without degrading the performance. Figure 84,
Figure 85, and Figure 86 show dc and ac-coupled
single-supply circuits with single-ended inputs. These
configurations all allow the input and output
common-mode voltage to be set to mid-supply
allowing for optimum performance. The information
presented here can also be applied to differential
input sources.
In Figure 84, the source is referenced to the same
voltage as the CM pin (VCM). VCM is set by the
internal circuit to mid-supply. RT along with the input
impedance of the amplifier circuit provides input
termination, which is also referenced to VCM.
Note RS and RT are added to the alternate input from
the signal input to balance the amplifier. Alternately,
one resistor can be used equal to the combined value
RG+ RS||RT on this input. This is also true of the
circuits shown in Figure 85 and Figure 86.
F
Figure 84. THS4509 DC-Coupled Single Supply
With Input Biased to VCM
)
V–S
VUO
+T
MC
T
where VCM is the voltage applied to the CM pin.
k 05
VUO
-T
RO
(VCI
æ 1
VMC çç
èR F
-V S+
ö
÷÷ - VCI
ø
æ 1
1
çç
+
èR NI R F
ö
÷÷
ø
(3)
VIC is the desire input common-mode voltage, VCM =
CM, and RIN = RG + RS||RT. To set to mid-supply,
make the value of RPU = RG+ RS||RT.
Table 3 is a modification of Table 1 to add the proper
values with RPU assuming a 50 Ω source impedance
and setting the input and output common-mode
voltage to mid-supply.
There are two drawbacks to this configuration. One is
it requires additional current from the power supply.
Using the values shown for a gain of 10 dB requires
37 mA more current with 5-V supply, and 22 mA
more current with 3-V supply.
The other drawback is this configuration also
increases the noise gain of the circuit. In the 10-dB
gain case, noise gain increases by a factor of 1.5.
Table 3. RPU Values for Various Gains
Gain
RF
RG
RIT
RPU
200 Ω
6 dB
348 Ω
169 Ω
64.9 Ω
10 dB
348 Ω
102 Ω
78.7 Ω
133 Ω
14 dB
348 Ω
61.9 Ω
115 Ω
97.6 Ω
20 dB
348 Ω
40.2 Ω
221 Ω
80.6 Ω
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
27
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
V S+
R PU
RS
RF
RG
RT
V Signal
V S+
V S+
RO
V OUT-
R PU
THS 4509
RG
RO
V OUT+
RS
V S-
RT
CM
RF
Figure 85. THS4509 DC-Coupled Single Supply
With RPU Used to Set VIC
Figure 86 shows ac coupling to the source. Using
capacitors in series with the termination resistors
allows the amplifier to self bias both input and output
to mid-supply.
C
RS
V Signal
RF
RG
RT
input capacitance of the ADS5500 limit the bandwidth
of the signal to 115 MHz (–3 dB). For testing, a signal
generator is used for the signal source. The
generator is an ac-coupled 50-Ω source. A band-pass
filter is inserted in series with the input to reduce
harmonics and noise from the signal source. Input
termination is accomplished via the 69.8-Ω resistor
and 0.22-µF capacitor to ground in conjunction with
the input impedance of the amplifier circuit. A 0.22-µF
capacitor and 49.9-Ω resistor are inserted to ground
across the 69.8-Ω resistor and 0.22-µF capacitor on
the alternate input to balance the circuit. Gain is a
function of the source impedance, termination, and
348-Ω feedback resistor. See Table 3 for component
values to set proper 50-Ω termination for other
common gains. A split power supply of +4 V and –1 V
is used to set the input and output common-mode
voltages to approximately mid-supply while setting
the input common-mode of the ADS5500 to the
recommended +1.55 V. This maintains maximum
headroom on the internal transistors of the THS4509
to ensure optimum performance.
VIN
From
50-W
source
V S+= 3V to 5V
100 W
C
V OUTRG
THS 4509
C
RT
C
100 W
THS 4509
CM
V S-
49.9 W
100 W2.7 pF
CM
69.8 W
0.22 mF
RF
14 -bit,
125 MSPS
A IN +
ADS5500
A IN - CM
49.9 W
-1 V
0.22 mF
348 W
0.1 mF
0.1 mF
Figure 87. THS4509 + ADS5500 Circuit
Figure 86. THS4509 AC-Coupled Single Supply
THS4509 + ADS5500 Combined Performance
09
The THS4509 is designed to be a high performance
drive amplifier for high performance data converters
like the ADS5500 14-bit 125-MSPS ADC. Figure 87
shows a circuit combining the two devices, and
Figure 88 shows the combined SNR and SFDR
performance versus frequency with –1-dBFS input
signal level sampling at 125 MSPS. The THS4509
amplifier circuit provides 10 dB of gain, converts the
11 001
09
08
07
06
05
04
03
single-ended input 0to
differential,
and
sets
the
proper
input common-mode voltage to the ADS5500. The
100-Ω resistors and 2.7-pF capacitor between the
THS4509 outputs and ADS5500 inputs along with the
58
28
100 W
0.22 mF
RO
V OUT+
RS
4V
69.3 W
RO
348 W
)cBd( RDFS
08
57
)SFBd( RNS
07
56
02
01
zHM - ycneuqerF tupnI
Figure 88. THS4509 + ADS5500 SFDR and SNR
Performance versus Frequency
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
Figure 89 shows the two-tone FFT of the THS4509 +
ADS5500 circuit with 65-MHz and 70-MHz input
frequencies. The SFDR is 90 dBc.
From
50-W
source
V IN
348 W
100 W
5V
69 .8 W
THS4509
100
49 .9 W
225 W
2 .7 pF
CM
69 .8 W
0.22 mF
14-bit,
105 MSPS
A IN+
ADS 5424
A IN– VBG
225 W
0.22 mF
0.22 mF
348 W
49.9 W
0.1 mF
0.1 mF
Figure 90. THS4509 + ADS5424 Circuit
59
)cBd( RDFS
09
58
Figure 89. THS4509 + ADS5500 Two-Tone FFT
with 65-MHz and 70-MHz Input
08
)SFBd( RNS
57
THS4509 + ADS5424 Combined Performance
Figure 90 shows the THS4509 driving the ADS5424
ADC, and Figure
their
SNR
07 91 shows
06
05 combined
04
03 and 02
SFDR performance versus frequency with –1-dBFS
input signal level and sampling at 80 MSPS.
As before, the THS4509 amplifier provides 10 dB of
gain, converts the single-ended input to differential,
and sets the proper input common-mode voltage to
the ADS5424. Input termination and circuit testing is
the same as previously described for the THS4509 +
ADS5500 circuit.
07
01
zHM - ycneuqerF tupnI
Figure 91. THS4509 + ADS5424 SFDR and
SNR Performance vs Frequency
The 225-Ω resistors and 2.7-pF capacitor between
the THS4509 outputs and ADS5424 inputs (along
with the input capacitance of the ADC) limit the
bandwidth of the signal to about 100 MHz (–3 dB).
Since
the
ADS5424's
recommended
input
common-mode voltage is 2.4 V, the THS4509 is
operated from a single power-supply input with
VS+ = 5 V and VS– = 0 V (ground).
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
29
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Layout Recommendations
It is recommended to follow the layout of the external
components near the amplifier, ground plane
construction, and power routing of the EVM as
closely as possible. General guidelines are:
1. Signal routing should be direct and as short as
possible into and out of the op amp circuit.
2. The feedback path should be short and direct
avoiding vias.
3. Ground or power planes should be removed from
directly under the amplifier’s input and output
pins.
4. An output resistor is recommended on each
output, as near to the output pin as possible.
5. Two 10-µF and two 0.1-µF power-supply
decoupling capacitors should be placed as near
to the power-supply pins as possible.
6. Two 0.1-µF capacitors should be placed between
the CM input pins and ground. This limits noise
coupled into the pins. One each should be placed
to ground near pin 4 and pin 9.
7. It is recommended to split the ground pane on
layer 2 (L2) and to use a solid ground on layer 3
(L3). A single-point connection should be used
between each split section on L2 and L3.
30
8. A single-point connection to ground on L2 is
recommended for the input termination resistors
R1 and R2. This should be applied to the input
gain resistors if termination is not used.
9. The THS4509 recommended PCB footprint is
shown in Figure 92.
441.0
940.0
210.0
1 niP
5900.0
510.0
441.0
5910.0 5070.0
010.0
saiv
230.0
030.0
5420.0
weiV p
To
Figure 92. QFN Etch and Via Pattern
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
THS4509-Q1
www.ti.com........................................................................................................................................................................................... SLOS547 – NOVEMBER 2008
THS4509 EVM
Figure 93 is the THS4509 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown in Figure 94, and
Table 4 is the bill of material for the EVM as supplied from TI.
DNG
V−S
5J
V+S
4J
6J
EEV
1.0 µ F
1PT
9C
01C
1.0 µ F 01
CCV
01 µ F
4C
µ F
1J
21R
9.94
51C
Ω 22.0
843
Ω
3R
001
µ F
1U
4R
3
V+O
−
11
2R
8.96
mcoV
Ω
001
V−O
01
daPrwP
4
51 31
961 41
EEV
Ω
CCV
CCV
6 8
7
+
2J
6R
9R
nepo
7R
6.68 Ω
8R
11R
8.96
6.68 Ω
TW1−1TDA_RMFX
01R
nepo
3J
1T
6
Ω
1C
nepo
1
8C
nepo
5
3
4
7C
nepo
2C
nepo
7J
843 Ω
3PT
2PT
41C
1.0 µF
11C
1.0
µ F
21C
8J
DP
2
1.01.0 µ F
351C
C
Ω
5
21
Ω
µ F
3C
5R
1R
8.96
01 01 µ F
6C
EEV
µF
Figure 93. THS4509 EVAL1 EVM Schematic
Figure 94. THS4509 EVAL1 EVM Layer 1 Through 4
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
31
THS4509-Q1
SLOS547 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Table 4. THS4509 EVAL1 EVM Bill of Materials
ITEM
DESCRIPTION
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER
1
CAP, 10.0 F, Ceramic, X5R, 6.3 V
0805
C3, C4, C5, C6
4
2
CAP, 0.1 F, Ceramic, X5R, 10 V
0402
C9, C10, C11, C12, C13, C14
6
(AVX) 08056D106KAT2A
(AVX) 0402ZD104KAT2A
3
CAP, 0.22 F, Ceramic, X5R, 6.3 V
0402
C15
1
(AVX) 04026D224KAT2A
4
OPEN
0402
C1, C2, C7, C8
4
5
OPEN
0402
R9, R10
2
6
Resistor, 49.9 Ω, 1/16 W, 1%
0402
R12
1
(KOA) RK73H1ETTP49R9F
8
Resistor, 69.8 Ω, 1/16 W, 1%
0402
R1, R2, R11
3
(KOA) RK73H1ETTP69R8F
9
Resistor, 86.6 Ω, 1/16 W, 1%
0402
R7, R8
2
(KOA) RK73H1ETTP86R6F
10
Resistor, 100 Ω, 1/16 W, 1%
0402
R3, R4
2
(KOA) RK73H1ETTP1000F
11
Resistor, 348 Ω, 1/16 W, 1%
0402
R5, R6
2
(KOA) RK73H1ETTP3480F
12
Transformer, RF
T1
1
(MINI-CIRCUITS) ADT1-1WT
13
Jack, banana receptacle, 0.25" diameter
hole
J4, J5, J6
3
(HH SMITH) 101
14
OPEN
J1, J7, J8
3
15
Connector, edge, SMA PCB Jack
J2, J3
2
(JOHNSON) 142-0701-801
16
Test point, Red
TP1, TP2, TP3
3
(KEYSTONE) 5000
17
IC, THS4509
U1
1
(TI) THS4509RGT
18
Standoff, 4-40 HEX, 0.625" length
4
(KEYSTONE) 1808
19
Screw, Phillips, 4-40, 0.250"
4
SHR-0440-016-SN
20
Printed circuit board
1
(TI) EDGE# 6468901
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the following table.
Input Range, VS+ to VS–
3.0 V to 6.0 V
Input range, VI
3.0 V to 6.0 V not to exceed VS+ or VS-
Output range, VO
3.0 V to 6.0 V not to exceed VS+ or VS-
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
32
www.BDTIC.com/TI
Submit Documentation Feedback
Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): THS4509-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
THS4509QRGTRQ1
ACTIVE
QFN
RGT
Pins Package Eco Plan (2)
Qty
16
250
Green (RoHS &
no Sb/Br)
Lead/Ball Finish
CU NIPDAU
MSL Peak Temp (3)
Level-2-260C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4509-Q1 :
• Catalog: THS4509
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
www.BDTIC.com/TI
Addendum-Page 1
www.BDTIC.com/TI
www.BDTIC.com/TI
www.BDTIC.com/TI
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DLP® Products
www.dlp.com
Communications and
Telecom
www.ti.com/communications
DSP
dsp.ti.com
Computers and
Peripherals
www.ti.com/computers
Clocks and Timers
www.ti.com/clocks
Consumer Electronics
www.ti.com/consumer-apps
Interface
interface.ti.com
Energy
www.ti.com/energy
Logic
logic.ti.com
Industrial
www.ti.com/industrial
Power Mgmt
power.ti.com
Medical
www.ti.com/medical
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
RFID
www.ti-rfid.com
Space, Avionics &
Defense
www.ti.com/space-avionics-defense
RF/IF and ZigBee® Solutions www.ti.com/lprf
Video and Imaging
www.ti.com/video
Wireless
www.ti.com/wireless-apps
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2010, Texas Instruments Incorporated
www.BDTIC.com/TI