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Download VERY LOW-POWER, HIGH-SPEED, RAIL-TO-RAIL INPUT AND OUTPUT VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER THS4281 FEATURES
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THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 VERY LOW-POWER, HIGH-SPEED, RAIL-TO-RAIL INPUT AND OUTPUT VOLTAGE-FEEDBACK OPERATIONAL AMPLIFIER Check for Samples: THS4281 FEATURES 1 • • 23 • • • • • • • • • DESCRIPTION Very Low Quiescent Current: 750 μA (at 5 V) Rail-to-Rail Input and Output: – Common-Mode Input Voltage Extends 400 mV Beyond the Rails – Output Swings Within 150 mV From the Rails Wide –3-dB Bandwidth at 5 V: – 90 MHz at Gain = +1, 40 MHz at Gain = +2 High Slew Rate: 35 V/μs Fast Settling Time (2-V Step): – 78 ns to 0.1% – 150 ns to 0.01% Low Distortion at Gain = +2, VO = 2-VPP, 5 V: – –91 dBc at 100 kHz, –67 dBc at 1 MHz Input Offset Voltage: 2.5 mV (Max at +25°C) Output Current > 30 mA (10-Ω Load, 5 V) Low Voltage Noise of 12.5 nV/√Hz Supply Voltages: +2.7 V, 3 V, +5 V, ±5 V, +15 V Packages: SOT23, MSOP, and SOIC Fabricated using the BiCom-II process, the THS4281 is a low-power, rail-to-rail input and output, voltage-feedback operational amplifier designed to operate over a wide power-supply range of 2.7-V to 15-V single supply, and ±1.35-V to ±7.5-V dual supply. Consuming only 750 μA with a unity gain bandwidth of 90 MHz and a high 35-V/μs slew rate, the THS4281 allows portable or other power-sensitive applications to realize high performance with minimal power. To ensure long battery life in portable applications, the quiescent current is trimmed to be less than 900 μA at +25°C, and 1 mA from –40°C to +85°C. The THS4281 is a true single-supply amplifier with a specified common-mode input range of 400 mV beyond the rails. This allows for high-side current sensing applications without phase reversal concerns. Its output swings to within 40 mV from the rails with 10-kΩ loads, and 150 mV from the rails with 1-kΩ loads. The THS4281 has a good 0.1% settling time of 78 ns, and 0.01% settling time of 150 ns. The low THD of –87 dBc at 100 kHz, coupled with a maximum offset voltage of less than 2.5 mV, makes the THS4281 a good match for high-resolution ADCs sampling less than 2 MSPS. APPLICATIONS • • • • • Portable/Battery-Powered Applications High Channel Count Systems ADC Buffer Active Filters Current Sensing The THS4281 is offered in a space-saving SOT23-5 package, a small MSOP-8 package, and the industry standard SOIC-8 package. 470 pF V BAT 500 W I 2.5 kW RSENSE V OUT = I RSENSE VBAT VBAT 0.2 W − 500 W + Load 100 W 470 pF THS4281 +IN ADS8320 −IN 10 nF 2.5 kW VBAT/2 High-Side, Low Power Current-Sensing System 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. FilterPro is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. www.BDTIC.com/TI PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2004–2009, Texas Instruments Incorporated THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). UNIT Supply voltage, VS– to VS+ 16.5 V Input voltage, VI ±VS ± 0.5 V Differential input voltage, VID ±2 V Output current, IO ±100 mA Continuous power dissipation See Dissipation Ratings Table Maximum junction temperature, any condition, (2) TJ +150°C Maximum junction temperature, continuous operation, long-term reliability (2) TJ +125°C Storage temperature range, Tstg ESD ratings (1) (2) –65°C to +150°C HBM 3500 V CDM 1500 V MM 100 V The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may result in reduced reliability and/or lifetime of the device. recommended operating conditions. RECOMMENDED OPERATING CONDITIONS Dual supply Supply voltage, (VS+ and VS –) MIN MAX ±1.35 ±8.25 2.7 16.5 Single supply UNIT V DISSIPATION RATINGS TABLE PER PACKAGE (1) (2) 2 PACKAGE θJC (°C/W) θJA (1) (°C/W) DBV (5) 55 255.4 D (8) 38.3 DGK (8) 71.5 POWER RATING (2) TA < +25°C TA = +85°C 391 mW 156 mW 97.5 1.02 W 410 mW 180.8 553 mW 221 mW This data was taken using the JEDEC standard High-K test PCB. Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and long term reliability. www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 PACKAGING/ORDERING INFORMATION (1) PACKAGED DEVICES DEVICE MARKING PACKAGE TYPE AON SOT23 - 5 –– SOIC - 8 AOO MSOP - 8 THS4281DBVT THS4281DBVR THS4281D THS4281DR THS4281DGK THS4281DGKR (1) TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 3000 Rails, 75 Tape and Reel, 2500 Rails, 75 Tape and Reel, 2500 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. PIN CONFIGURATIONS TOP VIEW DBV TOP VIEW D and DGK THS4281 VOUT 1 VS− 2 IN+ 3 THS4281 5 4 VS+ NC 1 8 NC IN− 2 7 VS+ IN+ 3 6 VOUT VS− 4 5 NC IN− NOTE: NC indicates there is no internal connection to these pins. www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 3 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS, VS = 3 V (VS+ = 3 V, VS– = GND) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ to 1.5 V, unless otherwise noted TYP PARAMETER CONDITIONS +25°C OVER TEMPERATURE +25°C 0°C to +70°C –40°C to +85°C UNITS MIN/ MAX AC PERFORMANCE G = +1, VO = 100 mVPP, RF = 34 Ω 83 MHz Typ G = +2, VO = 100 mVPP, RF = 1.65 kΩ 40 MHz Typ G = +5, VO = 100 mVPP, RF = 1.65 kΩ 8 MHz Typ G = +10, VO = 100 mVPP, RF = 1.65 kΩ 3.8 MHz Typ 0.1-dB Flat Bandwidth G = +2, VO = 100 mVPP, RF = 1.65 kΩ 20 MHz Typ Full-Power Bandwidth G = +2, VO = 2 VPP 8 MHz Typ G = +1, VO = 2-V Step 26 V/μs Typ Small-Signal Bandwidth Slew Rate G = –1, VO = 2-V Step 27 V/μs Typ Settling time to 0.1% G = –1, VO = 1-V Step 80 ns Typ Settling time to 0.01% G = –1, VO = 1-V Step 155 ns Typ Rise/Fall Times G = +1, VO = 2-V Step 55 ns Typ Harmonic Distortion G = +2, VO = 2 VPP –52 dBc Typ –52 dBc Typ –69 dBc Typ –71 dBc Typ 0.003 % Typ Second Harmonic Distortion Third Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion f = 1 MHz, RL = 1 kΩ f = 100 kHz, RL = 1 kΩ VO = 1 VPP, f = 10 kHz THD + N VO = 2 VPP, f = 10 kHz Differential Gain (NTSC/PAL) Differential Phase (NTSC/PAL) G = +2, RL = 150 Ω 0.03 % Typ 0.05/0.08 % Typ 0.25/0.35 ° Typ Input Voltage Noise f = 100 kHz 12.5 nA/√Hz Typ Input Current Noise f = 100 kHz 1.5 pA/√Hz Typ Open-Loop Voltage Gain (AOL) 95 dB Typ Input Offset Voltage 0.5 Max DC PERFORMANCE 2.5 Average Offset Voltage Drift Input Bias Current Average Bias Current Drift VCM = 1.5 V Input Offset Current 3.5 3.5 mV ±7 ±7 μV/°C Typ 1 μA Max 0.5 0.8 1 ±2 ±2 nA/°C Typ 0.1 0.4 0.5 0.5 μA Max ±2 ±2 nA/°C Typ Min Average Offset Current Drift INPUT CHARACTERISTICS Common-Mode Input Range –0.4/3.4 –0.3/3.3 –0.1/3.1 –0.1/3.1 V Common-Mode Rejection Ratio VCM = 0 V to 3 V 92 75 70 70 dB Min Input Resistance Common-mode 100 MΩ Typ Input Capacitance Common-mode/Differential 0.8/1.2 pF Typ 4 www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS, VS = 3 V (VS+ = 3 V, VS– = GND) (continued) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ to 1.5 V, unless otherwise noted TYP PARAMETER CONDITIONS +25°C OVER TEMPERATURE +25°C 0°C to +70°C –40°C to +85°C UNITS MIN/ MAX V Typ OUTPUT CHARACTERISTICS Output Voltage Swing RL = 10 kΩ 0.04/2.96 RL = 1 kΩ 0.1/2.9 0.14/2.86 0.2/2.8 0.2/2.8 V Min Output Current (Sourcing) RL = 10 Ω 23 18 15 15 mA Min Output Current (Sinking) RL = 10 Ω 29 22 19 19 mA Min Output Impedance f = 1 MHz 1 Ω Typ POWER SUPPLY Maximum Operating Voltage 3 16.5 16.5 16.5 V Max Minimum Operating Voltage 3 2.7 2.7 2.7 V Min Maximum Quiescent Current 0.75 0.9 0.98 1.0 mA Max Minimum Quiescent Current 0.75 0.6 0.57 0.55 mA Min Power-Supply Rejection (+PSRR) VS+ = 3.25 V to 2.75 V, VS– = 0 V 90 70 65 65 dB Min Power-Supply Rejection (–PSRR) VS+ = 3 V, VS– = 0 V to 0.65 V 90 70 65 65 dB Min www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 5 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS, VS = 5 V (VS+ = 5 V, VS– = GND) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ to 2.5 V, unless otherwise noted TYP PARAMETER CONDITIONS +25°C OVER TEMPERATURE +25°C 0°C to +70°C –40°C to +85°C UNITS MIN/ MAX AC PERFORMANCE G = +1, VO = 100 mVPP, RF = 34 Ω 90 MHz Typ G = +2, VO = 100 mVPP, RF = 2 kΩ 40 MHz Typ G = +5, VO = 100 mVPP, RF = 2 kΩ 8 MHz Typ G = +10, VO = 100 mVPP, RF = 2 kΩ 3.8 MHz Typ 0.1-dB Flat Bandwidth G = +2, VO = 100 mVPP, RF = 2 kΩ 20 MHz Typ Full-Power Bandwidth G = +2, VO = 2 VPP 9 MHz Typ G = +1, VO = 2-V Step 31 V/μs Typ G = –1, VO = 2-V Step 34 V/μs Typ Small-Signal Bandwidth Slew Rate Settling Time to 0.1% G = –1, VO = 2-V Step 78 ns Typ Settling Time to 0.01% G = –1, VO = 2-V Step 150 ns Typ Rise/Fall Times G = +1, VO = 2-V Step 48 ns Typ Harmonic Distortion G = +2, VO = 2 VPP –67 dBc Typ –76 dBc Typ Second Harmonic Distortion Third Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion THD + N Differential Gain (NTSC/PAL) Differential Phase (NTSC/PAL) f = 1 MHz, RL = 1 kΩ –92 dBc Typ –106 dBc Typ VO = 2 VPP, f = 10 kHz 0.0009 % Typ VO = 4 VPP, f = 10 kHz 0.0005 % Typ 0.11/0.17 % Typ 0.11/0.14 ° Typ f = 100 kHz, RL = 1 kΩ G = +2, RL = 150 Ω Input Voltage Noise f = 100 kHz 12.5 nV/√Hz Typ Input Current Noise f = 100 kHz 1.5 pA/√Hz Typ dB Min Max DC PERFORMANCE Open-Loop Voltage Gain (AOL) 105 85 80 80 Input Offset Voltage 0.5 2.5 3.5 3.5 mV ±7 ±7 μV/°C Typ 1 1 μA Max ±2 ±2 nA/°C Typ 0.5 0.5 μA Max ±2 ±2 nA/°C Typ Average Offset Voltage Drift Input Bias Current Average Bias Current Drift VCM = 2.5 V Input Offset Current 0.5 0.1 Average Offset Current Drift 6 0.8 0.4 www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS, VS = 5 V (VS+ = 5 V, VS– = GND) (continued) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ to 2.5 V, unless otherwise noted TYP PARAMETER CONDITIONS OVER TEMPERATURE +25°C +25°C 0°C to +70°C –0.4/5.4 –0.3/5.3 –0.1/5.1 100 85 80 –40°C to +85°C UNITS MIN/ MAX –0.1/5.1 V Min 80 dB Min INPUT CHARACTERISTICS Common-Mode Input Range Common-Mode Rejection Ratio VCM = 0 V to 5 V Input Resistance Common-mode Input Capacitance Common-mode/Differential 100 MΩ Typ 0.8/1.2 pF Typ RL = 10 kΩ 0.04/4.96 V Typ OUTPUT CHARACTERISTICS Output Voltage Swing RL = 1 kΩ 0.15/4.85 0.2/4.8 V Min Output Current (Sourcing) RL = 10 Ω 33 24 0.25/4.75 0.25/4.75 20 20 mA Min Output Current (Sinking) RL = 10 Ω 44 30 25 25 mA Min Output Impedance f = 1 MHz 1 Ω Typ V Max POWER SUPPLY Maximum Operating Voltage 5 16.5 16.5 16.5 Minimum Operating Voltage 5 2.7 2.7 2.7 V Min Maximum Quiescent Current 0.75 0.9 0.98 1.0 mA Max Minimum Quiescent Current 0.75 0.6 0.57 0.55 mA Min Power-Supply Rejection (+PSRR) VS+ = 5.5 V to 4.5 V, VS– = 0 V 100 80 75 75 dB Min Power-Supply Rejection (–PSRR) VS+ = 5 V, VS– = 0 V to 1.0 V 100 80 75 75 dB Min www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 7 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS, VS = ±5 V At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ, unless otherwise noted TYP PARAMETER CONDITIONS +25°C OVER TEMPERATURE +25°C 0°C to +70°C –40°C to +85°C UNITS MIN/ MAX AC PERFORMANCE G = +1, VO = 100 mVPP, RF = 34 Ω 95 MHz Typ G = +2, VO = 100 mVPP 40 MHz Typ G = +5, VO = 100 mVPP 8 MHz Typ G = +10, VO = 100 mVPP 3.8 MHz Typ 0.1-dB Flat Bandwidth G = +2, VO = 100 mVPP 20 MHz Typ Full-Power Bandwidth G = +1, VO = 2 VPP 9.5 MHz Typ G = +1, VO = 2-V Step 35 V/μs Typ Small-Signal Bandwidth Slew Rate G = –1, VO = 2-V Step 35 V/μs Typ Settling Time to 0.1% G = –1, VO = 2-V Step 78 ns Typ Settling Time to 0.01% G = –1, VO = 2-V Step 140 ns Typ Rise/Fall Times G = +1, VO = 2-V Step 45 ns Typ Harmonic Distortion G = +2, VO = 2 VPP –69 dBc Typ –76 dBc Typ –93 dBc Typ Second Harmonic Distortion Third Harmonic Distortion Second Harmonic Distortion Third Harmonic Distortion f = 1 MHz, RL = 1 kΩ f = 100 kHz, RL = 1 kΩ VO = 2 VPP, f = 10 kHz THD + N VO = 8 VPP, f = 10 kHz Differential Gain (NTSC/PAL) Differential Phase (NTSC/PAL) G = +2, RL = 150 Ω –107 dBc Typ 0.0009 % Typ 0.0003 % Typ 0.03/0.03 % Typ Typ 0.08/0.1 ° Input Voltage Noise f = 100 kHz 12.5 nV/√Hz Typ Input Current Noise f = 100 kHz 1.5 pA/√Hz Typ DC PERFORMANCE Open-Loop Voltage Gain (AOL) 108 90 85 85 dB Min Input Offset Voltage 0.5 2.5 3.5 3.5 mV Max ±7 ±7 μV/°C Typ 0.5 0.8 1 1 μA Max ±2 ±2 nA/°C Typ 0.1 0.4 0.5 0.5 μA Max ±2 ±2 nA/°C Typ V Min Average Offset Voltage Drift Input Bias Current Average Bias Current Drift VCM = 0 V Input Offset Current Average Offset Current Drift INPUT CHARACTERISTICS Common-Mode Input Range ±5.4 ±5.3 ±5.1 ±5.1 90 85 85 Common-Mode Rejection Ratio VCM = –5 V to +5 V 107 dB Min Input Resistance Common-mode 100 MΩ Typ Input Capacitance Common-mode/Differential 0.8/1.2 pF Typ RL = 10 kΩ ±4.93 V Typ RL = 1 kΩ ±4.8 ±4.6 ±4.5 ±4.5 V Min Output Current (Sourcing) RL = 10 Ω 48 35 30 30 mA Min Output Current (Sinking) RL = 10 Ω 60 45 40 40 mA Min Output Impedance f = 1 MHz 1 Ω Typ OUTPUT CHARACTERISTICS Output Voltage Swing 8 www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 ELECTRICAL CHARACTERISTICS, VS = ±5 V (continued) At G = +2, RF = 2.49 kΩ, and RL = 1 kΩ, unless otherwise noted TYP PARAMETER CONDITIONS OVER TEMPERATURE +25°C +25°C 0°C to +70°C –40°C to +85°C UNITS MIN/ MAX Maximum Operating Voltage ±5 ±8.25 ±8.25 ±8.25 V Max Minimum Operating Voltage ±5 ±1.35 ±1.35 ±1.35 V Min Maximum Quiescent Current 0.8 0.93 1.0 1.05 mA Max Minimum Quiescent Current 0.8 0.67 0.62 0.6 mA Min POWER SUPPLY Power-Supply Rejection (+PSRR) VS+ = 5.5 V to 4.5 V, VS– = 5.0 V 100 80 75 75 dB Min Power-Supply Rejection (–PSRR) VS+ = 5 V, VS– = –5.5 V to –4.5 V 100 80 75 75 dB Min www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 9 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS QUIESCENT CURRENT vs SUPPLY VOLTAGE (VS = 3 V, VS = 5 V) INPUT OFFSET VOLTAGEvs COMMON-MODE INPUT VOLTAGE 1000 900 TA = 25°C 800 TA = −40°C 700 600 500 3 4 5 6 7 8 0.5 0 −0.5 −1 VS = 5 V −1.5 VS = 3 V −2 −2.5 9 10 11 12 13 14 15 0 −0.5 −1 −1.5 −2 1 2 3 4 5 6 VICR − Common-Mode Input Voltage − V Figure 1. Figure 2. Figure 3. (VS = 15 V) INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE POSITIVE VOLTAGE HEADROOM vs SOURCE CURRENT NEGATIVE VOLTAGE HEADROOM vs SINK CURRENT 4 4 Load Tied to VS/2 + Voltage Headroom − (Vs+ − Vout) VS = 15 V 0.5 0 −0.5 −1 −1.5 −2 3.5 15 V 3 2.5 2 5V 1.5 1 0.5 0 −1 0 2 4 6 8 10 12 14 16 VICR − Common-Mode Input Voltage − V 20 30 40 50 2 5V 1.5 1 0.5 60 0 10 20 30 40 Figure 6. (VS = 5 V) OUTPUT VOLTAGE vs LOAD RESISTANCE (VS = ±5 V) OUTPUT VOLTAGE vs LOAD RESISTANCE (VS = 15 V) OUTPUT VOLTAGE vs LOAD RESISTANCE 4 VS = ±5 V Load Tied to GND 3 VO − Output Voltage − V VS = 5 V Load Tied to VS/2 3 2.5 2 1.5 1 2 1 0 −1 −2 −3 −4 0.5 −5 0 100 1k RL − Load Resistance − Ω Figure 7. 10 k 10 100 1k RL − Load Resistance − Ω Figure 8. 10 k 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 60 VS = 15 V Load Tied to VS/2 10 100 1k 10 k RL − Load Resistance − Ω Figure 9. www.BDTIC.com/TI Submit Documentation Feedback 50 −Iout − Sink Current − mA Figure 5. 5 10 15 V 2.5 Figure 4. 5 3.5 10 ±5 V 3 +Iout − Source Current − mA 4.5 4 3.5 0 0 VO − Output Voltage − V −2.5 Load Tied to VS/2 ±5 V − Voltage Headroom − (Vout − Vs−) 1 V OS − Input Offset Voltage − mV VS = ±5 V 0.5 −2.5 −6 −5 −4 −3 −2 −1 0 −1 0 1 2 3 4 5 6 VICR − Common-Mode Input Voltage − V VCC − Supply Voltage − V VO − Output Voltage − V V OS − Input Offset Voltage − mV V OS − Input Offset Voltage − mV I Q − Quiescent Current −µ A 1 1 TA = 85°C 10 (VS = ±5 V) INPUT OFFSET VOLTAGE vs COMMON-MODE INPUT VOLTAGE Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS (continued) (VS = 2.7 V) FREQUENCY RESPONSE FREQUENCY RESPONSE 9 6 RF = 4 kΩ 6 3 VS = 5 V 2 RF = 4 kΩ VS = 2.7 V VS = ±5 V 1 0 6 Signal Gain − dB 4 9 VS = 15 V Signal Gain − dB Gain = 1, RF = 34 Ω, RL = 1 kΩ, VO = 100 mVPP 5 Signal Gain − dB (VS = 3 V) FREQUENCY RESPONSE RF = 1.65 kΩ RF = 1 kΩ 3 RF = 1.65 kΩ RF = 1 kΩ 3 −1 0 VS = 2.7 V Gain = 2, RL = 1 kΩ, VO = 0.1 VPP −2 −3 −4 0 −3 1 10 0.1 100 VS = 3 V Gain = 2, RL = 1 kΩ, VO = 0.1 VPP −3 0.1 10 Figure 10. Figure 11. Figure 12. (VS = 5 V) FREQUENCY RESPONSE (VS = ±5 V) FREQUENCY RESPONSE (VS = 2.7 V, VS = 3 V) 0.1-dB FREQUENCY RESPONSE 9 100 1 f − Frequency − MHz 1 10 f − Frequency − MHz 9 6.2 RF = 2 kΩ 3 0 RF = 1 kΩ 3 VS = ± 5 V, Gain = 2, RL = 1 kΩ, VO = 0.1 VPP 0.1 100 VS = 3 V 5.9 5.8 5.7 5.6 Gain = 2, RF = 1.65 kΩ, RL = 1 kΩ, VO = 0.1 VPP 5.5 −3 1 10 f − Frequency − MHz 1 10 f − Frequency − MHz 5.4 0.1 100 1 10 Figure 14. Figure 15. (VS = 5 V, ±5 V, 15 V) 0.1-dB FREQUENCY RESPONSE (VS = 2.7 V) FREQUENCY RESPONSE (VS = 3 V) FREQUENCY RESPONSE 24 6.1 20 VS = ± 5 V VS = 5 V 5.8 5.7 5.6 5.5 1 10 f − Frequency − MHz G=5 12 8 G=2 4 Gain = 2, RF = 2 kΩ (VS = 5 V), RF = 2.49 kΩ (VS = ±5 V, 15 V), RL = 1 kΩ, VO = 0.1 VPP 5.4 0.1 16 16 8 G=2 4 G = −1 0 0 −4 Figure 16. G=5 12 G = −1 100 VS = 3V, RF = 1.65 kΩ, RL = 1 kΩ, VO = 0.1 VPP G = 10 20 Signal Gain − dB Signal Gain − dB 6 5.9 24 VS = 2.7 V, RF = 1.65 kΩ, RL = 1 kΩ, VO = 0.1 VPP G = 10 VS = 15 V 100 f − Frequency − MHz Figure 13. 6.2 Signal Gain − dB RF = 2.49 kΩ 0 VS = 5 V Gain = 2, RL = 1 kΩ, VO = 0.1 VPP −3 0.1 6 6 Signal Gain − dB Signal Gain − dB Signal Gain − dB RF = 1 kΩ VS = 2.7 V 6.1 RF = 4 kΩ RF = 4 kΩ 6 100 f − Frequency − MHz 0.1 1 10 100 −4 0.1 1 10 f − Frequency − MHz f − Frequency − MHz Figure 17. Figure 18. www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 100 11 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) (VS = 5 V) FREQUENCY RESPONSE (VS = ±5 V) FREQUENCY RESPONSE 24 Signal Gain − dB Signal Gain − dB 20 G=5 12 G=2 8 4 16 12 G=2 8 12 G=2 8 4 G = −1 0 1 10 0 −4 0.1 100 −4 f − Frequency − MHz 1 10 f − Frequency − MHz Figure 19. Figure 20. Figure 21. (VS = 2.7 V) LARGE-SIGNAL FREQUENCY RESPONSE (VS = 5 V) LARGE-SIGNAL FREQUENCY RESPONSE (VS = ±5 V) LARGE-SIGNAL FREQUENCY RESPONSE 100 0.1 1 1 1 0.5 0.5 0.5 VO = 500 mVPP VO = 500 mVPP 0 −1 VO = 1 VPP −2 VO = 2 VPP −2.5 −3.5 −4 VO = 2 VPP −1 VO = 1 VPP −1.5 −2 VO = 2 VPP −2.5 Gain = 1, RF = 34 Ω, RL = 1 kΩ, VS = 5 V −3 Gain = 1, RF = 34 Ω, RL = 1 kΩ, VS = ± 5 V −3.5 −4 1 10 1 100 10 100 f − Frequency − MHz Figure 22. Figure 23. Figure 24. OPEN-LOOP GAIN vs FREQUENCY OUTPUT IMPEDANCE vs FREQUENCY REJECTION RATIO vs FREQUENCY 50 Gain 80 0 −25 70 −50 60 −75 Phase −100 40 −125 30 −150 20 −175 10 −200 0 −10 −225 100 1k −250 10k 100k 1 M 10 M 100 M f − Frequency − Hz 110 100 Gain = 1 RF = 2.5 kΩ VS = 5 V, ± 5 V, 15 V VS = 15 V and 5 V 100 90 10 1 0.1 CMRR 80 PSRR+ 70 60 50 PSRR− 40 30 20 10 0.01 100 k 0 1M 10 M 100 M f − Frequency − Hz Figure 25. f − Frequency − MHz 1000 25 Z o − Output Impedance − Ω 90 10 VO = 500 mVPP f − Frequency − MHz RL = 1 kΩ, VS = ±5 V 100 −0.5 −4 100 110 1 −2 −3.5 100 50 −1.5 −3 10 1 VO = 1 VPP −1 −2.5 Gain = 1, RF = 34 Ω, RL = 1 kΩ, VS = 2.7 V −3 −0.5 Rejection Ratios − dB −1.5 Signal Gain − dB Signal Gain − dB −0.5 1 10 f − Frequency − MHz 0 0 Phase − ° Signal Gain − dB G=5 G = −1 −4 0.1 Open-Loop Gain − dB 16 4 0 VS = 15 V, RF = 2.49 kΩ, RL = 1 kΩ, VO = 0.1 VPP G = 10 20 G=5 G = −1 12 24 VS = ±5 V, RF = 2.49 kΩ, RL = 1 kΩ, VO = 0.1 VPP G = 10 Signal Gain − dB 20 16 24 VS = 5 V, RF = 2 kΩ, RL = 1 kΩ, VO = 0.1 VPP G = 10 (VS = 15 V) FREQUENCY RESPONSE Figure 26. 1G 1k 10 k 100 k 10 M 100 M Figure 27. www.BDTIC.com/TI Submit Documentation Feedback 1M f − Frequency − Hz Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS (continued) NOISE vs FREQUENCY Vn 12.5 nV/rt(Hz) In 10 1.5 pA/rt(Hz) 60 Gain = −1, RF = 3 kΩ, RL = 1 kΩ, VS = 2.7 V 40 Gain = −1, RF = 3 kΩ, RL = 1 kΩ, VS = 5 V 50 Fall SR − Slew Rate − V/ µ s 100 (VS = 5 V) SLEW RATE 50 VS = 2.7 V to 15 V, TA = 27°C SR − Slew Rate − V/ µ s I n − Current Noise − pA/ Hz V n − Voltage Noise − nV/ Hz 1000 (VS = 2.7 V) SLEW RATE 30 Rise 20 10 40 Fall Rise 30 20 10 1 10 100 1K 10K 100K 0 f − Frequency − Hz 0.5 0.75 1 1.25 1.5 1.75 0 0.5 2 1 VO − Output Voltage − VPP (VS = ±5 V) SLEW RATE (VS = 15 V) SLEW RATE (VS = ±1.35 V) SETTLING TIME Fall Rise 30 20 Rise 100 80 Fall 60 40 Gain = −1 RL = 1 kΩ RF= 3 kΩ VS = ±1.35 V 1-V Step 0 −0.2 Fall 20 0 1.5 2 2.5 3 3.5 4 4.5 5 −0.6 0 VO − Output Voltage − VPP 1 2 3 4 5 6 7 8 9 10 11 12 VO − Output Voltage − VPP 0 20 40 60 Figure 32. Figure 33. (VS = ±1.35 V) SETTLING TIME (VS = ±2.5 V) SETTLING TIME (VS = ±2.5 V) SETTLING TIME 0.6 Fall 0.4 0.2 0 −0.2 −0.4 −0.6 1.5 1 1 0.8 Gain = −1 RL = 1 kΩ RF = 3 kΩ VS = ±2.5 V 0.5 0 100 Gain = −1 RL = 1 kΩ RF = 3 kΩ VS = ±2.5 V 2-V Step 0.6 % Error Gain = −1 RL = 1 kΩ RF= 3 kΩ VS = ±1.35 V 1-V Step Rise VO − Output Voltage − V 1 80 t − Time − ns Figure 31. 0.8 % Error 0.2 −0.4 10 4 Rise 0.4 120 VO − Output Voltage − V SR − Slew Rate − V/µ s SR − Slew Rate − V/ µ s Gain = −1, RF = 3 kΩ, RL = 1 kΩ, VS = 15 V 140 40 3.5 0.6 160 1 3 Figure 30. Gain = −1, RF = 3 kΩ, RL = 1 kΩ, VS = ±5 V 0.5 2.5 Figure 29. 50 0 2 Figure 28. 70 60 1.5 VO − Output Voltage − VPP 0.4 0.2 Fall −0.5 0 −1 −0.2 −0.8 Rise −1 −1.5 20 40 60 80 100 120 140 160 180 t − Time − ns Figure 34. 0 10 20 30 40 50 60 70 80 90 100 −0.4 40 60 80 Figure 35. 100 120 140 160 180 200 t − Time − ns t − Time − ns Figure 36. www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 13 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) (VS = ±5 V) SETTLING TIME 1.5 −30 1 Gain = −1 RL = 1 kΩ RF = 3 kΩ VS = ±5 V 2-V Step 0.6 0 % Error Gain = −1 RL = 1 kΩ RF= 3 kΩ VS = ±5 V 0.5 0.4 0.2 Rise −0.5 0 −1 −0.2 0 10 60 80 0.1 1 10 f − Frequency − MHz Figure 39. (Gain = +1) HARMONIC DISTORTION vs FREQUENCY (VS = 3 V, 3.3 V) HARMONIC DISTORTION vs FREQUENCY (Gain = +2) HARMONIC DISTORTION vs FREQUENCY VS = 2.7 V, HD3 −60 VS = 5 V, HD2 −70 VS = ±5 V, 15 V HD2 −80 −90 VS = 3.3 V, 2 VPP, HD2 −85 VS = 5 V,±5 V, 15 V HD3 −90 VS = 3.3 V, 2 VPP, HD3 −95 VS = 3 V, 1 VPP, HD2 −100 VS = 3 V, 1 VPP, HD3 −105 −110 VS = 3.3 V, 1 VPP, HD2 −115 −120 VS = 3.3 V, 1 VPP, HD3 −125 −110 0.1 1 100 f − Frequency − MHz 1k −50 −60 VS = 2.7 V, HD2 −70 −80 VS = 2.7 V, HD3 −90 VS = 5 V ±5 V, 15 V HD2 −100 −110 VS = 5 V ±5 V, 15 V HD3 −120 Gain = 2, RL = 1 kΩ, to VS/2 −130 10 10 VO = 1 VPP, Gain = 2, RL = 1 kΩ, to VS/2 −40 Harmonic Distortion − dBc −50 −30 −80 VO = 2 VPP, Gain = 1, RL = 1 kΩ, to VS/2 VS = 2.7 V, HD2 Harmonic Distortion − dBc −130 100 10 k 20 k f − Frequency − Hz 1k 10 k 100 k f − Frequency − Hz 1M Figure 40. Figure 41. Figure 42. (Gain = +2) HARMONIC DISTORTION vs FREQUENCY HARMONIC DISTORTION vs LOAD RESISTANCE (VS = 2.7 V, 5 V) HARMONIC DISTORTION vs OUTPUT VOLTAGE −60 −30 VO = 2 VPP, Gain = 2, RL = 1 kΩ, to VS/2 −50 −70 Harmonic Distortion − dBc −40 −60 VS = 2.7 V, 3 V, HD2 −80 VS = 3 V, HD3 VS = 2.7 V, HD3 −100 VS = 5 V ±5 V, 15 V HD2 −110 −130 100 1k 10 k 100 k f − Frequency − Hz 1M VS = 3 V, 2 VPP, HD3 −90 VS = 3 V, 1 VPP, HD2 −70 −100 VS = 3 V, 1 VPP, HD3 VS = 5V and ±5V, 2VPP, HD3 −120 VS = 5 V ±5 V, 15 V HD3 −120 VS = 3 V, 2 VPP, HD2 −80 −110 10 M Figure 43. 1k Gain = 2, RL = 1 kΩ, to VS/2, f = 10 kHz VS = 2.7 V, HD2 −80 −90 −100 VS = 2.7 V, HD3 −110 VS = 5 V, HD2 −120 VS = 5 V, and ±5 V, 2 VPP, HD2 −130 100 10 M −60 Gain = 2 f = 10 khz Harmonic Distortion − dBc Harmonic Distortion − dBc VS = 5 V,±5 V, 15 V HD3 t − Time − ns −100 Harmonic Distortion − dBc −90 Figure 38. −40 14 VS = ±5 V, 15 V HD2 −80 Figure 37. −30 −90 −70 100 120 140 160 180 200 t − Time − ns −70 VS = 2.7 V, HD3 VS = 5 V, HD2 −60 −110 −0.4 40 20 30 40 50 60 70 80 90 100 −50 −100 Fall −1.5 VO = 1 VPP, Gain = 1, RL = 1 kΩ, to VS/2 VS = 2.7 V, HD2 −40 Harmonic Distortion − dBc 0.8 1 VO − Output Voltage − V (Gain = +1) HARMONIC DISTORTION vs FREQUENCY (VS = ±5 V) SETTLING TIME VS = 5 V, HD3 10 k RL − Load Resistance − W Figure 44. 100 k −130 0.1 1 VO − Output Voltage − VPP Figure 45. www.BDTIC.com/TI Submit Documentation Feedback 10 Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS (continued) Harmonic Distortion − dBc −70 (VS = 2.7 V) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY −60 Gain = 2, RL = 1 kΩ, to VS/2, f = 10 kHz VS = 3 V, HD2 Gain = 2, RL = 1 kΩ, to VS/2, f = 10 kHz −70 Harmonic Distortion − dBc −60 (VS = 3.3 V, 15 V) HARMONIC DISTORTION vs OUTPUT VOLTAGE −80 −90 VS = 3 V, HD3 −100 VS = ±5 V, HD2 −110 VS = 3.3 V, HD3 −80 −90 −100 VS = 3.3 V, HD2 −110 VS =15 V, HD2 −120 −120 VS = ±5 V, HD3 VS = 15 V, HD3 −130 −130 1 VO − Output Voltage − VPP 0.1 10 1 10 20 0.100 VO = 2.5 VPP VO = 2 VPP VO = 1 VPP VO = 0.5 VPP 0.010 VS = 2.7 V, Bandwidth = 600 kHz, Gain = 2, RF = 2 kΩ, RL = 1 kΩ to VS/2 0.001 10 VO − Output Voltage − VPP 100 1k 10 k 200 k Figure 46. Figure 47. Figure 48. (VS = 3 V) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY (VS = 5 V) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY (VS = ±5 V) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY THD+N −Total Harmonic Distortion + Noise − % THD+N −Total Harmonic Distortion + Noise − % f − Frequency − Hz THD+N −Total Harmonic Distortion + Noise − % 0.1 THD+N −Total Harmonic Distortion + Noise − % (VS = 3 V, ±5 V) HARMONIC DISTORTION vs OUTPUT VOLTAGE 0.100 VO = 2 VPP VO = 2.8 VPP 0.010 VO = 1 VPP VS = 3 V, Bandwidth = 600 kHz, Gain = 2, RF = 2 kΩ, RL = 1 kΩ to VS/2 0.001 10 100 1k 10 k 200 k 0.1000 VS = 5 V, Bandwidth = 600 kHz, Gain = 2, RF = 2 kΩ, RL = 1 kΩ to VS/2 VO = 4.8 VPP 0.0100 VO = 4.6 VPP 0.0010 VO = 4 VPP 0.0001 10 100 f − Frequency − Hz 1k 10 k 200 k 0.1000 VS = ±5 V, Bandwidth = 600 kHz, Gain = 2, RF = 2 kΩ, RL = 1 kΩ 0.0010 VO = 9.6 VPP VO = 9 VPP 0.0100 VO = 4 VPP VO = 8 VPP 0.0001 10 100 1k 10 k 200 k f − Frequency − Hz f − Frequency − Hz (VS = 15 V) TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY (f = 1 kHz) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE (f = 10 kHz) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE 0.1000 VS = 15 V, Bandwidth = 600 kHz, Gain = 2, RF = 2 kΩ, RL = 1 kΩ , to VS/2 0.0100 VO = 14.5 VPP VO = 14 VPP VO = 4 VPP VO = 8 VPP 0.0010 VO = 12 VPP 0.0001 10 100 1k 10 k 200 k f − Frequency − Hz Figure 52. 0.1000 VS = 3.3 V VS = 5 V VS = ±5 V VS = 3 V VS = 2.7 V 0.0100 0.0010 Amplifier Noise Limit Line f = 1 kHz, Bandwidth = 22 kHz, Gain = 2, RF = 2 kΩ, RL = 1 kΩ , to VS/2 0.0001 0.1 VS = 15 V 1 10 VO − Output Voltage − VPP Figure 53. 20 THD+N −Total Harmonic Distortion + Noise − dBc Figure 51. THD+N −Total Harmonic Distortion + Noise − dBc Figure 50. THD+N −Total Harmonic Distortion + Noise − dBc Figure 49. 0.1000 VS = 5 V VS = ±5 V VS = 15 V VS = 3.3 V VS = 3 V VS = 2.7 V 0.0100 0.0010 f = 10 kHz, Bandwidth = 80 kHz, Gain = 2, RF = 2 kΩ, RL = 1 kΩ , to VS/2 Amplifier Noise Limit Line 0.0001 0.1 1 www.BDTIC.com/TI Product Folder Link(s): THS4281 20 Figure 54. Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated 10 VO − Output Voltage − VPP 15 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com TYPICAL CHARACTERISTICS (continued) (VS = 5 V) DIFFERENTIAL GAIN vs NUMBER OF LOADS 0.8 VS = ±5 V VS = 15 V 0.7 VS = 5 V VS = 3.3 V VS = 2.7 V 0.010 0.1 0.5 0.3 1 10 VO − Output Voltage − VPP 1 20 2 1.6 NTSC 1.4 1.2 1 0.8 0.6 Gain = 2 Rf = 2.5 kΩ VS = 5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.4 0.2 0 0 3 1 2 Number of Loads − 150 Ω Number of Loads − 150 Ω Figure 55. Figure 56. Figure 57. (VS = ±5 V) DIFFERENTIAL GAIN vs NUMBER OF LOADS (VS = ±5 V) DIFFERENTIAL PHASE vs NUMBER OF LOADS INPUT OFFSET VOLTAGE vs TEMPERATURE PAL ° 1.2 1 0.8 NTSC 0.6 Gain = 2 RF= 2.5 kΩ VS = ±5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.4 0.2 1 2 1.6 800 1.4 700 PAL 1.2 Differential Phase − Differential Gain − % Gain = 2 RF= 2.5 kΩ VS = 5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.2 Amplifier Noise Limit Line 1.4 1 NTSC 0.8 0.6 Gain = 2 Rf = 2.5 kΩ VS = ±5 V 40 IRE − NTSC and Pal Worst Case ±100 IRE Ramp 0.4 0.2 1 VICR = VS/2 600 VS = 15 V 500 400 VS = ±5 V VS = 5 V 300 200 VS = 3 V 100 0 2 Number of Loads − 150 Ω −200 −40−30−20−10 0 10 20 30 40 50 60 70 80 90 3 TC − Case Temperature − °C Figure 58. Figure 59. Figure 60. (VS = 5 V) INPUT BIAS AND OFFSET CURRENT vs TEMPERATURE (VS = 15 V) INPUT BIAS AND OFFSET CURRENT vs TEMPERATURE SMALL-SIGNAL TRANSIENT RESPONSE 510 40 520 36 510 24 IIB− 20 460 IIB+ 450 16 12 440 8 430 4 0 420 −40 −30−20−10 0 10 20 30 40 50 60 70 80 90 TC − Case Temperature − °C Figure 61. 490 IOS 28 IIB− 480 470 24 20 IIB+ 16 460 12 450 8 440 4 0 430 −40 −30−20 −10 0 10 20 30 40 50 60 70 80 90 TC − Case Temperature − °C Figure 62. VO − Output Voltage − mV 470 28 500 Output 50 32 I OS − Input Offset Current − n A 480 IOS I IB − Input Bias Current − n A 32 490 60 36 VS =15 V I OS − Input Offset Current − n A VS = 5 V 500 40 30 20 Input 10 0 −10 Gain = 2 RL = 1 kΩ RF = 2.5 kΩ VS = ± 7.5 V −20 −30 −40 −50 −60 0 100 200 300 400 500 600 700 t − Time − ns Figure 63. www.BDTIC.com/TI Submit Documentation Feedback 3 −100 0 3 Number of Loads − 150 Ω I IB − Input Bias Current − n A NTSC 0.4 1.6 16 ° 0.1 0.001 PAL 0.6 Differential Gain − % VS = 3 V f = 100 kHz, Bandwidth = 600 kHz, Gain = 2, RF = 2 kΩ, RL = 1 kΩ , to VS/2 2 1.8 PAL Differential Phase − 0.100 0 (VS = 5 V) DIFFERENTIAL PHASE vs NUMBER OF LOADS VOS− Input Offset Voltage − µ V THD+N −Total Harmonic Distortion + Noise − dBc (f = 100 kHz) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 TYPICAL CHARACTERISTICS (continued) (VS = 5 V) OVERDRIVE RECOVERY TIME 6 1 Input 0 −0.5 Gain = 2 RL = 1 kΩ RF = 2.5 kΩ VS = ± 5 V −1 −1.5 −2 VO − Output Voltage − V VO − Output Voltage − mV 2 1.5 0.5 4 3.25 2.25 Output 1 1.75 0 −1 0 3.75 2.75 2 0 0.5 1 Gain = 2 RL = 1 kΩ RF = 2.5 kΩ VS = ± 5 V 1.5 4 3 2 1 2 1 0 0 −1 −2 −1 Output −3 −2 −4 1.25 Input −5 2.5 2 3 3.5 0.75 −6 t − Time − µs 100 200 300 400 500 600 700 800 3 6 5 3 −2.5 −3 4.25 Gain = 2 RL = 1 kΩ RF = 2.5 kΩ VS = 5 V 5 VO − Output Voltage − V Output VI − Input Voltage − V 3 2.5 (VS = ±5 V) OVERDRIVE RECOVERY TIME VI − Input Voltage − V LARGE-SIGNAL TRANSIENT RESPONSE Input 0 0.5 1 1.5 2 2.5 3 −3 3.5 t − Time − µs t − Time − ns Figure 64. Figure 65. Figure 66. OVERDRIVE RESPONSE OUTPUT VOLTAGE vs TIME 2 V O − Output Voltage − V 6 VS = ±2.5 V Gain = 2, RL = 1 kΩ, RF = 2 kΩ VO 4 1 2 0 VI 0 −1 −2 −2 −4 −3 0 20 40 60 80 V I − Input Voltage − V 3 −6 100 t − Time − ms Figure 67. www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 17 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com APPLICATION INFORMATION HIGH-SPEED OPERATIONAL AMPLIFIERS +VS The THS4281 is a unity gain stable, rail-to-rail input and output, voltage-feedback operational amplifier designed to operate from a single 2.7-V to 16.5-V power supply. + 0.1 µF 6.8 µF 50-Ω Source + VI Applications Section Contents • • • • • • • • • • • 49.9 Ω Wideband, Noninverting Operation Wideband, Inverting Gain Operation Video Drive Circuits Single-Supply Operation Power-Supply Decoupling Techniques Recommendations Active Filtering with the THS4281 Driving Capacitive Loads Board Layout Thermal Analysis Additional Reference Material Mechanical Package Drawings VO _ Rf 2.49 kΩ To Load 2.49 kΩ Rg 0.1 µF 6.8 µF + and −VS Figure 68. Wideband, Noninverting Gain Configuration 24 Signal Gain − dB Voltage feedback amplifiers can use a wide range of resistors values to set their gain with minimal impact on frequency response. Larger-valued resistors decrease loading of the feedback network on the output of the amplifier, but may cause peaking and instability. For a gain of +2, feedback resistor values between 1 kΩ and 4 kΩ are recommended for most applications. However, as the gain increases, the use of even higher feedback resistors can be used to conserve power. This is due to the inherent nature of amplifiers becoming more stable as the gain increases, at the expense of bandwidth. Figure 69 and Figure 70 show the THS4281 using feedback resistors of 10 kΩ and 100 kΩ. Be cautioned that using such high values with high-speed amplifiers is not typically recommended, but under certain conditions, such as high gain and good high-speed printed circuit board (PCB) layout practices, such resistances can be used. RF = 1.65 kΩ and 10 kΩ 16 12 8 VS = 3 V Gain = 10, RL = 1 kΩ, VO = 0.1 VPP 4 0 0.1 1 10 100 f − Frequency − MHz Figure 69. Signal Gain vs Frequency, VS = 3 V 24 RF = 100 kΩ 20 Signal Gain − dB Figure 68 shows the noninverting gain configuration of 2 V/V used to demonstrate the typical performance curves. RF = 100 kΩ 20 WIDEBAND, NONINVERTING OPERATION 16 RF = 2.5 kΩ and 10 kΩ 12 8 4 0 0.1 VS = ±5 V Gain = 10, RL = 1 kΩ, VO = 0.1 VPP 1 10 100 f − Frequency − MHz Figure 70. Signal Gain vs Frequency, VS = ±5 V 18 www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 WIDEBAND, INVERTING OPERATION Figure 71 shows a typical inverting configuration where the input and output impedances and noise gain from Figure 68 are retained with an inverting circuit gain of –1 V/V. +VS + 0.1 µF 6.8 µF Another consideration in inverting amplifier design is setting the bias current cancellation resistor (RT) on the noninverting input. If the resistance is set equal to the total dc resistance presented to the device at the inverting terminal, the output dc error (due to the input bias currents) is reduced to the input offset current multiplied by RT. In Figure 71, the dc source impedance presented at the inverting terminal is 2.49 kΩ || (2.49 kΩ + 25.3 Ω) ≈ 1.24 kΩ. To reduce the additional high-frequency noise introduced by the resistor at the noninverting input, RT is bypassed with a 0.1-μF capacitor to ground (CT). + RT 1.24 kΩ CT 0.1 µF VO _ To Load 50-Ω Source Rg VI Rf 2.49 kΩ RM 51.1 Ω 2.49 kΩ 0.1 µF 6.8 µF + −VS Figure 71. Wideband, Inverting Gain Configuration SINGLE-SUPPLY OPERATION The THS4281 is designed to operate from a single 2.7-V to 16.5-V power supply. When operating from a single power supply, care must be taken to ensure the input signal and amplifier are biased appropriately to allow for the maximum output voltage swing and not violate VICR. The circuits shown in Figure 72 shows inverting and noninverting amplifiers configured for single-supply operation. +VS 50-Ω Source + In the inverting configuration, some key design considerations must be noted. One is that the gain resistor (Rg) becomes part of the signal channel input impedance. If the input impedance matching is desired (which is beneficial whenever the signal is coupled through a cable, twisted pair, long PCB trace, or other transmission line conductors), Rg may be set equal to the required termination value and Rf adjusted to give the desired gain. However, care must be taken when dealing with low inverting gains, as the resulting feedback resistor value can present a significant load to the amplifier output. For example, an inverting gain of 2, setting Rg to 49.9 Ω for input matching, eliminates the need for RM but requires a 100-Ω feedback resistor. The 100-Ω feedback resistor, in parallel with the external load, causes excessive loading on the amplifier output. To eliminate this excessive loading, it is preferable to increase both Rg and Rf values, as shown in Figure 71, and then achieve the input matching impedance with a third resistor (RM) to ground. The total input impedance is the parallel combination of Rg and RM. VI 49.9 Ω RT VO _ To Load +VS Rf 2 Rg 2 kΩ 2 kΩ Power Supply Bypassing Not Shown For Simplicity +VS 2 Rf VS 2 kΩ 50-Ω Source Rg VI RT 51.1 Ω _ 2 kΩ RT + VO To Load +VS +VS 2 2 CT Figure 72. DC-Coupled Single Supply Operation www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 19 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com APPLICATION CIRCUITS Active Filtering with the THS4281 The two most common low-pass filter circuits used are the Sallen-Key filter and the Multiple Feedback (MFB) – aka Rauch filter. FilterPro was used to determine a 2-pole Butterworth response filter with a corner (–3-dB) frequency of 100 kHz, which is shown in Figure 73 and Figure 74. One of the advantages of the MFB filter, a much better high-frequency rejection, is clearly shown in the response shown in Figure 75. This is due to the inherent R-C filter to ground being the first elements in the design of the MFB filter. The Sallen-Key design also has an R-C filter, but the capacitor connects directly to the output. At very high frequencies, where the amplifier's access loop gain is decreasing, the ability of the amplifier to reject high frequencies is severely reduced and allows the high-frequency signals to pass through the system. One other advantage of the MFB filter is the reduced sensitivity in component variation. This is important when using real-world components where capacitors can easily have ±10% variations. 2.05 kW 270 pF 1.02 kW 5V 2.1 kW _ VI VO + 2.2 nF RL 1 kW −5V Figure 74. Second-Order MFB 100-kHz Butterworth Filter, Gain = 2 V/V 10 Sallen-Key Response 0 −10 Signal Gain − dB High-performance active filtering with the THS4281 is achievable due to the amplifier's good slew rate, wide bandwidth, and voltage-feedback architecture. Several options are available for high-pass, low-pass, bandpass, and bandstop filters of varying orders. Filters can be quite complex and time consuming to design. Several books and application reports are available to help design active filters. But, to help simplify the process and minimize the chance of miscalculations, Texas Instruments has developed a filter design program called FilterPro™. FilterPro is available for download at no cost from TI's web site (www.ti.com). −20 −30 −40 −50 MFB Response −60 VS = 3 V, 5 V, ±5 V, 15 V, VO = 100 mVPP −70 −80 1k 10k 100k 1M 10M 100M f − Frequency − Hz Figure 75. Second-Order 100-kHz Active Filter Response Driving Capacitive Loads 2 kW 2 kW 5V _ VI 649 W 2.61 kW 1.5 nF 1 nF VO + −5V RL 1 kW Figure 73. Second-Order Sallen-Key 100-kHz Butterworth Filter, Gain = 2 V/V 20 One of the most demanding, and yet common, load conditions for an op amp is capacitive loading. Often, the capacitive load is the input of an A/D converter, including additional external capacitance, which may be recommended to improve A/D linearity. A high-speed, high open-loop gain amplifier like the THS4281 can be susceptible to instability and peaking when a capacitive load is placed directly on the output. When the amplifier open-loop output resistance is considered, this capacitive load introduces an additional pole in the feedback path that decreases the phase margin. When the primary considerations are frequency response flatness, pulse response fidelity, or distortion, a simple and effective solution is to isolate the capacitive load from the feedback loop by inserting a small series isolation resistor (for example, R(ISO) = 100 Ω for CLOAD = 10 pF to R(ISO) = 10 Ω for CLOAD = 1000 pF) between the amplifier output and the capacitive load. www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 Power-Supply Decoupling Techniques and Recommendations Power-supply decoupling is a critical aspect of any high-performance amplifier design. Careful decoupling provides higher quality ac performance. The following guidelines ensure the highest level of performance. 1. Place decoupling capacitors as close to the power-supply inputs as possible, with the goal of minimizing the inductance. 2. Placement priority should put the smallest valued capacitors closest to the device. 3. Use of solid power and ground planes is recommended to reduce the inductance along power-supply return current paths (with the exception of the areas underneath the input and output pins as noted below). 4. A bulk decoupling capacitor is recommended (6.8 μF to 22 μF) within 1 inch, and a ceramic (0.1 μF) within 0.1 inch of the power input pins. NOTE The bulk capacitor may be shared by other op amps. BOARD LAYOUT Achieving optimum performance with a high-frequency amplifier like the THS4281 requires careful attention to board layout parasitics and external component types. See the EVM layout figures (Figure 78 to Figure 81) in the Design Tools section. Recommendations that optimize performance include: 1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability and on the noninverting input, it can react with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. 2. Minimize the distance (< 0.1 inch) from the power-supply pins to high-frequency, 0.1-μF decoupling capacitors. Avoid narrow power and ground traces to minimize inductance. The power-supply connections should always be decoupled as described above. 3. Careful selection and placement of external components preserves the high-frequency performance of the THS4281. Resistors should be a low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal-film, axial-lead resistors can also provide good high-frequency performance. Again, keep the leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-frequency application. Because the output pin and inverting input pin are the most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to the output pin. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Excessively high resistor values can create significant phase lag that can degrade performance. Keep resistor values as low as possible, consistent with load-driving considerations. It is suggested that a good starting point for design is to set the Rf to 2 kΩ for low-gain, noninverting applications. Doing this automatically keeps the resistor noise terms reasonable and minimizes the effect of parasitic capacitance. www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 21 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com space space 22 THERMAL ANALYSIS The THS4281 does not incorporate automatic thermal shutoff protection, so the designer must take care to ensure that the design does not violate the absolute maximum junction temperature of the device. Failure may result if the absolute maximum junction temperature of +150° C is exceeded. For long-term dependability, the junction temperature should not exceed +125°C. The thermal characteristics of the device are dictated by the package and the PCB. Maximum power dissipation for a given package can be calculated using the following formula. P Dmax + Tmax–T A q JA where: PDmax is the maximum power dissipation in the amplifier (W). Tmax is the absolute maximum junction temperature (°C). TA is the ambient temperature (°C). θJA = θJC + θCA θJC is the thermal coefficient from the silicon junctions to the case (°C/W). θCA is the thermal coefficient from the case to ambient air (°C/W). 1.8 P D − Maximum Power Dissipation − W 4. Connections to other wideband devices on the board should be made with short direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 mils to 100 mils) should be used, preferably with ground and power planes opened up around them. Low parasitic capacitive loads (< 4 pF) may not need an R(ISO), because the THS4281 is nominally compensated to operate at unity gain (+1 V/V) with a 2-pF capacitive load. Higher capacitive loads without an R(ISO) are allowed as the signal gain increases. If a long trace is required, and the 6-dB signal loss intrinsic to a doubly terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A matching series resistor into the trace from the output of the THS4281 is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and the input impedance of the destination device: this total effective impedance should be set to match the trace impedance. If the 6-dB attenuation of a doubly-terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only. Treat the trace as a capacitive load in this case, and use a series resistor (R(ISO) = 10 Ω to 100 Ω, as noted above) to isolate the capacitive load. If the input impedance of the destination device is low, there is signal attenuation due to the voltage divider formed by R(ISO) into the terminating impedance. A 50-Ω environment is normally not necessary onboard, and in fact a higher impedance environment improves distortion as shown in the distortion versus load plots. 5. Socketing a high-speed part like the THS4281 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create a troublesome parasitic network which can make it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the THS4281 onto the board. 1.6 8-pin SOIC (D) Package 1.4 8-pin MSOP (DGK) Package 1.2 1 0.8 0.6 0.4 0.2 0 −40 5-pin SOT23 (DBV) Package −20 0 20 40 60 80 TA − Free-Air Temperature − °C 100 θJA = 97.5°C/W for 8-Pin SOIC (D) θJA = 180.8°C/W for 8-Pin MSOP (DGK) θJA = 255.4°C/W for 5-Pin SOT−23 (DBV) TJ = 125°C, No Airflow Figure 76. Maximum Power Dissipation vs Ambient Temperature When determining whether or not the device satisfies the maximum power dissipation requirement, it is important to consider not only quiescent power dissipation, but also dynamic power dissipation. Often maximum power dissipation is difficult to quantify because the signal pattern is inconsistent, but an estimate of the RMS value can provide a reasonable analysis. www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 DESIGN TOOLS Evaluation Fixtures and Application Support Information Texas Instruments is committed to providing its customers with the highest quality of applications support. To support this goal, an evaluation board has been developed for the THS4281 operational amplifier. The evaluation board is available and easy to use allowing for straight-forward evaluation of the device. These evaluation board can be obtained by ordering through the Texas Instruments web site, or through your local Texas Instruments Sales Representative. A schematic for the evaluation board is shown in Figure 77 with their default component values. Unpopulated footprints are shown to provide insight into design flexibility. space Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the THS4281 device is available through either the Texas Instruments web site or as one model on a disk from the Texas Instruments Product Information Center (1-800-548-6132). The PIC is also available for design assistance and detailed product information at this number. These models do a good job of predicting small-signal ac and transient performance under a wide variety of operating conditions. They are not intended to model the distortion characteristics of the amplifier, nor do they attempt to distinguish between the package types in their small-signal ac performance. Detailed information about what is and is not modeled is contained in the model file itself. www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 23 THS4281 www.ti.com J7 J5 –vs FB1 C3 0.1 µF C0805 C2 100 pF +Vs –Vs SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 +vs FB2 C4 22 µF R4 2 kΩ R0603_1% + R2 2 kΩ R0603_1% J1 +vs U1 4 SIDEMOUNT_SMA R1 51.1 Ω R0805_1% 6 3 2 1 + C5 22 µF R5 953 Ω R0603_1% SIDEMOUNT_SMA THS4281DBV R6 R0603_1% C1 C1206 TP1 J6 R3 49.9 Ω R0805_1% J4 GND J3 PD J2 C7 100 pF 5 –vs SIDEMOUNT_SMA C6 0.1 µF C0805 Figure 77. THS4281EVM Schematic TOP Layer 2 − GND Figure 78. THS4281EVM Layout (Top Layer and Silkscreen Layer) 24 Figure 79. THS4281EVM Board Layout www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 Layer 3 − GND BOTTOM Figure 80. THS4281EVM Board Layout Figure 81. THS4281EVM Board Layout www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 25 THS4281 SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 www.ti.com BILL OF MATERIALS THS4281DBV EVM ITEM (1) DESCRIPTION SMD SIZE REFERENCE DESIGNATO R PCB QTY. FB1, FB2 2 MANUFACTURER'S PART NUMBER (1) DISTRIBUTOR'S PART NUMBER 1 Bead, Ferrite, 3A, 80 Ω 1206 2 OPEN 1206 C1 1 3 Cap, 22 μF, tanatalum, 25 V, 10% D C4, C5 2 4 Cap, 0.1 μF, ceramic, X7R, 50V 0805 C3, C6 2 (AVX) 08055C104KAT2A (GARRETT) 08055C104KAT2A 5 Cap, 100 pF, ceramic, 5%, 150V AQ12 C2, C7 2 (AVX) AQ12EM101JAJME (TTI) AQ12EM101JAJME 6 OPEN 0603 R6 1 7 Resistor, 2 KΩ, 1/10W, 1% 0603 R2, R4 2 (PHYCOMP) 9C06031A2001FKHFT (GARRETT) 9C06031A2001FKHFT 8 Resistor, 953 Ω, 1/10W, 1% 0603 R5 1 (PHYCOMP) 9C06031A9530FKRFT (GARRETT) 9C06031A9530FKRFT 9 Resistor, 51.1 Ω, 1/8W, 1% 0805 R1 1 (PHYCOMP) 9C08052A51R1FKHFT (GARRETT) 9C08052A51R1FKHFT 10 Resistor, 49.9 Ω, 1/8W, 1% 0805 R3 1 (PHYCOMP) 9C08052A49R9FKHFT (GARRETT) 9C08052A49R9FKHFT 11 Jack, banana receptance, 0.25" diameter hole J5, J6, J7 3 (HH SMITH) 101 (NEWARK) 35F865 12 OPEN J3 1 13 Test point, black 14 Connector, edge, SMA PCB JACK 15 Standoff, 4-40 HEX, 0.625" length 16 Screw, PHILLIPS, 4-40, 0.250" 17 IC, THS4281 18 Board, printed circuit (STEWARD) HI1206N800R-00 (DIGI-KEY) 240-1010-1-ND (AVX) TAJD226K025R (GARRETT) TAJD226K025R TP1 1 (KEYSTONE) 5001 (DIGI-KEY) 5001K-ND J1, J2, J4 3 (JOHNSON) 142-0701-801 (NEWARK) 90F2624 4 (KEYSTONE) 1804 (NEWARK) 89F1934 4 SHR-0440-016-SN 1 (TI) THS4281DBV 1 (TI) EDGE # 6448015 Rev.A U1 The manufacturer's part numbers are used for test purposes only. ADDITIONAL REFERENCE MATERIALS • • • • 26 PowerPAD Made Easy, application brief (SLMA004) PowerPAD Thermally Enhanced Package, technical brief (SLMA002) Active Low-Pass Filter Design, application report (SLOA049) FilterPro MFB and Sallen-Key Low-Pass Filter Design Program, application report (SBFA001) www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 THS4281 www.ti.com SLOS432A – APRIL 2004 – REVISED NOVEMBER 2009 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (April, 2004) to Revision A Page • Updated document format to current standards ................................................................................................................... 1 • Deleted Lead temperature specification from Absolute Maximum Ratings table ................................................................. 2 • Revised Driving Capacitive Loads section .......................................................................................................................... 20 • Changed Board Layout section; revised statements in fourth recommendation about how to make connections to other wideband devices on the board ................................................................................................................................. 22 www.BDTIC.com/TI Submit Documentation Feedback Copyright © 2004–2009, Texas Instruments Incorporated Product Folder Link(s): THS4281 27 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty THS4281D ACTIVE SOIC D 8 THS4281DBVR ACTIVE SOT-23 DBV THS4281DBVRG4 ACTIVE SOT-23 THS4281DBVT ACTIVE THS4281DBVTG4 75 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DBV 5 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM ACTIVE SOT-23 DBV 5 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4281DG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4281DGK ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4281DGKG4 ACTIVE MSOP DGK 8 80 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4281DGKR ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4281DGKRG4 ACTIVE MSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4281DR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM THS4281DRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. www.BDTIC.com/TI Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2009 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. www.BDTIC.com/TI Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ THS4281DBVR SOT-23 3000 180.0 DBV 5 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 9.0 3.15 3.2 1.4 4.0 W Pin1 (mm) Quadrant 8.0 Q3 THS4281DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3 THS4281DGKR MSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 THS4281DR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 www.BDTIC.com/TI Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 25-Jun-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS4281DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0 THS4281DBVT SOT-23 DBV 5 250 182.0 182.0 20.0 THS4281DGKR MSOP DGK 8 2500 358.0 335.0 35.0 THS4281DR SOIC D 8 2500 346.0 346.0 29.0 www.BDTIC.com/TI Pack Materials-Page 2 www.BDTIC.com/TI www.BDTIC.com/TI www.BDTIC.com/TI www.BDTIC.com/TI www.BDTIC.com/TI IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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