Download Dual 2GHz Balanced Mixer with Low Side LO Buffer, ADL5356

Dual 2GHz Balanced Mixer
with Low Side LO Buffer,
IF Amp, and RF Balun
ADL5356
Preliminary Technical Data
FEATURES
RF Frequency 1700MHz to 2200MHz
IF Frequency 50MHZ to 450MHz
Power Conversion Gain of 8.0dB
SSB Noise Figure of 10dB
SSB NF with +10dBm blocker of 18dB
Input IP3 of 26dBm
Input P1dB of 11 dBm
Typical LO Drive of 0 dBm
Single-ended, 50Ω RF and LO Input Ports
High Isolation SPDT LO Input Switch
Single Supply Operation: 3.3 to 5 V
Exposed Paddle 6 x 6 mm, 36 Lead LFCSP Package
36
35
34
33
32
31
30
29
28
1
27
2
26
ADL5356
3
25
4
24
5
23
6
22
APPLICATIONS
7
21
Cellular Base Station Receivers
Main and Diversity Receiver Designs
Radio Link Downconverters
8
20
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19
9
GENERAL DESCRIPTION
The ADL5356 utilizes two highly linear doubly balanced passive
mixer cores along with integrated RF and LO balancing
circuitry to enable single-ended operation. The ADL5356
incorporates two RF baluns allowing for optimal main and
diversity mixer performance over a 1700 to 2200 MHz RF input
frequency range using low-side LO injection. (For a high side
injection version, please contact the factory). The balanced
passive mixer arrangement provides good LO to RF, typically
better than -36dBm, and excellent intermodulation
performance. The balanced mixer cores also provide extremely
high input linearity allowing the device to be used in
demanding cellular applications where in-band blocking signals
may otherwise result in the degradation of dynamic
performance. High linearity IF buffer amps follow the passive
mixer cores, to yield a typical power conversion gain of 8.0dB.
(For a higher IIP3 version of the dual mixer without the IF
amplifiers, please contact the factory).
10
11
12
13
14
15
16
17
18
Figure 1. Functional Block Diagram
externally set using a resistor to minimize DC current
commensurate with the desired level of performance. An
additional 3V logic pin is provided to power down (<100uA)
the circuit when desired.
For low voltage applications, the ADL5356 is capable of
operation at voltages down to 3V with substantially reduced DC
current.
The ADL5356 is fabricated using a BiCMOS high performance
IC process. The device is available in a 6mm x 6mm 36-lead
LFCSP package and operates over a −40°C to +85°C
temperature range. An evaluation board is also available.
The ADL5356 provides two switched LO paths that can be
utilized in TDD applications where it is desirable to rapidly
alternate between two local oscillators. LO current can be
REV.PrA
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
www.analog.com
Tel: 781.329.4700
Fax: 781.326.8703
© 2008 Analog Devices, Inc. All rights reserved.
ADL5356
Preliminary Technical Data
ADL5356—Specifications at VS=5V
Table 1. VS = 5 V, TA = 25°C, fRF = 1900 MHz, fLO = 1703 MHz, LO power = 0 dBm, Zo = 50Ω, unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Unit
RF INPUT INTERFACE
Return Loss
Tunable to >20dB over a limited bandwidth
Input Impedance
dB
50
Ω
1700
RF Frequency Range
OUTPUT INTERFACE
Output Impedance
Differential impedance, f = 200 MHz
2200
1
Externally generated
MHz
VS
5.25
V
-6
0
12
50
+10
dBm
dB
Ω
2100
MHz
Input Impedance
Low Side LO injection
450
4.75
Tunable to >20dB over a limited bandwidth
LO Frequency Range
MHz
Ω
200
40
IF Frequency Range
DC Bias Voltage
LO INTERFACE
LO Power
Return Loss
12
1400
DYNAMIC PERFORMANCE
Power Conversion Gain
Voltage Conversion Gain
Including 4:1 IF port transformer and PCB loss
8.0
dB
ZSOURCE = 50Ω, Differential ZLOAD = 200Ω
Differential
14.5
dB
Including 4:1 IF port transformer and PCB loss
10.0
dB
18
dB
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SSB Noise Figure
SSB Noise Figure Under-Blocking
+10dBm Blocker present +/-10MHz from wanted
RF input, LO source filtered
Input Third Order Intercept
fRF1 = 1899.5 MHz, fRF2 = 1900.5 MHz, fLO = 1703
MHz, each RF tone at -10 dBm
Input Second Order Intercept
fRF1 = 1900 MHz, fRF2 = 1850 MHz, fLO = 1703 MHz,
each RF tone at -10 dBm
Input 1 dB Compression Point
LO to IF Output Leakage
Unfiltered IF Output, Improves substantially with
external filter components.
LO to RF Input Leakage
RF to IF Output Isolation
Unfiltered IF Output, Improves substantially with
external filter components.
RFI1 to RFI2 Channel Isolation
IF/2 Spurious
IF/3 Spurious
26.0
dBm
50
dBm
11
dBm
-30
dBm
-45
dBm
45
dBc
45
-10 dBm Input Power
-65
dBc
-10 dBm Input Power
-75
dBc
POWER INTERFACE
Supply Voltage
Quiescent Current
5
Resistor Programmable
1
Supply voltage must be applied from external circuit through external inductors.
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360
V
mA
Preliminary Technical Data
ADL5356
ADL5356—Specifications at VS=3.3V
Table 2. VS = 3.3 V, TA = 25°C, fRF = 1900 MHz, fLO = 1703 MHz, LO power = 0 dBm, Zo = 50Ω, unless otherwise noted
Parameter
Conditions
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Power Conversion Gain
Including 4:1 IF port transformer and PCB loss
8.7
dB
Voltage Conversion Gain
ZSOURCE = 50Ω, Differential ZLOAD = 200Ω
Differential
15.2
dB
SSB Noise Figure
Including 4:1 IF port transformer and PCB loss
9.0
dB
Input Third Order Intercept
fRF1 = 1899.5 MHz, fRF2 = 1900.5 MHz, fLO = 1703
MHz, each RF tone at -10 dBm
20
dBm
Input Second Order Intercept
fRF1 = 1900 MHz, fRF2 = 1850 MHz, fLO = 1703 MHz,
each RF tone at -10 dBm
50
dBm
7
dBm
Input 1 dB Compression Point
POWER INTERFACE
Supply Voltage
Quiescent Current
3.0
Resistor Programmable
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3.3
265
3.6
V
mA
ADL5356
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage, VPOS
PWDN, LOSW, VGS0, VGS1, VGS2
RF Input Power, DVIN, MNIN
Internal Power Dissipation
θJA (Exposed Paddle Soldered Down)
θJC (At Exposed Paddle)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
5.5 V
3.3 V
TBD
TBD
TBD
TBD
TBD
−40°C to +85°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
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REV. PrA| Page 4 of 10
Preliminary Technical Data
ADL5356
36
35
34
33
32
31
30
29
28
VPOS
MNGM
COMM
MNON
MNOP
MNLE
VPOS
MNLG
NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
ADL5356
TOP VIEW
(Not to Scale)
27
26
25
24
23
22
21
20
19
LOI2
VGS2
VGS1
VGS0
LOSW
PWDN
VPOS
COMM
LOI1
VPOS 10
DVGM 11
COMM 12
DVOP 13
DVON 14
DVLE 15
VPOS 16
DVLG 17
NC 18
MNIN 1
MNCT 2
COMM 3
VPOS 4
COMM 5
VPOS 6
COMM 7
DVCT 8
DVIN 9
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3, 5, 7,
12, 20,
34
4,, 6, 10,
16, 21,
30, 36
8
9
11
13, 14
Mnemonic
MNIN
MNCT
COMM
Function
VPOS
Positive Supply Voltage.
DVCT
DVIN
DVGM
DVOP, DVON
15
17
18, 28
19,
22
23
24, 25,
26
27
29
31
32, 33
DVLE
DVLG
NC
L0I1
PWDN
LOSW
VGS0, VGS1,
VGS2
LOI2
MNLG
MNLE
MNOP, MNON
Center Tap for Diversity Channel Input Balun. Should be bypassed to ground using low inductance capacitor.
RF Input for Diversity Channel. Internally matched to 50Ω. Must be ac-coupled.
Diverstiy Amplifier Bias Setting. Connect 1.2kΩ resistor to ground for typical operation.
Diversity Channel Differential Open-Collector Outputs. DVOP and DVON should be pulled-up to VCC using
external inductors.
Diversity Channel External Inductor. Connect 10nH inductor to ground for typical operation.
Diverstiy Channel LO Buffer Bias Setting. Connect 390Ω resistor to ground for typical operation.
No Connect.
Local Oscillator Input 1. Internally matched to 50Ω. Must be ac-coupled.
Connect to Ground for Normal Operation. Connect pin to 3.3V for disable mode.
Local Oscillator Input Selection Switch. Set LOSW high to select LOI1, and set low to select LOI2.
Gate to Source Control Voltages. For typical operation set VGS2 high and VGS0 and VGS1 to low logic level.
35
MNGM
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RF Input for Main Channel. Internally matched to 50Ω. Must be ac-coupled.
Center Tap for Main Channel Input Balun. Should be bypassed to ground using low inductance capacitor.
Device Common (DC Ground).
Local Oscillator Input 2. Internally matched to 50Ω. Must be ac-coupled.
Main Channel LO Buffer Bias Setting. Connect 390Ω resistor to ground for typical operation.
Main Channel External Inductor. Connect 10nH inductor to ground for typical operation.
Main Channel Differential Open-Collector Outputs. MNOP and MNON should be pulled-up to VCC using
external inductors.
Main Amplifier Bias Setting. Connect 1.2kΩ resistor to ground for typical operation.
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ADL5356
Preliminary Technical Data
TYPICAL PERFORMANCE CHARACTERISTICS–PRELIMINARY DATA
VS = 5 V, TA = 25°C, as measured using typical circuit schematic with low-side LO unless otherwise noted.
15
15
Main Channel
High_Band_Main
High_Band_Div
14
13
13
12
12
SSB Noise Figure (dB)
Gain (dB)
14
11
10
9
8
11
10
9
8
7
7
6
6
5
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
Diversity Channel
5
2500
1500
RF Frequency (MHz)
1600
1700
1800
1900
2000
2100
2200
RF Frequency (MHz)
2300
2400
2500
Figure 6. Single-Sideband NF versus RF Frequency
Figure 3. Conversion Gain versus RF Frequency
25
30
Main Channel
Diversity Channel
Poly. (Main Channel)
Poly. (Diversity Channel)
23
21
Input IP3 (dB)
Single-Sideband NF (dB)
25
19
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20
15
10
17
15
13
11
9
5
High_Band_Main
High_Band_Div
0
1500
7
5
1600
1700
1800
1900
2000
2100
2200
2300
RF Frequency (MHz)
2400
-20
2500
-15
-10
-5
0
5
10
Blocker Level (dBm)
Figure 7. Single-Sideband NF versus Blocker Level at 1950MHz
Figure 4. IIP3 versus RF Frequency
0
20
High_Band_Main
High_Band_Div
18
-10
LO to RF Leakage (dBm)
Input P1dB (dBm)
16
14
12
10
8
6
Main Channel
Diversity Channel
-20
-30
-40
4
-50
2
0
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
-60
1300
RF Frequency (MHz)
1400
1500
1600
1700
1800
1900
2000
2100
LO Frequency (MHz)
Figure 5. IP1dB versus RF Frequency
Figure 8. LO to RF Leakage versus LO Frequency
REV. PrA| Page 6 of 10
2200
2300
Preliminary Technical Data
ADL5356
TYPICAL PERFORMANCE CHARACTERISTICS–PRELIMINARY DATA
VS = 3.3 V, TA = 25°C, as measured using typical circuit schematic with low-side LO unless otherwise noted.
20
9
18
8
16
SSB Noise Figure (dB)
10
Gain (dB)
7
6
5
4
3
14
12
10
8
6
Main Channel
4
2
Diversity Channel
2
1
0
1500
0
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
1600
1700
1800
2500
RF Frequency (MHz)
Figure 9. Conversion Gain versus RF Frequency
Channel to Channel Isolation (dB)
Input IP3 (dBm)
10
5
2500
30
20
Main Channel
10
0
1500
1600
1700
1800
1900
2000
2100
2200
2300
2400
Diversity Channel
1600
1700
1800
2500
1900
2000
2100
2200
2300
2400
2500
2200
2300
RF Frequency (MHz)
Figure 13. Channel to Channel Isolation vs. RF Frequency
0
20
-5
Main Channel
Diversity Channel
-10
LO to RF Leakage (dBm)
Input P1dB (dBm)
2400
40
Figure 10. IIP3 versus RF Frequency
14
12
10
8
6
-20
-25
-30
-35
-40
2
-45
1600
1700
1800
1900
2000
2100
2200
2300
2400
2500
Main Channel
Diversity Channel
-15
4
0
1500
2300
50
RF Frequency (MHz)
16
2200
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15
18
2100
60
Main Channel
Diversity Channel
20
0
1500
2000
Figure 12. Single-Sideband NF versus RF Frequency
30
25
1900
RF Frequency (MHz)
-50
1300
1400
1500
1600
1700
1800
1900
2000
2100
LO Frequency (MHz)
RF Frequency (MHz)
Figure 11. IP1dB versus RF Frequency
Figure 14. LO to RF Leakage versus LO Frequency
REV. PrA | Page 7 of 10
Preliminary Technical Data
ADL5356
EVALUATION BOARD SCHEMATIC
R10
MAIN_OUTN
MAIN_OUTP
C33
C32
T1
C8
C17
L2
C19
L1
C21
VCC
R3
VCC
C25
C22
R1
36
34
35
C18
VCC
L6
33
32
31
30
29
R2
28
C9
C16
MAIN_IN
27
1
LO2
Z2
Z1
R12
2
C3
26
C2
ADL5356
3
24
5
23
6
22
7
21
8
20
9
19
C4
C5
VCC
C6
VCC
R13
R7
R8
R14
25
4
C34
R17
LOSEL
R11
R15
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C7
R16
PWDN
R15
VCC
C26
C15
C11
DIV_IN
Z3
LO1
C14
Z4
10
VCC
11
12
13
15
14
L3
C24
R4
C23
VCC
16
17
18
VCC R5
C13
R6
C10
C1
L5
C20
GND
VCC
L4
C12
C29
T2
DIV_OUTP
DIV_OUTN
C30
C31
Figure 9. Evaluation Board Schematic.
REV. PrA | Page 8 of 10
Preliminary Technical Data
ADL5356
Table 3. Eval Board Configuration
Components
C1, C4, C5, C8, C10, C12,
C13, C15, C18, C21, C22,
C23, C24, C25, C26
Function
Power Supply Decoupling. Nominal supply decoupling consists a
0.01 μF capacitor to ground in parallel with 10pF capacitors to
ground positioned as close to the device as possible.
Z1-Z4, C2, C3, C6, C7, C9,
C22
RF Main and Diversity Input Interface. Main and Diversity input
channels are ac-coupled through C9 and C22. Z1-Z4 provides
additional component placement for external matching/filter
networks. C2, C3, C6, and C7 provide bypassing for the center taps
of the main and diversity on-chip input baluns.
IF Main and Diversity Output Interface. The open collector IF output
interfaces are biased through pull-up choke inductors L1, L2, L4, and
L5, with R3 and R6 available for additional supply bypassing. T1 and
T2 are 4:1 impedance transformers used to provide a single ended IF
output interface, with C27 and C28 providing center-tap bypassing.
C17, C19, C20, C29, C30, C31, C32, and C33 ensure an ac-coupled
output interface. R9 and R10 should be removed for balanced
output operation.
LO Interface. C14 and C16 provide ac-coupling for the LOI1 and LOI2
local oscillator inputs. LOSEL selects the appropriate LO input for
both mixer cores. R15 provides a pull-down to ensure LOI2 is
enabled when the LOSEL jumper is removed. Jumper can be
removed to allow LOSEL interface to be excercised using external
logic generator.
PWDN Interface. When the PWDN 2-pin shunt is inserted the
ADL5356 is powered down. When open R19 pulls the PWDN logic
low and enables the device. Jumper can be removed to allow PWDN
interface to be excercised using external logic generator. It is
permissible to ground the pwrdn pin for nominal operation.
Bias Control. R16 and R17 form a voltage divider to provide a 3V for
logic control, bypassed to ground through C34. R7, R8, R11, R12,
R13, and R14 provide resistor programmability of VGS0, VGS1 and
VGS2. Typically these nodes can be hard-wired for nominal
operation. It is permissible to ground these pins for nominal
operation. R2 and R5 set the bias point for the internal LO buffers. R1
and R4 set the bias point for the internal IF amplifiers. L3 and L6 are
external inductors used to improve isolation and common mode
rejection.
T1, T2, C17, C19, C20, C27,
C28, C29, C30, C31, C32,
C33, L1, L2, L4, L5, R3, R6,
R9, R10
C14, C16, R15, LOSEL
R19, PWDN
R1, R2, R4, R5,L3, L6, R7,
R8, R11, R12, R13, R14,
R16, R17, C34
Default Conditions
C10 = 4.7 μF (size 3216)
C1, C8, C12, C21 = 150pF (size 0402)
C4, C5, C22, C23, C24, C25, C26 = 10pF
(size 0402)
C13, C15, C18 = 0.1 μ (size 0402)
C2, C7 = 10pF (size 0402)
C3, C6 = 0.01 μF (size 0402)
C9, C22 = 22pF (size 0402)
Z1-Z4 = open (size 0402)
C17, C19, C20, C29-C33 = 0.001 μF (size
0402)
C27, C28 = 150pF (size 0402)
T1, T2 = TC4-1T+ (MiniCircuits)
L1, L2, L4, L5 = 330 nH (size 0805)
R3, R6, R9, R10 = 0 Ω (size 0402)
C14, C16 = 10pF (size 0402)
R15 = 10kΩ (size 0402)
LOSEL = 2-pin shunt
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REV. PrA | Page 9 of 10
R19 = 10kΩ (size 0402)
PWDN = 2-pin shunt
R1, R4 = 1.2kΩ (size 0402)
R2, R5 = 390Ω (size 0402)
L3, L6 = 10nH (size 0603)
R7, R13, R14 = open (size 0402)
R8, R11, R12 = 0Ω (size 0402)
R16 = 10kΩ (size 0402)
R17 = 15kΩ (size 0402)
C34 = 1nF (size 0402)
ADL5356
Preliminary Technical Data
OUTLINE DIMENSIONS
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Figure 10. 36-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
6mm × 6 mm Body, Very Thin Quad (CP-36-1))
Dimensions shown in millimeters
ORDERING GUIDE
Models
ADL5356XCPZ-R7
Temperature
Range
−40°C to +85°C
ADL5356XCPZ-WP
−40°C to +85°C
ADL5356-EVALZ
Package Description
36-Lead Lead Frame Chip Scale Package
[LFCSP_VQ]
36-Lead Lead Frame Chip Scale Package
[LFCSP_VQ]
Evaluation Board
REV. PrA| Page 10 of 10
Package
Option
CP-36-1
Branding
TBD
Transport
Media Quantity
TBD, Reel
CP-36-1
TBD
TBD, Waffle Pack
1
PR07883-0-10/08(PrA)