Download Quad Low Noise, Low Cost Variable Gain Amplifier AD8335

Quad Low Noise, Low Cost
Variable Gain Amplifier
AD8335
VIP1
VIN1
VCM2
VCM1
EN12
SP12
HL12
FUNCTIONAL BLOCK DIAGRAM
POP1
61
60
59
58
53
55
52
51
49
PIP1 63
18dB
ATTEN
–48dB TO
0dB
VMD1
PMD1 64
PMD2 1
18dB
INTERPOLATOR
VMD2
GAIN INT
PIP2 2
PON2 4
INTERPOLATOR
VIP2 6
ATTEN
–48dB TO
0dB
VIN2 7
46
VOL1
56
VGN1
50
SL12
GAIN INT
54
VGN2
43
VOL2
42
VOH2
39
VOH3
38
VOL3
27
VGN3
31
SL34
25
VGN4
35
VOL4
34
VOH4
20dB
TO
28dB
AD8335
VIN3 10
ATTEN
–48dB TO
0dB
VIP3 11
20dB
TO
28dB
POP3 12
INTERPOLATOR
PON3 13
GAIN INT
PIP3 15
18dB
VMD3
18dB
VMD4
INTERPOLATOR
PMD3 16
PMD4 17
26
29
30
32
HL34
VIP4
VIN4
28
SP34
23
EN34
22
20dB
TO
28dB
VCM4
21
GAIN INT
VCM3
20
POP4
PIP4 18
ATTEN
–48dB TO
0dB
PON4
Medical imaging (ultrasound, gamma cameras)
Sonar
Test and measurement
Precise, stable wideband gain control
VOH1
POP2 5
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APPLICATIONS
47
20dB
TO
28dB
04976-001
Low noise preamplifier (PrA)
Voltage noise = 1.3 nV/√Hz typical
Current noise = 2.4 pA/√Hz typical
NF = 7 dB (RS = RIN = 50 Ω)
Single-ended input; VIN maximum = 625 mV p-p
Active input match
Input SNR (noise bandwidth = 20 MHz) = 92 dB
VGA
Differential output
VOUT maximum = 5 V p-p, RL = 500 Ω differential
Gain range (8 dB output gain step)
−10 dB to +38 dB—low gain mode
−2 dB to +46 dB—high gain mode
Accurate linear-in-dB gain control
PrA + VGA performance
−3 dB bandwidth of 85 MHz
Excellent overload performance
Supply: 5 V
Power consumption
95 mW/channel (380 mW total)
65 mW/channel (PrA off; 260 mW total)
Power-down
PON1
FEATURES
Figure 1.
GENERAL DESCRIPTION
The AD8335 is a quad variable gain amplifier (VGA) with low
noise preamplifier intended for cost and power sensitive applications. Each channel features a gain range of 48 dB, fully
differential signal paths, active input preamplifier matching,
and user-selectable maximum gains of 46 dB and 38 dB.
Individual gain controls are provided for each channel.
The preamplifier (PrA) has a single-ended to differential gain
of ×8 (18.06 dB) and accepts input signals ≤625 mV p-p. PrA
noise is 1.2 nV/√Hz and the combined input referred voltage
noise of the PrA and VGA is 1.3 nV/√Hz at maximum gain.
Assuming a 20 MHz noise bandwidth (NBW), the Nyquist
frequency for a 40 MHz ADC, the input SNR is 92 dB. The
HLxx pin optimizes the output SNR for 10-bit and 12-bit
ADCs with 1 V p-p or 2 V p-p full-scale (FS) inputs.
Channel 1 and Channel 2 are enabled through the EN12 pin
and Channel 3 and Channel 4 are enabled through the EN34
pin. For VGA only applications, the PrAs can be powered down,
significantly reducing power consumption.
The AD8335 is available in a 64-lead lead frame chip scale
package (9 mm × 9 mm) for the industrial temperature range
of −40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2008 Analog Devices, Inc. All rights reserved.
AD8335
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications Information .............................................................. 20 Applications ....................................................................................... 1 Ultrasound .................................................................................. 20 Functional Block Diagram .............................................................. 1 Basic Connections ...................................................................... 21 General Description ......................................................................... 1 Preamp Connections ................................................................. 21 Revision History ............................................................................... 2 Input Overdrive .......................................................................... 22 Specifications..................................................................................... 3 Logic Inputs................................................................................. 22 Absolute Maximum Ratings............................................................ 5 Common-Mode Pins ................................................................. 22 ESD Caution .................................................................................. 5 Driving ADCs ............................................................................. 22 Pin Configuration and Function Descriptions ............................. 6 Evaluation Board ............................................................................ 23 Typical Performance Characteristics ............................................. 7 Measurement Setup.................................................................... 23 Test Circuits ..................................................................................... 15 Board Layout ............................................................................... 23 Theory of Operation ...................................................................... 16 Bill of Materials ........................................................................... 27 Enable Summary ........................................................................ 16 Outline Dimensions ....................................................................... 28 Preamp ......................................................................................... 17 Ordering Guide .......................................................................... 28 VGA.............................................................................................. 18 REVISION HISTORY
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8/08—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Table 1, Scale Factor Parameter.................................. 4
Changes to Theory of Operation Section .................................... 16
Changes to Figure 54 ...................................................................... 16
Changes to Equation 4 ................................................................... 18
Changes to Figure 58 ...................................................................... 21
Added Evaluation Board Section ................................................. 23
Added Figure 60 to Figure 68........................................................ 23
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
9/04—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8335
SPECIFICATIONS
VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, low gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal
voltage specified differential, per channel performance, dBm (50 Ω), unless otherwise noted.
Table 1.
Parameter
PrA CHARACTERISTICS
Gain
Input Voltage Range
Input Resistance
Input Capacitance
−3 dB Small Signal Bandwidth
Input Voltage Noise
Input Current Noise
Noise Figure
Active Termination Match
Unterminated
PrA + VGA CHARACTERISTICS
−3 dB Small Signal Bandwidth
Conditions
Min
Typ
Max
Single-ended input to differential output
Single-ended input to single-ended output
PrA output limited to 5 V p-p differential
RFB = 249 Ω
RFB = 374 Ω
RFB = 499 Ω
RFB = ∞, low frequency value into PIPx
PIPx (Pin 2, Pin 15, Pin 18, Pin 63)
With RFB = 249 Ω
RS = 0 Ω, RFB = ∞
18
12
625
50
75
100
14.7
1.5
110
1.15
2.4
dB
dB
mV p-p
Ω
Ω
Ω
kΩ
pF
MHz
nV/√Hz
pA/√Hz
RS = RIN = 50 Ω, RFB = 249 Ω
RS = 50 Ω, RFB = ∞
7
4.4
dB
dB
Unterminated: RS = 50 Ω, RFB = ∞
Matched: RS = RIN = 50 Ω
Low gain, VGN = 3 V, VOUT = 2 V p-p
High gain, VGN = 3 V, VOUT = 2 V p-p
VGNx pins = 3 V, RS = 0 Ω, RFB = ∞
VGNx pins = 3 V, f = 1 MHz to 10 MHz
RS = RIN = 50 Ω
RS = RIN = 100 Ω
RS = 50 Ω, RFB = ∞
RS = 500 Ω, RFB = ∞
Low gain; VGN < 2 V
High gain; VGN < 2 V
Differential, RL ≥ 500 Ω
f < 1 MHz, VOHx, VOLx pins
Set to midsupply for PrA and VGA
70
85
250
350
1.3
MHz
MHz
V/μs
V/μs
nV/√Hz
7
4.5
5.0
1.3
33
80
5
1.2
VS/2
dB
dB
dB
dB
nV/√Hz
nV/√Hz
V p-p
Ω
V
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Slew Rate
Input Voltage Noise
Noise Figure
Active Termination Match
Unterminated
Output Referred Noise
Peak Output Voltage
Output Resistance
Common-Mode Level
Output Offset Voltage
Differential
Common-Mode
Harmonic Distortion
HD2
HD3
HD2
HD3
Harmonic Distortion
HD2
HD3
HD2
HD3
Output 1 dB Compression (OP1dB)
Unit
Between VOHx pins and VOLx pins, full gain range
Between VOHx pins and VCMx pins, and between
VOLx pins and VCMx pins
VOUT = 1 V p-p, low gain, VGN = 2 V
f = 1 MHz
f = 1 MHz
f = 10 MHz
f = 10 MHz
VOUT = 1 V p-p, high gain, VGN = 2 V
f = 1 MHz
f = 1 MHz
f = 10 MHz
f = 10 MHz
VGN = 3 V
VGN = 3 V
Rev. A | Page 3 of 28
−25
−20
+5
+0
+35
+20
mV
mV
−69
−57
−57
−55
dBc
dBc
dBc
dBc
−58
−70
−55
−55
18
8
dBc
dBc
dBc
dBc
dBm
dBV peak
AD8335
Parameter
Two-Tone IMD3 Distortion
Output IP3 (OIP3)
Channel-to-Channel Crosstalk
Overload Recovery
Group Delay Variation
GAIN CONTROL INTERFACE
Normal Operating Range
Maximum Range
Gain Range
Scale Factor
Bias Current
Response Bandwidth
Response Time
GAIN ACCURACY
Absolute Gain Error
Gain Law Conformance Over Temperature
Intercept
Conditions
VOUT = 1 V p-p, VGN = 3 V
f1 = 1 MHz, f2 = 1.05 MHz
f1 = 10 MHz, f2 = 10.05 MHz
VOUT = 1 V p-p, VGN = 3 V
f = 1 MHz
f = 10 MHz
VOUT = 1 V p-p, f = 1 to 10 MHz
PrA or VGA
Full gain range, f = 1 MHz to 10 MHz
VGNx pins
No gain foldover
Low gain mode; (HLxx pins = 0 V)
High gain mode; (HLxx pins = VS)
Nominal (Pin SL12 and Pin SL34 = 2.5 V)
48 dB gain change
VGNx pins
0 ≤ VGN ≤ 0.4 V
0.4 ≤ VGN ≤ 2.6 V, 1σ
2.6 ≤ VGN ≤ 3 V
0.4 ≤ VGN ≤ 2.6 V; −40°C < TA < +85°C
Low gain mode; PrA matched to 50 Ω
High gain mode; PrA matched to 50 Ω
0.4 ≤ VGN ≤ 2.6 V
HLxx, SPxx, and ENxx pins
Min
Typ
Max
−69
−65
dBc
dBc
33
31
−80
10
3.0
dBm
dBm
dBc
ns
ns
0
0
3
VS
−10 to +38
−2 to +46
19.1
20.1
21.1
−0.3
5
350
1.25
−1.25
−7.5
±0.2
7.5
+1.25
−1.25
±0.75
−16.1
−8.1
0.15
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Channel-to-Channel Matching
LOGIC LEVEL—HIGH/LOW, SHUTDOWN
PREAMP, and ENABLE INTERFACES
Logic High
Logic Low
BIAS CURRENT—HIGH/LOW, ENABLE
Logic High
Logic Low
INPUT RESISTANCE—HIGH/LOW, ENABLE
BIAS CURRENT— SHUTDOWN PREAMP
Logic High
Logic Low
INPUT RESISTANCE—SHUTDOWN PREAMP
High/Low Response Time
Enable Response Time
POWER SUPPLY
Supply Voltage
Quiescent Current
Over Temperature
Quiescent Power
Disable Current
PSRR
Unit
2.75
0
5
1
V
V
dB
dB
dB/V
μA
MHz
ns
dB
dB
dB
dB
dB
dB
dB
V
V
80
−12
50
μA
μA
kΩ
20
0
500
0.6
100
μA
μA
kΩ
μs
μs
VPPx and VPVx pins
4.5
Each channel—PrA and VGA enabled
Each channel—PrA disabled, VGA enabled
All channels enabled
−40°C < TA < +85°C
Each channel—PrA and VGA enabled
Each channel—PrA disabled, VGA enabled
All channels disabled
VGN = 0 V, all bypass capacitors removed, 1 MHz
Rev. A | Page 4 of 28
5
19
13
76
16
5.5
22.8
95
65
0.8
−60
V
mA
mA
mA
mA
mW
mW
mA
dB
AD8335
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
Voltage
Supply VS
Preamp Input
VGA Inputs
Enable, Shutdown Preamp, and
High/Low Interfaces
Gain
Power Dissipation (4-Layer JEDEC Board (2s2p))
θJA
θJC
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range (Soldering 60 sec)
Rating
6V
VS
VS
VS
VS
2.46 W
26.4°C/W
6.8°C/W
−40°C to +85°C
−65°C to
+150°C
300°C
ESD CAUTION
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Rev. A | Page 5 of 28
AD8335
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PMD1
PIP1
VPP1
PON1
POP1
VIP1
VIN1
COM1
VGN1
VCM1
VGN2
VCM2
EN12
SP12
SL12
HL12
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIN 1
IDENTIFIER
AD8335
TOP VIEW
(Not to Scale)
GND1
VOH1
VOL1
VPV1
VPV2
VOL2
VOH2
GND2
GND3
VOH3
VOL3
VPV3
VPV4
VOL4
VOH4
GND4
04976-058
PMD4
PIP4
VPP4
PON4
POP4
VIP4
VIN4
COM4
VGN4
VCM4
VGN3
VCM3
EN34
SP34
SL34
HL34
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PMD2
PIP2
VPP2
PON2
POP2
VIP2
VIN2
COM2
COM3
VIN3
VIP3
POP3
PON3
VPP3
PIP3
PMD3
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Mnemonic
PMD2
PIP2
VPP2
PON2
POP2
VIP2
VIN2
COM2
COM3
VIN3
VIP3
POP3
PON3
VPP3
PIP3
PMD3
PMD4
PIP4
VPP4
PON4
POP4
VIP4
VIN4
COM4
VGN4
VCM4
VGN3
VCM3
EN34
SP34
SL34
HL34
Description
Preamp Input Common—CH2
Preamp Input—CH2
Positive Supply Preamp—CH2
Preamp Output Negative—CH2
Preamp Output Positive—CH2
VGA Input Positive—CH2
VGA Input Negative—CH2
Ground Preamp—CH2
Ground Preamp—CH3
VGA Input Negative—CH3
VGA Input Positive—CH3
Preamp Output Positive—CH3
Preamp Output Negative—CH3
Positive Supply Preamp—CH3
Preamp Input—CH3
Preamp Input Common—CH3
Preamp Input Common—CH4
Preamp Input—CH4
Positive Supply Preamp—CH4
Preamp Output Negative—CH4
Preamp Output Positive—CH4
VGA Input Positive—CH4
VGA Input Negative—CH4
Ground Preamp—CH4
Gain Control—CH4
Common-Mode Decoupling Pin—CH4
Gain Control—CH3
Common-Mode Decoupling Pin—CH3
Enable—CH3 and CH4
Shutdown—Preamp 3 and Preamp 4
Slope Decoupling Pin—CH3 and CH4
High/Low Pin—CH3 and CH4
Pin No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Mnemonic
GND4
VOH4
VOL4
VPV4
VPV3
VOL3
VOH3
GND3
GND2
VOH2
VOL2
VPV2
VPV1
VOL1
VOH1
GND1
HL12
SL12
SP12
EN12
VCM2
VGN2
VCM1
VGN1
COM1
VIN1
VIP1
POP1
PON1
VPP1
PIP1
PMD1
Description
Ground VGA—CH4
VGA Output Positive—CH4
VGA Output Negative—CH4
Positive Supply VGA—CH4
Positive Supply VGA—CH3
VGA Output Negative—CH3
VGA Output Positive—CH3
Ground VGA—CH3
Ground VGA—CH2
VGA Output Positive—CH2
VGA Output Negative—CH2
Positive Supply VGA—CH2
Positive Supply VGA—CH1
VGA Output Negative—CH1
VGA Output Positive—CH1
Ground VGA—CH1
High/Low Pin—CH1 and CH2
Slope Decoupling Pin—CH1 and CH2
Shutdown—Preamp 1 and Preamp 2
Enable—CH1 and CH2
Common-Mode Decoupling Pin—CH2
Gain Control—CH2
Common-Mode Decoupling Pin—CH1
Gain Control—CH1
Ground Preamp—CH1
VGA Input Negative—CH1
VGA Input Positive—CH1
Preamp Output Positive—CH1
Preamp Output Negative—CH1
Positive Supply Preamp—CH1
Preamp Input—CH1
Preamp Input Common—CH1
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Rev. A | Page 6 of 28
AD8335
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, RL = 500 Ω, f = 5 MHz, CL = 10 pF, low gain range (−10 dB to +38 dB), RFB = 249 Ω (PrA RIN = 50 Ω) and signal
voltage specified differential, per channel performance, unless otherwise noted.
20
50
+85°C
18
40
16
HIGH GAIN
30
14
20
% OF UNITS
GAIN (dB)
420 CHANNELS
(105 UNITS)
VGAIN = 1.5V
LOW GAIN
+25°C
10
–40°C
12
10
8
6
0
4
–10
0.5
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
0
–0.6 –0.5 –0.4 –0.3 –0.2 –0.1
Figure 3. Gain vs. VGAIN at Three Temperatures (See Figure 49)
0.1 0.2 0.3 0.4 0.5 0.6
Figure 6. Gain Error Histogram
25
2.0
20
1.5
15
420 CHANNELS
(105 UNITS)
VGAIN = 1.0V
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10
+85°C, LOW GAIN
+85°C, HIGH GAIN
5
% OF UNITS
0.5
+25°C, LOW GAIN
0
–0.5
+25°C, HIGH GAIN
–40°C, LOW GAIN
–1.0
–40°C, HIGH GAIN
–1.5
0
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.0
25
20
VGAIN = 2.0V
15
CH1 TO CH2
10
CH1 TO CH3
CH1 TO CH4
0
0.5
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
0
04976-003
–2.0
CHANNEL-TO-CHANNEL GAIN MATCH (dB)
Figure 4. Gain Error vs. VGAIN at Three Temperatures (See Figure 49)
04976-006
5
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
GAIN ERROR (dB)
0
GAIN ERROR (dB)
04976-005
0
04976-002
–20
2
Figure 7. Gain Match Histogram for VGAIN = 1 V and 2 V
6.0
45
40
4.0
420 CHANNELS
(105 UNITS)
0.5V < VGAIN < 2.5V
2.0
5MHz
30
% TOTAL
20MHz
0
25
20
1MHz
–2.0
15
10MHz
10
–4.0
–6.0
0
0.5
1.0
1.5
VGAIN (V)
2.0
2.5
3.0
0
19.9
20.0
20.1
20.2
GAIN SCALING FACTOR
Figure 5. Gain Error vs. VGAIN at Various Frequencies (See Figure 49)
20.3
20.4
04976-007
5
04976-004
GAIN ERROR (dB)
35
Figure 8. Gain Scaling Factor Histogram for 0.5 V < VGAIN < 2.5 V
Rev. A | Page 7 of 28
AD8335
25
20
30
420 CHANNELS
(105 UNITS)
0.5V < VGAIN < 2.5V
25
RFB = ∞
15
15
GAIN (dB)
% TOTAL
20
10
RFB = 249Ω
RS = 50Ω
VIN = 10mV p-p
10
5
0
5
Figure 9. Intercept Histogram
1M
10M
FREQUENCY (Hz)
100M
1G
04976-011
–15.5
–15.6
–10
100k
04976-008
INTERCEPT (dB)
–15.7
–15.8
–15.9
–16.0
–16.1
–16.2
–16.3
–16.4
–16.5
–16.6
0
–16.7
–5
Figure 12. Frequency Response for a Terminated and Unterminated
50 Ω Source (See Figure 49)
–10
50
40
VGAIN = 3.0V
30
VGAIN = 2.5V
VOUT = 1V p-p
–20
–30
CROSSTALK (dB)
VGAIN = 1.5V
–20
100k
–60
–80
VGAIN = 0V
–90
1M
10M
100M
1G
FREQUENCY (Hz)
40
VGAIN = 2V
1M
10M
100M
Figure 13. Channel-to-Channel Crosstalk vs. Frequency for
Various Values of VGAIN
80
VGAIN = 3.0V
70
VGAIN = 2.5V
60
GROUP DELAY (ns)
30
GAIN (dB)
VGAIN = 3V
FREQUENCY (Hz)
VGAIN = 2.0V
VGAIN = 1.5V
20
VGAIN = 1.0V
10
VGAIN = 0.5V
0
50
40
30
20
VGAIN = 0V
–10
10
1M
10M
FREQUENCY (Hz)
100M
1G
0
100k
04976-010
–20
100k
VGAIN = 1V
VGAIN = 3V
–100
100k
Figure 10. Frequency Response for Various Values of VGAIN (See Figure 49)
50
VGAIN = 1V
–70
VGAIN = 0.5V
04976-009
–10
VGAIN = 2V
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VGAIN = 1.0V
0
–50
04976-012
10
–40
1M
10M
FREQUENCY (Hz)
Figure 11. Frequency Response vs. Frequency for Various Values of VGAIN,
HLxx = High (See Figure 49)
Rev. A | Page 8 of 28
Figure 14. Group Delay vs. Frequency
100M
04976-013
GAIN (dB)
VGAIN = 2.0V
20
AD8335
25
1k
20
10
INPUT IMPEDANCE (Ω)
OFFSET VOLTAGE (mV)
RFB = 2.5kΩ
+85°C, HIGH
+85°C, LOW
15
5
0
–5
–40°C, LOW
–10
–15
–40°C, HIGH
+25°C, HIGH
+25°C, LOW
RFB = 1kΩ
RFB = 499Ω
100
RFB = 249Ω
RSH = ∞, CSH = 0pF
RSH = 49Ω, CSH = 22pF
0
0.5
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
10
04976-014
–25
1M
25
50j
VIN = 10mV p-p
–10
20
25j
–20
15
100j
–30
10
–40
CROSSTALK (dB)
5
0
STOP
1GHz
–50
17Ω
0Ω
50Ω
150Ω
www.BDTIC.com/ADI
–70
START
100kHz
–80
–15
–20
–90
–25
0
0.5
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
–75j
–25j
–50j
Figure 19. Smith Chart S11 vs. Frequency, 100 kHz to 1 GHz
Figure 16. Absolute Offset vs. VGAIN at VOHx and VOLx Pins
Relative to VCMx Pins
250
100
RS = 0Ω
VIN = 10mV p-p
OUTPUT REFERRED NOISE (nV/ Hz)
VOHx
VOLx
10
1M
10M
FREQUENCY (Hz)
1G
RFB = ∞
200
150
HLxx = HIGH
100
50
0
04976-016
1
0.1
100k
100MHz
–100
04976-018
–10
–60
HLxx = LOW
0
0.5
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
Figure 20. Output Referred Noise vs. VGAIN (See Figure 50)
Figure 17. Output Resistance at VOHx and VOLx Pins vs. Frequency
Rev. A | Page 9 of 28
04976-019
–5
04976-015
OFFSET VOLTAGE (mV)
1G
Figure 18. Preamp Input Resistance vs. Frequency for
Various Values of RFB
Figure 15. Differential Output Offset Voltage vs. VGAIN at Three Temperatures
OUTPUT IMPEDANCE (Ω)
10M
FREQUENCY (Hz)
04976-017
–20
AD8335
1.4
60
f = 10MHz
50
45
VGAIN = 3.0V
RS = 0Ω
RFB = ∞
1.0
NOISE FIGURE (dB)
INPUT REFERRED NOISE (nV/ Hz)
55
1.2
0.8
0.6
0.4
40
35
30
25
20
15
10
0.2
10
0
04976-020
1
100
FREQUENCY (MHz)
0
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
Figure 24. Noise Figure vs. VGAIN for RS = RIN = 50 Ω
Figure 21. Short-Circuit Input Referred Noise vs. Frequency at Maximum Gain
(See Figure 50)
–35
1k
f = 10MHz
VOUT = 1V p-p
VGAIN = 1.5V
–40
T = +85°C
100
HLxx = LOW
HD2
HD3
–45
DISTORTION (dBc)
NOISE (nV/ Hz)
0.5
04976-062
5
0
0.1
10
–50
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T = +25°C
–55
HLxx = HIGH
HD2
HD3
–60
1.0
T = –40°C
0
0.5
1.0
1.5
2.0
2.5
–70
200
04976-021
0.1
3.0
VGAIN (V)
600
800
1.0k
1.2k
1.4k
1.6k
1.8k
2.0k
RLOAD (Ω)
Figure 25. Harmonic Distortion vs. RLOAD (See Figure 53)
Figure 22. Input Referred Noise vs. VGAIN at Three Temperatures
(See Figure 50)
–20
10
f = 1MHz, VGAIN = 3V
f = 10MHz
VOUT = 1V p-p
DISTORTION (dBc)
–30
1.0
RS THERMAL NOISE
ALONE
HLxx = LOW
HD3
–40
HLxx = HIGH,
HD3
–50
–60
HLxx = HIGH,
HD2
HLxx = LOW,
HD2
0.1
1
10
100
SOURCE RESISTANCE (Ω)
1k
–80
0
10
20
30
40
CLOAD (pF)
Figure 26. Harmonic Distortion vs. CLOAD (See Figure 53)
Figure 23. Input Referred Noise vs. RS
Rev. A | Page 10 of 28
50
04976-200
–70
04976-022
INPUT NOISE (nV/ Hz)
400
04976-025
–65
AD8335
–20
–20
HIGH GAIN
VOUT = 1V p-p
–30
–40
–40
DISTORTION (dBc)
–30
–50
f = 10MHz
f = 5MHz
–70
–80
0.5
1.5
2.0
f = 10MHz
–60
f = 5MHz
–70
f = 1MHz
1.0
–50
f = 1MHz
2.5
3.0
VGAIN (V)
–80
0.5
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
Figure 27. HD2 vs. VGAIN at Three Frequencies, Low Gain (See Figure 53)
04976-030
–60
04976-026
DISTORTION (dBc)
LOW GAIN
VOUT = 1V p-p
Figure 30. HD3 vs. VGAIN at Three Frequencies, High Gain (See Figure 53)
–35
–20
f = 1MHz
LOW GAIN
VOUT = 1V p-p
–40
–30
DISTORTION (dBc)
–40
–50
f = 10MHz
–60
–55
–60
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f = 5MHz
–70
–50
2V p-p
–65
–70
1V p-p
–75
0.5V p-p
f = 1MHz
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
–80
0.5
04976-027
–80
0.5
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
Figure 28. HD3 vs. VGAIN at Three Frequencies, Low Gain (See Figure 53)
04976-031
DISTORTION (dBc)
–45
Figure 31. HD2 vs. VGAIN at Three Output Voltages, Low Gain (See Figure 53)
–20
–20
HIGH GAIN
VOUT = 1V p-p
f = 1MHz
–30
–30
DISTORTION (dBc)
DISTORTION (dBc)
–40
–40
f = 10MHz
–50
–60
2V p-p
–50
1V p-p
–60
0.5V p-p
–70
f = 5MHz
f = 1MHz
–70
1.5
2.0
VGAIN (V)
2.5
3.0
–90
0.5
1.0
1.5
2.0
VGAIN (V)
Figure 29. HD2 vs. VGAIN at Three Frequencies, High Gain (See Figure 53)
2.5
3.0
04976-032
1.0
04976-029
–80
0.5
–80
Figure 32. HD3 vs. VGAIN, at Three Output Voltages, Low Gain (See Figure 53)
Rev. A | Page 11 of 28
AD8335
–35
40
VOUT = 1Vp-p
f = 1MHz
35
–40
–45
5MHz (LOW)
25
IP3 (dBm)
–50
2V p-p
–55
15
1V p-p
–60
10
0.5V p-p
–65
5
0
0.5
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
0
04976-034
–70
20
0
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
Figure 33. HD2 vs. VGAIN at Three Output Voltages, High Gain, f = 1 MHz
(See Figure 53)
Figure 36. Output Referred IP3 (OIP3) vs. VGAIN
–20
5
f = 10MHz
f = 1MHz
–30
0
–40
–5
INPUT POWER (dBm)
DISTORTION (dBc)
0.5
04976-037
DISTORTION (dBc)
5MHz (HIGH)
30
–50
2V p-p
HLxx = LOW
–10
HLxx = HIGH
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–60
1V p-p
–70
–15
–20
0.5V p-p
0
0.5
1.0
1.5
2.0
2.5
3.0
VGAIN (V)
–30
0
0.5
1.0
1.5
2.0
2.5
VGAIN (V)
Figure 34. HD3 vs. VGAIN at Three Output Voltages, High Gain (See Figure 53)
3.0
04976-038
–90
–25
04976-035
–80
Figure 37. Input P1dB (IP1dB) vs. VGAIN
0
VOUT = 1V p-p
VGAIN = 3V
–10
10mV
–40
–50
IMD3 (HIGH)
–60
–70
IMD3 (LOW)
–80
–90
90
10
0
50mV
1
10
FREQUENCY (MHz)
100
10ns
04976-036
IMD3 (dBc)
–30
100
Figure 38. Small Signal Pulse Response, Low Gain (See Figure 51)
Figure 35. IMD3 vs. Frequency
Rev. A | Page 12 of 28
04976-039
HARMONIC DISTORTION (dBc)
–20
AD8335
2V
90
100mV
10
10ns
500mV
90
10
0
04976-040
0
100
100mV
Figure 39. Large Signal Pulse Response, Low Gain (See Figure 51)
100µs
04976-043
HARMONIC DISTORTION (dBc)
HARMONIC DISTORTION (dBc)
100
Figure 42. Small Signal Enable Response (See Figure 51)
2
CL = 47pF
VOUT (V)
CL = 0pF
0
100
90
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–1
10
0
1V
0
10
20
30
40
50
60
70
80
90
100
TIME (ns)
Figure 40. Large Signal Pulse Response for Various Capacitive Loads,
CL = 0 pF, 10 pF, 20 pF, 47 pF Each Output (See Figure 51)
Figure 43. Large Signal Enable Response (See Figure 51)
1V
HARMONIC DISTORTION (dBc)
100
90
10
0
400ns
04976-042
HARMONIC DISTORTION (dBc)
2V
500mV
100µs
04976-041
INPUT IS NOT TO SCALE
–2
04976-044
HARMONIC DISTORTION (dBc)
INPUT
1
2V
CL = 22pF
CL = 10pF
100
90
10
0
1µs
Figure 41. Gain Response, VGAIN Stepped from 0 V to3 V, VOUT = 2 V p-p
(See Figure 51)
04976-045
VGAIN = 2V
Figure 44. Preamp Overdrive Recovery,
50 mV p-p to 1.5 V p-p at Preamp Input (Measured at Preamp Output)
Rev. A | Page 13 of 28
AD8335
95
HARMONIC DISTORTION (dBc)
100
90
10
1µs
04976-046
0
90
VGAIN = 2.5V
85
80
75
70
65
60
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 45. VGA Overdrive Recovery, 40 mV to 500 mV Input, VGAIN = 2.5 V
100
04976-047
QUIESCENT SUPPLY CURRENT (mA)
1V
Figure 47. Quiescent Supply Current vs. Temperature
0
2V
–10
VGAIN = 2.5V
100
VGAIN = 1.5V
90
–30
–40
–60
–70
www.BDTIC.com/ADI
VGAIN = 0.5V
10
VGAIN = 0V
0
500mV
–80
100k
1M
10M
100M
FREQUENCY (Hz)
1µs
Figure 46. PSRR vs. Frequency (All Bypass Capacitors Removed)
Figure 48 High/Low Response Time
Rev. A | Page 14 of 28
04976-101
–50
04976-100
PSRR (dB)
–20
AD8335
TEST CIRCUITS
NETWORK ANALYZER
50Ω
50Ω
OUT
0.1µF
IN
237Ω
0.1µF
AD8335
28Ω
0.1µF
50Ω
1:1
22pF
237Ω
0.1µF
0.1µF
28Ω
1:1
49.9Ω
237Ω
0.1µF
04976-048
0.1µF
50Ω
IN
49.9Ω
237Ω
28Ω
22pF
AD8335
0.1µF
249Ω
04976-049
18nF
OSCILLOSCOPE
18nF 249Ω
28Ω
Figure 49. Test Circuit for Gain and Bandwidth Measurements
Figure 51. Test Circuit for Transient Measurements
NETWORK ANALYZER
50Ω
SPECTRUM
ANALYZER
AD8335
0.1µF
50Ω
0.1µF
50Ω
OUT
18nF
IN
50Ω
249Ω
IN
04976-050
0.1µF
0.1µF
AD8335
0.1µF
237Ω
28Ω
www.BDTIC.com/ADI
22pF
0.1µF
49.9Ω
22pF
1:1
50Ω
237Ω
0.1µF
0.1µF
28Ω
Figure 52. Test Circuit for S11 Measurements
Figure 50. Test Circuit for Noise Measurements
SIGNAL
GENERATOR
0.1µF
LPF
50Ω
SPECTRUM
ANALYZER
249Ω
AD8335
0.1µF
237Ω
28Ω
50Ω
22pF
0.1µF
50Ω
IN
1:1
237Ω
0.1µF
28Ω
Figure 53. Test Circuit Used for Distortion Measurements
Rev. A | Page 15 of 28
04976-051
18nF
04976-052
1:1
49Ω
AD8335
THEORY OF OPERATION
Figure 54 is a simplified block diagram of a single channel. Each
channel consists of a low noise preamplifier (PrA) followed by a
VGA with a user-selectable gain of 20 dB or 28 dB. Channels are
enabled in pairs, Channel 1 and Channel 2, and Channel 3 and
Channel 4. The preamps are enabled by grounding the SPxx
pins and powered down by connecting them to the positive supply.
The ENxx pins are connected to the positive supply to enable
the VGAs and the overall channel. HLxx configures VGA for a
fixed gain of 20 dB or 28 dB, with 0 V or 5 V applied to the
HLxx pins, respectively. Channel 1 and Channel 2 share Pin HL12,
and Channel 3 and Channel 4 share Pin HL34. The HLxx pins
are typically hardwired to adjust the VGA gain according to an
ADC resolution of 12 bits for low gain and 10 bits for high gain.
Gain [dB] = 20.1
dB
VGN + ICPT
V
(1)
where ICPT = −16.1 dB for low gain mode −8.1 dB for high
gain mode.
Power consumption is 95 mW/channel from a 5 V supply, or
380 mW for all four channels. Power is distributed 35% for the
PrA, and 65% for the remainder of the circuit. The preamps can
be shut down via the SP12 and SP34 pins if a user wants to use
the VGAs only. However, to avoid feedthrough around the
preamp, feedback resistors should not be installed.
Table 4. Channel Gain Distribution
Low Nominal Gain
(dB)
18.06
0 to −48.16
20
−10.1 to +38.6
High Nominal Gain
(dB)
18.06
0 to −48.16
27.96
−2.14 to +46.02
The signal path is fully differential throughout to maximize
signal swing and reduce even-order distortion; however, the
preamplifiers are designed to be driven from a single-ended
signal source. Gain values are referenced from the single-ended
PrA input to the differential output of either the PrA or the
VGA. Again referring to Figure 54, the system gain is
distributed as listed in Table 4.
Section
PrA
Attenuator
Output Amp
Aggregate
In the remainder of this document, the gain values are rounded
to −10 dB to +38 dB for low gain mode and to −2 dB to +46 dB
for high gain mode. If desired, Equation 1 can be used to
calculate the gain at a value of VGAIN.
Table 5 summarizes the enable/shutdown logic and resulting
supply current.
ENABLE SUMMARY
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Table 5. Control Pin Logic and Power Consumption
EN12
SP12
EN34
SP34
PrA1/PrA2
VGA1/VGA2
PrA3/PrA4
VGA3/VGA4
IS
High
High
Low
Low
Low
High
Low
High
High
High
Low
Low
Low
High
Low
High
On
Off
Off
Off
On
On
Off
Off
On
Off
Off
Off
On
On
Off
Off
76 mA
52 mA
0.8 mA
0.8 mA
+1
VINx
PONx
INTERPOLATOR
OUTPUT AMP
20dB OR 28dB
RFB
PIPx
ATTENx
–48dB TO 0dB
PrA
18dB
PMDx
+1
VOLx
+1
BIAS
+1
GAIN INTERFACE
HIGH/LOW
ENxx
POPx
VIPx
VCMx
VGNx SLxx
Figure 54. Simplified Block Diagram of Single Channel
Rev. A | Page 16 of 28
HLxx
04976-054
RS
VOHx
+1
AD8335
The preamplifier consists of a fixed gain amplifier with differential outputs. With the negative output available and a fixed gain
of 8 (18.06 dB), an active input termination is synthesized by
connecting a feedback resistor between the negative output and
the positive input, Pin PIPx. This technique is well known and
results in the input resistance shown in Equation 2.
R IN
R FB
=
(1 + A / 2)
RIN = 500Ω, RFB = 2.5kΩ
RSH = ∞, CSH = 0pF
RIN = 200Ω, RFB = 1kΩ
RSH = 50Ω, CSH = 22pF
100
RIN = 100Ω, RFB = 499Ω
RIN = 50Ω, RFB = 249Ω
RSH = ∞, CSH = 0pF
RSH = 50Ω, CSH = 22pF
(2)
where A/2 is the single-ended gain, or the gain from the PIPx
inputs to the PONx outputs. Since the amplifier has a gain of ×8
from its input to its differential output, it is important to note
that the gain A/2 is the gain from Pin PIPx to Pin PONx, which
is 6 dB lower, or 12.04 dB (×4). The input resistance is reduced
by an internal bias resistor of 14.7 kΩ in parallel with the source
resistance connected to Pin PIPx, with Pin PMDx ac-grounded.
Equation 3 can be used to calculate the needed RFB for a desired
RIN, and is used for higher values of RIN.
R IN
1k
10
100k
1M
10M
FREQUENCY (Hz)
50M
04976-102
Although the preamp signal path is fully differential, the design
is optimized for single-ended input drive and signal source
resistance matching. Thus, the negative input to the differential
preamplifier PMDx pins must be ac-grounded to provide a
balanced differential signal at the PrA outputs. Detailed information regarding the preamplifier architecture is found in the
LNA section of the AD8331/AD8332 data sheet.
the lower frequency limit is determined by the size of the accoupling capacitors, and the upper limit is determined by the
preamplifier BW. Furthermore, the input capacitance and RS
limits the BW at higher frequencies.
INPUT IMPEDANCE (Ω)
PREAMP
Figure 55. RIN vs. Frequency for Various Values of RFB;
Effects of RSH and CSH are also shown.
Figure 55 shows RIN vs. frequency for various values of RFB. Note
that at the lowest value, 50 Ω, RIN peaks at frequencies greater
than 10 MHz. This is due to the BW roll-off of the PrA as mentioned earlier. The RSH and CSH network shown in Figure 58
reduces this peaking.
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R
= FB || 14.7 kΩ
(1 + 4)
(3)
For example, to set RIN = 200 Ω, the value of RFB is 1.013 kΩ. If
the simplified Equation 2 is used to calculate RIN, the value is
197 Ω, resulting in a less than 0.1 dB gain error. Factors such as
a widely varying source resistance might influence the absolute
gain accuracy more significantly. At higher frequencies, the
input capacitance of the PrA needs to be considered. The user
must determine the level of matching accuracy and adjust RFB
accordingly.
The bandwidths (BW) of the preamplifier and VGA are
approximately 110 MHz each, resulting in a cascaded BW of
approximately 80 MHz. Ultimately the BW of the PrA limits the
accuracy of the synthesized RIN. For RIN = RS up to approximately
200 Ω, the best match is between 100 kHz and 10 MHz, where
However, as can be seen for larger RIN values, parasitic
capacitance starts rolling off the signal BW before the PrA can
produce peaking and the RSH/CSH network further degrades the
match. Therefore, RSH and CSH should not be used for values of
RIN greater than 50 Ω.
Noise
The total input referred noise (IRN) is approximately 1.3 nV/√Hz.
Allowing for a gain of ×8 in the preamp, the VGA noise is
0.46 nV/√Hz referred to the PrA input. The preamp noise is
1.2 nV/√Hz. It is important to note that these noise values
include all amplifier noise sources, including the VGA and the
preamplifier gain resistors. Frequently, manufacturer noise
specifications exclude gain setting resistors, and the voltage
noise spectral density of an op amp might be presented as
1 nV/√Hz. Including the gain resistors results in a much higher
noise specification.
Rev. A | Page 17 of 28
AD8335
Figure 56 shows the simulated noise figure (NF) vs. source
resistance, and various values of preamplifier RIN from 50 Ω,
to 14.7 kΩ, the value seen looking into the PIPx pins when
RFB = ∞. As shown in the figure, the minimum NF for RIN = 50 Ω
is slightly less than 7 dB. Note that, for this preamplifier, the NF
is optimized for the RIN from 50 Ω to 200 Ω; for RFB = ∞, the
minimum NF is at approximately 480 Ω. This optimum noise
resistance can also be calculated by dividing the input referred
voltage noise by the current noise.
16
RIN = 50Ω
RFB = 250Ω
INCLUDES NOISE OF VGA
f = 1MHz
14
RIN = 75Ω
RFB = 375Ω
RIN = 100Ω
RFB = 500Ω
10
8
6
4
2
SIMULATION
0
10
RIN = 14.7kΩ
RFB = ∞
RIN = 200Ω
RFB = 1kΩ
100
RS (Ω)
1k
04976-066
NOISE FIGURE (dB)
12
Figure 56. Simulated Noise Figure vs. RS for
Various Fixed Values of RIN, Actively Matched
VGA
either gain setting; therefore, only the output referred noise
(ORN) changes (by 8 dB) without affecting any other parameters.
Attenuator
The attenuator is an 8-stage differential R-2R ladder with a total
attenuation of 48.16 dB or 6.02 dB per tap. The effective input
resistance per side is 320 Ω nominal for a total differential resistance of 640 Ω. The common-mode voltage of the attenuator
and the VGA is controlled by an amplifier that uses the same
midsupply voltage derived in the preamplifier, permitting dc
coupling of the PrA to the VGA without introducing large offsets
due to common-mode differences. However, when dc coupling
between the PrA and VGA, any offset from the PrA is amplified
as the gain is increased, producing an exponentially increasing
VGA output offset. When the PrA and the VGA are ac-coupled,
the output offset is unchanged with changes in gain (see Figure 15).
As a result, ac coupling is recommended for most applications.
As can be seen from Figure 54, The VCMx pins connect to the
respective midpoints on each channel and are used to ac decouple
the common-mode node at high frequencies. It is very important that at least a 0.1 μF capacitor be used, with better decoupling
at higher frequencies when another smaller capacitor (10 nF) is
connected in parallel. The internal +1 buffer provides correct
common-mode bias levels and any dynamic currents have to be
absorbed by the external decoupling capacitors.
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Gain Control
As seen in Figure 54, the basic architecture, an X-AMP®, consists
of a ladder attenuator, followed by a fixed gain amplifier with
selectable input stages. Earlier examples of this architecture are
to be found in the AD60x series, AD8331/AD8332, and AD8367
VGAs. Through a proprietary, temperature-compensated
interpolator design, the bias currents to the input gm stages are
continuously steered from right to left (decreasing attenuation)
resulting in increasing gain.
The HLxx gain pins (HL12 and HL34)select one of two output
amplifier networks consisting of the feedback resistors, amplifier
stages, and buffers.
Optimizing the System Dynamic Range
The VGA output gain switch of 8 dB (×2.5) optimizes the VGA
noise floor for a 10-bit or 12-bit ADC, assuming a full-scale ADC
input voltage of 1 V p-p.
At low gain, the ADC SNR should limit the system noise performance, whereas at high gains, the noise is defined by the source
and preamplifier. The maximum voltage swing is bounded by
the full-scale peak-to-peak ADC input voltage (typically 1 V p-p
to 2 V p-p). The noise performance is optimized by adjusting
the noise floor of the VGA according to the ADC resolution.
The SNR of a 12-bit converter is theoretically 12 dB better than
a 10-bit; however, approximately 8 dB is typical in practice,
accounting for the 8 dB gain option of the AD8335. The IRN
and the power consumption of the VGA are unaffected by
The gain control interface has two inputs, VGAIN (VGNx pins)
and VSLP (SLxx pins). The slope input is intended only as a
decoupling pin, and the only guaranteed gain slope is the
20 dB/V default. However, if a voltage is applied to the VSLP
inputs, the gain slope can be increased by reducing the slope
voltage. For example, if a voltage of 1.67 V is applied to the SLxx
pins, the gain slope changes to 30 dB/V. Use Equation 4 to
calculate the gain slope.
VSLP =
2.5 V× 20.1 dB/V
Slope
(4)
VGAIN varies the gain of the VGA through the interpolator by
selecting the appropriate input stages connected to the input
attenuator. The nominal VGAIN range for 20 dB/V is 0 V to 3 V,
with the best gain linearity from approximately 0.5 V to 2.5 V,
where the error is typically less than ±0.2 dB. For VGAIN voltages
above 2.5 V and less than 0.5 V, the error increases (see Figure 4).
The value of the VGAIN voltage can be increased to that of the
supply voltage, without gain foldover.
Each channel has separate gain control pins that can be
connected to a common voltage source such as found in most
ultrasound applications. For control of individual channels,
connect the appropriate gain control signal to each channel.
Rev. A | Page 18 of 28
AD8335
Output Stage
Duplicate output stages of the VGA provide an 8 dB (×2.5) gain
switch. The gain switch is intended to optimize the output noise
floor for either a 10-bit or a 12-bit ADC. The VGA gain is 20 dB
(×10) in low gain mode and 28 dB (×25) in high gain mode. The
logic setting of the HLxx pins selects between output amplifiers
including the gain resistors and feedback buffers.
100 MHz bandwidth is maintained between the amplifiers by
changing the compensation capacitance as the gain switches gain
settings. Power consumption is the same for either level of gain.
In certain applications, power consumption can be reduced by
lowering the supply voltage as much as possible; however, the
output dynamic range is affected by the more limited swing. The
fully differential signal path of the AD8335 restores 6 dB of
dynamic range, and the common-mode level is maintained
automatically at half the supply voltage for maximum signal
swing. The differential signal has the added benefit of suppressing the even order harmonics.
The output amplifier is designed to drive a nominal differential
load of 500 Ω or greater; the signal swing can be as large as
5 V p-p differential before clipping occurs. However, that distortion increases before reaching the clipping level. Distortion is
shown in Figure 25 through Figure 34 for typical values of
1 V p-p or 2 V p-p (full-scale inputs for many ADCs). The
output is ac-coupled to a differential antialias filter driving a
differential ADC. Most modern ADCs have differential inputs
and achieve optimum performance when driven differentially.
For more information, see the Applications Information section.
VGA Noise
As with all X-AMPs, the output noise of the VGA is constant
with gain. This causes the input referred noise to increase as the
gain is decreased. This characteristic is desirable in receiver
applications where wide dynamic range input signals are compressed with a fixed ceiling and noise floor into an ADC. The
VGA output noise is approximately 33 nV/√Hz in low gain
mode and 2.5 times higher than this, 83 nV/√Hz, in high gain
mode. As the gain increases, the noise of the preamplifier prevails
and, at the maximum VGA gain, the output noise is approximately 90 nV/√Hz and 225 nV/√Hz for low and high gain
modes, respectively.
The output SNR is determined by the noise floor and the largest
signal level, typically limited by the FS of the ADC. Modulation
noise, essentially the noise introduced by the gain control input,
can be troublesome. Normally one tends to look at the main
amplifier signal path for noise, but a VGA is really a multiplier
with the following function:
VOUT =
VGAIN × VIN
VREF
(5)
where VREF (bias) and VGAIN (gain control interface) are both
noise contributors under certain conditions. It is therefore
important that the gain control signals be kept clean, especially
at higher gain control slopes.
www.BDTIC.com/ADI
Rev. A | Page 19 of 28
AD8335
APPLICATIONS INFORMATION
Most modern machines use digital beamforming. In this
technique, the signal is converted to digital format immediately
following the TGC amplifier; beamforming is done digitally.
ULTRASOUND
The primary application for the AD8335 is medical ultrasound.
Figure 57 shows a simplified block diagram of an ultrasound
system. The most critical function of an ultrasound system is
the time gain control (TGC) compensation for physiological
signal attenuation. Because the attenuation of ultrasound
signals is exponential with respect to distance (time), a linearin-dB VGA is the optimal solution.
Typical ADC resolution in general purpose machines is 10 bits
with sampling rates greater than 40 MSPS, and high-end
systems use 12 bits.
Power consumption and low cost are of primary importance in
low-end and portable ultrasound machines, and the AD8335 is
designed for these criteria.
Key requirements in an ultrasound signal chain are very low
noise, active input termination, fast overload recovery, low
power, and differential drive to an ADC. Because ultrasound
machines use beamforming techniques requiring large binary
weighted numbers (for example, 32 to 512) of channels, the
lowest power at the lowest possible noise is of key importance.
For additional information regarding ultrasound systems, refer
to “How Ultrasound System Considerations Influence FrontEnd Component Choice”, Analog Dialogue, Vol. 36, No. 3,
May–July 2003.
(www.analog.com/library/analogDialogue/archives/36-03/
ultrasound/index.html)
TX HV AMPs
BEAMFORMER
CENTRAL CONTROL
TX BEAMFORMER
www.BDTIC.com/ADI
MULTICHANNEL
TGC USES MANY VGAs
HV
MUX/
DEMUX
T/R
SWITCHES
AD8335
VGAs
Rx BEAMFORMER
(B AND F MODES)
LNAs
TGC
TIME GAIN COMPENSATION
BIDIRECTIONAL
CABLE
CW (ANALOG)
BEAMFORMER
SPECTRAL
DOPPLER
PROCESSING
MODE
AUDIO
OUTPUT
Figure 57. Simplified Ultrasound System Block Diagram
Rev. A | Page 20 of 28
IMAGE AND
MOTION
PROCESSING
(B MODE)
COLOR
DOPPLER (PW)
PROCESSING
(F MODE)
DISPLAY
04976-053
TRANSDUCER
ARRAY
128, 256 ETC.
ELEMENTS
AD8335
resistor (or RIN), along with the exact value and nearest standard
1% feedback resistor. For values other those than listed in Table 6,
RFB can be calculated using Equation 6. For values larger than
1 kΩ, it may be advantageous to simply remove RFB.
BASIC CONNECTIONS
Figure 58 shows the basic connections for the AD8335. Input
signals enter from the left and output signals exit from the right,
providing straight line signal paths. Of course, a device with
four differential VGAs such as this requires a multilayer printed
circuit board. Power supply isolation is shown for the preamps,
and for the VGA sections. If components are mounted to both
sides of the board, those in the signal path should be located on
the top, with power-supply decoupling components on the
wiring side.
Table 6. Feedback Resistor Values for Various Input
Resistances
RIN (Ω)
Exact RFB Value (Ω)
Nearest Standard 1% Value (Ω)
200
500
1000
1014
2588
5365
1.02k
2.61k
5.36k
PREAMP CONNECTIONS
To configure the AD8335 for input matching, a feedback resistor
(RFB) is ac-coupled between Pin PONx and Pin PIPx. AC coupling
accommodates dissimilar common-mode voltages at the input
and output ports. For values of RSOURCE between 50 Ω and 200 Ω,
RFB is simply 5 × RSOURCE. Table 6 lists a few larger values of source
5 × RIN
R
1 − IN
14.7 k
RFB (Ω) =
(6)
+5V
0.1µF
RSH1
49.9Ω
CSH1
22pF
SL12
1nF* 0.1µF 1nF* 0.1µF
H
0.1µF
L
VPP
0.1µF
64
0.1µF
0.1µF
0.1µF
PIP2
VGN2
VGN1
RFB1
0.1µF 249Ω
PIP1
63
62
+5V
61
60
59
57
58
56
55
54
53
52
0.1µF
51
49
50
VOH1
0.1µF
PIP3
RFB3
249Ω
VPP 14
0.1µF
15
RSH3
49.9Ω
16
CSH3
22pF
0.1µF
HL12
SL12
SP12
EN12
VCM2
VGN2
VGN1
VCM1
COM1
VIN1
VIP1
POP1
PON1
VOH3
VIP3
VOL3
POP3
VPV3
PON3
VPV4
VPP3
VOL4
PIP3
VOH4
PMD3
GND4
17
0.1µF
18
19
20
VPP
0.1µF
PIP4
0.1µF
RSH4
49.9Ω
*SEE TEXT
VPP1
VIN3
21
22
23
24
25
26
27
0.1µF
CSH4
22pF
29
30
31
+5V
0.1µF
1nF*
RFB4
249Ω
28
1nF*
VGN3
Figure 58. Basic Connections for RIN = 50 Ω
Rev. A | Page 21 of 28
+5V
47
120nH FB
46
45 VPV
0.1µF
44
43
0.1µF
42
0.1µF
VOL2
VOH2
41
40
39
0.1µF
38
0.1µF
37
VOH3
VOL3
VPV
36
35
0.1µF
34
0.1µF
33
VOL4
VOH4
+5V
H
32
0.1µF
L
0.1µF
0.1µF
VGN4
VOL1
48
SL34
04976-056
13
GND3
0.1µF
HL34
12
GND2
AD8335
COM3
SL34
0.1µF
COM2
SP34
0.1µF
VOH2
VIN2
EN34
11
VOL2
VCM3
10
VIP2
VGN3
9
VPV2
VCM4
0.1µF
POP2
VGN4
8
VPP
VPV1
COM4
120nH FB
+5V
PON2
VIN4
6
7
VOL1
VIP4
0.1µF
VPP2
POP4
5
VOH1
PON4
4
0.1µF
GND1
PIP2
VPP4
VPP
3
PMD2
PIP4
2
PMD1
0.1µF
1
PMD4
0.1µF
RFB2
249Ω
PIP1
www.BDTIC.com/ADI
RSH2
49.9Ω
CSH2
22pF
AD8335
The PIPx inputs must be capacitively coupled from the signal
source because they have a nominal dc level of more than half
the supply voltage. AC coupling capacitors throughout the circuit
should be as large as possible for the application. Although 0.1 μF
capacitors are shown in Figure 58 (and used in most positions
in the evaluation board), values of these capacitors should be
determined by the application. Capacitors used for coupling
PMDx and PIPx pins should be the same value.
When synthesizing low values of RIN, the bandwidth of the
preamplifier produces some peaking at the high end of the
frequency response. The optional series RSHx/CSHx network
shown in Figure 58 flattens the response (see Figure 55). With a
50 Ω source, the resistor and capacitor values should be 49.9 Ω
and 22 pF. For RS values greater than 100 Ω, the network is not
needed. The circuit is stable in either scenario.
The starred capacitors in Figure 58 (*) on the VGNx pins can be
removed when faster gain control signals are required.
INPUT OVERDRIVE
Excellent overload behavior is of primary importance in ultrasound. Both the preamplifier and VGA have built-in overdrive
protection and quickly recover after an overload event.
user. With such diodes, clamping levels of ±0.5 V or less greatly
enhance the system overload performance.
+HV
RFB
PONx
OPTIONAL
SCHOTTKY
OVERLOAD
CLAMP
Rs
PIPx
3
PrA
18dB
PMDx
2
TRANSDUCER
POPx
1
–HV
BAS40-04
04976-057
The preamp PMD pins must be capacitively coupled to ground.
Although the preamplifier is a differential design, the PMD pins
are the internal input bias nodes and are made available for
bypassing only. Do not use these pins as signal inputs.
Figure 59. Input Overload Protection
LOGIC INPUTS
The EN12 and EN34 enable pins, the SP12 and SP34 preamp
shutdown pins, and the HL12 and HL34 high/low pins are all
logic inputs of the AD8335. The enable inputs turn on and off
each of the corresponding pairs of channels; the preamp
shutdown pins do the same for the preamplifiers only; inputs
HL12 and HL34 set the high/low gain for Channel 1 and
Channel 2, and Channel 3 and Channel 4, respectively.
Shutting down the preamplifiers allows use of the VGAs alone,
while reducing power consumption. The VGAs cannot be shut
down independently. The SPxx (shutdown preamp) pins are
logic high; thus, the pins are grounded to enable the preamplifiers.
www.BDTIC.com/ADI
Input Overload Protection
As with any amplifier, voltage clamping prior to the inputs is
highly recommended if the application is subject to high
transient voltages.
A block diagram of a simplified ultrasound transducer interface
is shown in Figure 59. A common transducer element serves the
dual functions of transmit and receive of ultrasound energy.
During the transmit phase, high voltage pulses are applied to
the ceramic elements. A typical T/R (transmit/receive) switch
may consist of four high voltage diodes in a bridge configuration.
Although they ideally block transmit pulses from the sensitive
receiver input, diode characteristics are not ideal, and resulting
leakage transients impinging on the PIPx inputs can be
problematic.
Because ultrasound is a pulse system, and time-of-flight is
used to determine depth, quick recovery from input overloads
is essential. Overload can occur in the preamp and the VGA.
Immediately following a transmit pulse, the typical VGA gains
are low, and the PrA is subject to overload from T/R switch
leakage. With increasing gain, the VGA can become overloaded
from strong echoes that occur with near field echoes and
acoustically dense materials, such as bone.
Figure 59 illustrates an external overload protection scheme. A
pair of back-to-back Schottky diodes is installed prior to
installing the ac-coupling capacitors. Although the BAS40 is
shown, many types are available and merit investigation by the
The pins can be enabled by connecting to the supply or to
ground for fixed enable or disable, or to the output of a logic
device. Be sure to check the data sheet of the device for voltage
and current requirements.
COMMON-MODE PINS
The common-mode VCMx pins are provided for bypassing the
internal common-mode reference for each channel to ground.
They require a capacitor at each of the four pins and can neither
be connected together nor driven by an external source.
DRIVING ADCs
The AD8335 VGA is designed to drive 10-bit and 12-bit ADCs
with minimal extra components. Because the AD8335 is a single
supply 5 V part and many of the newest ADCs operate from a 3 V
supply, dissimilar common-mode voltages exist between the VGA
output and the ADC input. This level shift is most easily accommodated by ac coupling, especially if the signal is filtered, as is
the case in most ultrasound and communications applications.
When an antialiasing filter (AAF) is called for, it is advantageous
to implement a differential configuration. A fully differential
AAF requires approximately 1.5 times the number of components
than a single-ended filter, because the components that in the
single-ended case are tied to ground, now connect across the
differential signal path. Although the series components double,
the component count for the differential filter is more economical
when compared to simply building a pair of single-ended filters
requiring twice as many components.
Rev. A | Page 22 of 28
AD8335
EVALUATION BOARD
The AD8335 evaluation board enables an efficient means to
become familiar with the operating characteristics and features
of the AD8335 quad VGA. Jumpers provide for exercising the
user-selectable features of the AD8335, such as the preamp and
VGAs and the optional high and low gain ranges. Test pins are
provided for power and gain voltage connections and for probes
used to observe waveforms at the input and outputs. Provisions
are also made for driving the gain controls dynamically.
resistors protect the outputs from accidental short circuits,
limiting the output current. Transformer coupling is intended
for low impedance loads. 50 Ω single-ended loads can be connected directly via the transformer-coupled SMA connectors.
The preferred signal detector is a high impedance differential
probe connected to the VOx 2-pin headers, as indicated in
Figure 62.
All channels are tested for full functionality. The board is built
and tested using the components shown in black in the schematic
of Figure 61. Mounting patterns for optional SMA connectors
are provided for applying dynamic gain control inputs. The
components and jumpers are shown in gray in the schematic.
The input impedance of the LNA is configured for 50 Ω to
match the output impedance of most signal generators and
network analyzers. Input impedances up to 14.7 kΩ are obtained
with appropriate values of RFB1-4. refer to Table 6 for resistor
values. The board is designed for surface-mount components.
The basic board connections for measuring bandwidth are
shown in Figure 62. A 5 V, 200 mA (minimum) power supply is
required for the supply rail, and a low noise voltage reference
supply is required for VGNx inputs
MEASUREMENT SETUP
BOARD LAYOUT
The evaluation board circuitry is four layers, with power and
ground on the inner layers interconnecting circuitry on the
outer layers. Figure 63 through Figure 68 illustrate various
board layers, and Table 7 is a bill of materials.
Optional high frequency transformers are provided for
differential to single-ended conversion of the output. Series
04976-060
www.BDTIC.com/ADI
Figure 60. Photograph of the AD8335-EVALZ Evaluation Board
Rev. A | Page 23 of 28
AD8335
+5V
GND GND1 GND2 GND3 GND4
VGN12
+5V
2
RFB2
249Ω
3
C71
0.1µF
4
5
C85
0.1µF
C84
0.1µF
6
7
8
9
10
11
C65
0.1µF
C60
0.1µF
12
SP
D
EP
50
49
PMD2
GND1
PIN2
VOH1
VPP2
VOL1
PON2
VPV1
POP2
VPV2
VIP2
VOL2
VIN2
VOH2
COM2
GND2
AD8335
U1
COM3
GND3
VIN3
VOH3
VIP3
VOL3
POP3
VPV3
PON3
VPV4
VPP3
VOL4
PIN3
VOH4
PMD3
GND4
T1
1:1
VO1
R28
237Ω
W2
HL12
VCM1
52 51
C34
0.1µF R26
237Ω
W1
VO1
SL12
53
L
SL12
C57
0.1µF
SP12
54
H
HL12
SP12
EN12
55
VGN2
56
VGN1
57
58
COM1
59
VIP1
61 60
VIN1
62
E
EN12
C68
0.1µF
C16
C81 C53
1nF
1nF 0.1µF
C1
0.1µF
POP1
1
63
VGN2
VGN1
+5V
VPP1
64
C9
0.1µF
+5V
VGNM2
C14
0.1µF
PON1
CFB2
0.018µF
RS2
49.9Ω
IN2
CS2
22 pF
PMD1
PIN2
C83
0.1µF
C11
0.1µF
C8
0.1µF
PIN1
RS1
49.9Ω
CS1
22pF
IN1
VGNM1
C3
10µF
10V
CFB1
0.018µF RFB1
249Ω
C10
0.1µF
PIN1
+5V
VCM2
+
C36
0.1µF
48
C7
0.1µF
47
46
VPV
L2
120 nH FB
+5V
C39
R31
W3 0.1µF 237Ω
45
T2
1:1
44
43
VO2
42
C41
R33
W4 0.1µF 237Ω
VO2
C44
0.1µF R36
237Ω
T3
1:1 VO3
41
40
W5
39
38
VO3
37
W6
C46
0.1µF R38
237Ω
W7
R41
237Ω
CS3
22pF
C24
0.1µF
PIN4
IN4
17
C20
0.1µF
RS4
49.9Ω
CS4
22pF
CFB4
0.018µF
18
19
20
21
22
23
26
27
29 30
28
31
35
VPV
34
33
VO4
HL34
SL34
SP34
EN34
VCM3
VCM4
25
VGN3
COM4
24
VGN4
VIN4
RS3
49.9Ω
36
32
+5V
C23
0.1µF
+5V
RFB4
249Ω
C74
0.1µF
C18
0.1µF
C64
1nF
C55
0.1µF
E
C80
1nF
EN34
C19
0.1µF
COMPONENTS
SHOWN IN GRAY
ARE NOT INSERTED
D
VGN4
C62
0.1µF
C51
0.1µF
SP34
EP
VGNM3
VGN34
Figure 61. AD8335-EVALZ Schematic Diagram
Rev. A | Page 24 of 28
HL34
L
VO4
SP
VGN3
VGNM4
R43
237Ω
W8
H
+5V
C49
0.1µF
T4
1:1
SL34
04976-061
IN3
16
C21
0.1µF
VIP4
CFB3
0.018µF
POP4
C27
0.1µF
15
PON4
PIN3
RFB3
249Ω
PMD4
C26
0.1µF
VPP4
14
PIN4
www.BDTIC.com/ADI
13
+5V
AD8335
PRECISION VOLTAGE REFERENCE
(FOR VGAIN)
GND
POWER
SUPPLY
GND
+5 V
NETWORK ANALYZER
SIGNAL
INPUT
04976-063
www.BDTIC.com/ADI
DIFFERENTIAL PROBE
04976-063
PROBE
POWERSUPPLY
Figure 62. AD8335-EVALZ Typical Test Connections
Rev. A | Page 25 of 28
04976-064
04976-069
AD8335
Figure 65. AD8335-EVALZ Secondary Side Copper
Figure 63. AD8335-EVALZ Assembly
04976-065
04976-070
www.BDTIC.com/ADI
Figure 66. AD8335-EVALZ Internal Power Plane
Figure 64. AD8335-EVALZ Component Side Copper
Rev. A | Page 26 of 28
Figure 67. AD8335-EVALZ Internal Ground Plane
04976-072
04976-071
AD8335
Figure 68. AD8335-EVALZ Primary Side Silk screen
BILL OF MATERIALS
Table 7.
Qty
1
5
6
35
4
4
4
16
8
1
8
4
4
6
4
1
1
www.BDTIC.com/ADI
Reference Designator
+5 V
GND to GND4
SL12, SL34, VGN1 to VGN4
C1, C7, C8, C9, C10, C11, C14, C18, C19,
C20, C21, C23, C24, C26, C27, C34, C36,
C39, C41, C44, C46, C49, C51, C53, C55,
C57, C60, C62, C65, C68, C71, C74, C83,
C84, C85
C16, C64, C80, C81
CFB1 to CFB4
CS1 to CS4
IN1 to IN4, VO1 to VO4, W1 to W8
PIN1 to PIN4, VO1 to VO4
L2
R26, R28, R31, R33, R36, R38, R41, R43
RFB1 to RFB4
RS1 to RS4
EN12, EN34, HL12, HL34, SP12, SP34
T1 to T4
U1
C3
Description
0.125 in diameter red test loop
0.125 in diameter black test loop
0.125 in diameter black test loop
0.1 μF, 16 V, 0603 ceramic capacitor
Manufacturer
Components Corp.
Components Corp.
Components Corp.
Kemet
Manufacturer
Part Number
TP-104-01-02
TP-104-01-00
TP-104-01-07
C0603C104K4RAC
1 nF, 10%, 100 V, 0603 capacitor
0.018 μF, 0603 capacitor
22 pF, 5%, 50 V, 0603
0.1 in, 2-pin header
SMA, right angle PC mount/connector
Ferrite bead, 120 nH, 0603 inductor
237 Ω, 1%. 1/10 W, 0603 resistor
249 Ω, 1%. 1/10 W, 0603 resistor
49.9 Ω, 1%. 1/10 W, 0603 resistor
0.1 in, 3-pin header
RF, 0.015 MHz to 300 MHz transformer
Integrated circuit, quad VGA
10 μF, 10 V, tantalum, Size A capacitor
Panasonic
Panasonic
Panasonic
FCI
Amphenol
Murata
Panasonic-ECG
Panasonic-ECG
Panasonic-ECG
Molex
Mini Circuits
Analog Devices
Panasonic-ECG
ECJ-1VB2Z102K
ECJ-1VB1E183K
ECJ-1VC1H220J
69157-102
901-143-6RFX
BLM18BA750SN1D
ERJ-6ENF2370V
ERJ-2RKF2490X
ERJ-6ENF49R9V
22-10-2031
T1-6T KK81
AD8335ACPZ
ECS-T1AY106R
Rev. A | Page 27 of 28
AD8335
OUTLINE DIMENSIONS
9.00
BSC SQ
0.30
0.25
0.18
0.60 MAX
0.60 MAX
64
49
48
PIN 1
INDICATOR
EXPOSED
PADDLE
4.9 MM SQ
8.75
BSC SQ
TOP
VIEW
1
*4.85
4.70 SQ
4.55
(BOTTOM VIEW)
0.50
0.40
0.30
1.00
0.85
0.80
12° MAX
33
32
16
17
7.50
REF
0.80 MAX
0.65 TYP
0.05 MAX
0.02 NOM
SEATING
PLANE
0.50 BSC
PIN 1
INDICATOR
THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY
OF THE SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO
THE GROUND PLANE.
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 69. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-1)
Dimensions shown in millimeters
www.BDTIC.com/ADI
ORDERING GUIDE
Model
AD8335ACPZ 1
AD8335ACPZ-REEL1
AD8335ACPZ-REEL71
AD8335-EVALZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Z = RoHS Compliant Part.
©2004–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04976-0-8/08(A)
Rev. A | Page 28 of 28
Package Option
CP-64-1
CP-64-1
CP-64-1