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a AN-534 APPLICATION NOTE One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106 • 781/329-4700 • World Wide Web Site: http://www.analog.com Adding HART® Capability to the AD421, Loop-Powered 4 mA–20 mA DAC Using the 20C15* HART Modem by Albert O’Grady INTRODUCTION The AD421 is a complete, loop-powered, digital to 4 mA–20 mA converter designed to meet the needs of smart transmitter manufacturers in the industrial control industry. It provides a high precision, fully integrated, low cost solution in a compact 16-lead package and is ideal for extending the resolution of smart 4 mA– 20 mA transmitters at very low cost. The HART (Highway Addressable Remote Transducer) protocol is widely accepted in the industry as the standard for digitally enhanced 4 mA–20 mA communication with smart field instruments. This protocol makes use of the Bell 202 Frequency Shift Keying (FSK) standard to superimpose digital signals at a low level on the 4 mA–20 mA analog signal. This allows two-way communication to take place and makes it possible for additional information beyond just the normal process variable to be communicated to/from a smart field instrument. The SYM20C15 from Symbios Logic is designed to allow the user implement a HART-compliant physical layer. This device APPROX 1 0.5mA implements the necessary modulation, demodulation, carrier detection, waveshaping and bandpass filtering to implement the protocol on-chip. The HART protocol communicates without interrupting the 4 mA–20 mA signal and allows a host application (master) to get two or more digital updates per second from a field device. As the digital FSK signal is phase continuous, there is no interference with the 4 mA–20 mA signal. Two different frequencies, 1200 Hz and 2200 Hz respectively, are used to represent binary 1 and 0 as shown in Figure 1. These tones are superimposed on the dc signal at a low level with the average value of the sine wave signal being zero. Therefore, no dc component is added to the existing 4 mA–20 mA signal regardless of the digital data being sent over the line. Consequently, existing analog instruments continue to work in systems that apply HART; as the low-pass filtering present removes the digital signal. A single-pole 10 Hz low-pass filter effectively reduces the communication signal to a ripple of about ±0.01% of the full scale signal. Figure 2 shows a block diagram of a field instrument that uses the HART protocol. MEMORY SENSORS APPROX 2 0.5mA 1200Hz "1" A/D CONVERTER D/A CONVERTER 4mA TO 20mA MEASUREMENT CIRCUIT COMMUNICATION SYSTEM 2200Hz "0" Figure 1. Digital Transmission Using the HART Protocol MICROPROCESSOR Figure 2. Smart and Intelligent Field Instrument This application note deals primarily with the interface between the AD421 loop-powered 4 mA–20 mA DAC and the 20C15 HART modem and the necessary steps required to implement a HART-compliant instrument. *20C15 is available from Symbios Logic, Telephone No. (408) 433-8000. HART is a registered trademark of the HART Communication Foundation. www.BDTIC.com/ADI AN-534 AD421 Current Control Circuitry The AD421 contains a 16-bit sigma-delta DAC to convert the digital information loaded to the input latch into a current. The sigma-delta architecture is particularly useful for the relatively low bandwidth requirements of the industrial control environment because of its inherent monotonicity at high resolution. The AD421 guarantees monotonicity to the 16-bit level. Selecting Coupling Capacitor C C The HART output signal on the loop is 1 mA p-p and is generated in the AD421 by applying a suitable voltage signal to the C3 pin as mentioned earlier. HART applications accommodate both digital and analog communications, therefore it is very important that the digital HART signal injected onto the loop not interfere with the mean value of the analog loop current. The HART signal is ac-coupled to avoid introducing errors. Capacitors CC and C3 attenuate the HART voltage signal from the 20C15 to ensure that a HART signal of 1 mA p-p gets onto the loop during HART transmissions. The signal appearing at the C3 pin is applied across a 40 kΩ resistor and twice this signal is forced across the 40 Ω loop current sense resistor. Therefore, a 20 mV signal is required at the C3 pin to ensure a 1 mA current on the loop. The following attenuation factor is required on the HART input signal VH from the 20C15. The sigma-delta DAC on the part consists of a second order modulator followed by a continuous time filter. The single bit stream from the modulator controls a switched current source. This current source is then filtered by three resistor capacitor filter sections. The resistors for each of the filter sections are on-chip while the capacitors should be connected to the C1, C2 and C3 pins. To meet the specified HART physical layer low pass characteristic of a double pole with cutoff frequency of 25 Hz, capacitor C1 should be 0.01 µF, C2 = 0.5 µF and C3 = 0.16 µF. The HART signal is coupled into the loop through capacitor CC at node C3. Capacitors CC and C3 ensure a flat response at the HART frequencies of 1200 Hz and 2200 Hz. Figure 3 shows a block diagram of the current control circuitry within the AD421. AD421 SIGMADELTA DAC 4kV 12.5kV Attenuation Factor: 20 mV/VH = CC /(CC + C3). ∴ CC = (20E–3 × C3)/(VH-20E–3). Filter Time Constant = (CC + C3) × (40E + 3). As an example, if the HART input signal applied to CC is 500 mV p-p, and the filter time constant is to correspond to 25 Hz, the HART signal band requirement, then CC should be approximately 6.2 nF. AD421-20C15 Interface Figure 4 shows an evaluation circuit for the AD42120C15 interface, which shows the required components to implement the transmit interface. The external transistor Q1 (DN25D depletion mode MOSFET), in association with the internal op amp and voltage reference on the AD421, form a voltage regulator that regulates the supply voltage for the AD421 from the loop voltage. LK1, LK2 and LK3 allow this regulated voltage to be programmed to either 5 V, 3.3 V or 3 V. The external pass transistor (Q2) is added to reduce the power loading on the depletion mode MOSFET Q1. BOOST 40kV 80kV 40V LOOP RTN LOOP(2) C1 C2 C3 C1 0.01mF C2 0.5mF C3 0.16mF CC FROM 20C15 Figure 3. AD421 Current Control Circuitry The DAC output current drives the second section, an operational amplifier and NPN transistor which acts as a current amplifier to set the current flowing from the LOOP RTN pin. The base drive to the NPN transistor servos the voltage across the 40 Ω sense resistor to equal the voltage across the 80 kΩ resistor connected between the DAC output and loop return. The MOSFET supplies the quiescent current for the AD421. The BOOST pin on the AD421 sinks the necessary current through the pass transistor Q2 from the loop so that the current flowing into BOOST, plus the quiescent current flowing into COM, equals the programmed loop current. U3 shows the 20C15 HART modem and its associated circuitry required to implement the HART interface. The coupling capacitor C15 couples the HART signal onto the analog 4 mA–20 mA loop at the C3 pin of the AD421. www.BDTIC.com/ADI –2– AN-534 LOOP PLUS J2-1 28F0195-100 L1 VCC Q1 D G C10 0.01mF REFOUT1 C B VCC E3297a–1–6/99 S C11 0.1mF Q2 BC548 C5 4.7mF E REFOUT2 BOOST C6 0.01mF LK3 CENTRONICS CONNECTOR R2 10kV J1-3 U2A COMP LV DRIVE C7 2.2mF LK1 LATCH 74HC4050 R3 10kV J1-5 C1 R1 1kV U1 AD421 U2B 5 C8 0.1mF C1 0.01mF 2 3 REFIN C4 4.7mF LK2 4 C2 0.5mF CLOCK C2 C9 1nF 74HC4050 R4 10kV J1-9 C3 0.16mF U2C 7 6 DATA 74HC4050 C3 COM LOOP RTN J1-18 LOOP MINUS J2-2 L2 J1-19 J1-20 28F0195-100 R14 732kV J1-21 J1-22 J1-23 J1-25 C19 220pF C15 6.2nF R13 825kV C21 1000pF C20 1000pF R12 216kV R15 453kV R10 787kV 10 26 27 R18 1MV 24 R17 1MV 23 6 18 17 16 IRXAC ORXAF IRXA OTXA IAREF ORXD ICDREF OCD ITXD 15 LK4 LK5 R16 402kV VCC 11 R9 10kV 12 R8 14.7kV U4 AD589 C18 0.01mF R7 200kV U3 20C15 OXTL 19 INRTS VDD IXTL 22 VCC R11 3MV C22 470pF 20 XTAL1 460kHz C16 220pF C17 220pF VDDA OCBIAS 13 21 14 VSS 9 8 7 5 1 R6 500kV Figure 4. AD421-20C15 Interface Circuit Diagram www.BDTIC.com/ADI –3– PRINTED IN U.S.A. J1-24