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XA95144XL Automotive CPLD
DS600 (v1.1) April 3, 2007
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Features
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AEC-Q100 device qualification and full PPAP support
available in I-grade.
Guaranteed to meet full electrical specifications over
TA = -40° C to +85° C (I-grade)
15.5 ns pin-to-pin logic delays
System frequency up to 64.5 MHz
144 macrocells with 3,200 usable gates
Available in the following package
- 144-CSP (117 user I/O pins)
- Pb-free package only
Optimized for high-performance 3.3V systems
- Low power operation
- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
- 3.3V or 2.5V output capability
- Advanced 0.35 micron feature size CMOS
Fast FLASH™ technology
Advanced system features
- In-system programmable
- Superior pin-locking and routability with
Fast CONNECT™ II switch matrix
- Extra wide 54-input Function Blocks
- Up to 90 product-terms per macrocell with
individual product-term allocation
- Local clock inversion with three global and one
product-term clocks
- Individual output enable per output pin with local
inversion
- Input hysteresis on all user and boundary-scan pin
inputs
- Bus-hold circuitry on all user pin inputs
- Full IEEE Standard 1149.1 boundary-scan (JTAG)
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
- Endurance exceeding 10,000 program/erase
cycles
- 20 year data retention
- ESD protection exceeding 2,000V
Product Specification
gates with propagation delays of 15.5 ns. See Figure 2 for
overview.
Power Estimation
Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output
loading. Each macrocell in an XA9500XL automotive device
must be configured for low-power mode (default mode for
XA9500XL devices). In addition, unused product-terms and
macrocells are automatically deactivated by the software to
further conserve power.
For a general estimate of ICC, the following equation may be
used:
ICC(mA) = MC(0.052*PT + 0.272) + 0.04 * MCTOG * MC * f
where:
MC = # macrocells
PT = average number product terms per macrocell
f = maximum clock frequency
MCTOG = average % of flip-flops toggling per clock
(~12%)
This calculation was derived from laboratory measurements
of an XA9500XL part filled with 16-bit counters and allowing
a single output (the LSB) to be enabled. The actual ICC
value varies with the design application and should be verified during normal system operation. Figure 1 shows the
above estimation in a graphical form. For a more detailed
discussion of power consumption in this device, see Xilinx
application note XAPP114, “Understanding XC9500XL
CPLD Power.”
150
Typical ICC (mA)
R
100
64.4 MHz
50
0
50
Clock Frequency (MHz)
100
DS600_01_121106
Figure 1: Typical ICC vs. Frequency for XA95144XL
WARNING: Programming temperature range of
TA = 0° C to +70° C
Description
The XA95144XL is a 3.3V CPLD targeted for high-performance, low-voltage automotive applications. It is comprised
of eight 54V18 Function Blocks, providing 3,200 usable
© 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS600 (v1.1) April 3, 2007
Product Specification
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1
XA95144XL Automotive CPLD
R
3
JTAG Port
1
JTAG
Controller
In-System Programming Controller
54
Function
Block 1
18
I/O
Macrocells
1 to 18
I/O
Fast CONNECT II Switch Matrix
I/O
I/O
I/O
Blocks
I/O
I/O
I/O
54
Function
Block 2
18
Macrocells
1 to 18
54
Function
Block 3
18
Macrocells
1 to 18
I/O
3
I/O/GCK
54
1
Function
Block 4
18
I/O/GSR
4
Macrocells
1 to 18
I/O/GTS
54
Function
Block 8
18
Macrocells
1 to 18
DS056_02_101300
Figure 2: XA95144XL Architecture
Function Block outputs (indicated by the bold line) drive the I/O Blocks directly.
2
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DS600 (v1.1) April 3, 2007
Product Specification
XA95144XL Automotive CPLD
R
Absolute Maximum Ratings(1,3)
Symbol
Description
Value
Units
VCC
Supply voltage relative to GND
–0.5 to 4.0
V
VIN
Input voltage relative to GND(2)
–0.5 to 5.5
V
–0.5 to 5.5
V
–65 to +150
oC
+125
oC
output(2)
VTS
Voltage applied to 3-state
TSTG
Storage temperature (ambient)(4)
TJ
Junction temperature
Notes:
1. All automotive customers are required to set the Macrocell Power Setting to low, and set Logic Optimization to density.
2. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0 V or overshoot to +7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. External I/O voltage may not exceed VCCINT by 4.0V.
3. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
4. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb-free
packages, see XAPP427.
Recommended Operation Conditions
Symbol
TA
VCCINT
VCCIO
Min
Max
Units
Ambient temperature
Parameter
–40
+85
oC
Supply voltage for internal logic and input buffers
3.0
3.6
V
Supply voltage for output drivers for 3.3V operation
3.0
3.6
V
Supply voltage for output drivers for 2.5V operation
2.3
2.7
V
VIL
Low-level input voltage
0
0.80
V
VIH
High-level input voltage
2.0
5.5
V
VO
Output voltage
0
VCCIO
V
Quality and Reliability Characteristics
Symbol
Parameter
Min
Max
Units
20
-
Years
TDR
Data Retention
NPE
Program/Erase Cycles (Endurance) @ TA = 70°
10,000
-
Cycles
VESD
Electrostatic Discharge (ESD)
2,000
-
Volts
DC Characteristic Over Recommended Operating Conditions
Symbol
Parameter
Test Conditions
Min
Max
Units
-
V
Output high voltage for 3.3V outputs
IOH = –4.0 mA
2.4
Output high voltage for 2.5V outputs
IOH = –500 μA
90% VCCIO
-
V
Output low voltage for 3.3V outputs
IOL = 8.0 mA
-
0.4
V
Output low voltage for 2.5V outputs
IOL = 500 μA
-
0.4
V
IIL
Input leakage current
VCC = Max; VIN = GND or VCC
-
±10
μA
IIH
I/O high-Z leakage current
VCC = Max; VIN = GND or VCC
-
±10
μA
VOH
VOL
DS600 (v1.1) April 3, 2007
Product Specification
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3
XA95144XL Automotive CPLD
Symbol
R
Parameter
Test Conditions
I/O high-Z leakage current
IIH
Min
Max
Units
VCC = Max; VCCIO = Max;
VIN = GND or 3.6V
-
±10
μA
VCC Min < VIN < 5.5V
-
±50
μA
-
10
pF
CIN
I/O capacitance
VIN = GND; f = 1.0 MHz
ICC
Operating supply current
(low power mode, active)
VIN = GND, No load; f = 1.0 MHz
45 (Typical)
mA
AC Characteristics
XA95144XL-15
Symbol
Parameter
Min
Max
Units
-
15.5
ns
12.0
-
ns
TPD
I/O to output valid
TSU
I/O setup time before GCK
TH
I/O hold time after GCK
0
-
ns
GCK to output valid
-
5.8
ns
fSYSTEM
Multiple FB internal operating frequency
-
64.5
MHz
TPSU
I/O setup time before p-term clock input
7.6
-
ns
TPH
I/O hold time after p-term clock input
0.0
-
ns
TCO
TPCO
P-term clock output valid
-
10.2
ns
TOE
GTS to output valid
-
7.0
ns
TOD
GTS to output disable
-
7.0
ns
TPOE
Product term OE to output enabled
-
11.0
ns
TPOD
Product term OE to output disabled
-
11.0
ns
TAO
GSR to output valid
-
14.5
ns
TPAO
P-term S/R to output valid
-
15.3
ns
TWLH
GCK pulse width (High or Low)
4.5
-
ns
Asynchronous preset/reset pulse width (High or Low)
7.0
-
ns
P-term clock pulse width (High or Low)
7.0
-
ns
TSUEC
Clock enable setup
6.5
-
ns
THEC
Clock enable hold
0
-
ns
TAPRPW
TPLH
VTEST
R1
Output Type
VCCIO
VTEST
R1
R2
CL
3.3V
3.3V
320 Ω
360 Ω
35 pF
2.5V
2.5V
250 Ω
660 Ω
35 pF
Device Output
R2
CL
DS058_03_081500
Figure 3: AC Load Circuit
4
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DS600 (v1.1) April 3, 2007
Product Specification
XA95144XL Automotive CPLD
R
Internal Timing Parameters
XA95144XL-15
Symbol
Parameter
Min
Max
Units
Buffer Delays
TIN
Input buffer delay
-
3.5
ns
TGCK
GCK buffer delay
-
1.8
ns
TGSR
GSR buffer delay
-
4.5
ns
TGTS
GTS buffer delay
-
7.0
ns
TOUT
Output buffer delay
-
3.0
ns
TEN
Output buffer enable/disable delay
-
0
ns
Product Term Control Delays
TPTCK
Product term clock delay
-
2.7
ns
TPTSR
Product term set/reset delay
-
1.8
ns
TPTTS
Product term 3-state delay
-
7.5
ns
-
1.7
ns
Internal Register and Combinatorial Delays
TPDI
Combinatorial logic propagation delay
TSUI
Register setup time
3.0
-
ns
THI
Register hold time
3.5
-
ns
TECSU
Register clock enable setup time
3.0
-
ns
TECHO
Register clock enable hold time
3.5
-
ns
TCOI
Register clock to output valid time
-
1.0
ns
TAOI
Register async. S/R to output delay
-
7.0
ns
TRAI
Register async. S/R recover before clock
10.0
-
ns
TLOGI
Internal logic delay
-
7.3
ns
Fast CONNECT II feedback delay
-
4.2
ns
Incremental product term allocator delay
-
1.0
ns
Slew-rate limited delay
-
4.5
ns
Feedback Delays
TF
Time Adders
TPTA
TSLEW
DS600 (v1.1) April 3, 2007
Product Specification
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5
XA95144XL Automotive CPLD
R
XA95144XL I/O Pins
Function
Block
Macrocell
CSG144
BScan
Order
Function
Block
Macrocell
CSG144
BScan
Order
1
1
H3
429
3
1
M3
321
L1(1)
318
1
2
F1
426
3
2(1)
1
3
G2
423
3
3
K4
315
1
4
J1
420
3
4
N4
312
1
5
G3
417
3
5
L2
309
1
6
G4
414
3
6
L3
306
1
7
-
411
3
7
L5
303
N2(1)
300
1
8
H1
408
3
8(1)
1
9
H2
405
3
9
N3
297
1
10
K3
402
3
10
N5
294
1
11
H4
399
3
11
M4
291
1
12
J2
396
3
12
K5
288
1
13
-
393
3
13
-
285
1
14
J3
390
3
14
K6
282
1
15
J4
387
3
15
L6
279
1
16
M1
384
3
16
-
276
1
17(1)
K2(1)
381
3
17
M6
273
1
18
-
378
3
18
-
270
2
1
C3
375
4
1
C9
267
2
2(1)
A2(1)
372
4
2
A7
264
2
3
-
369
4
3
A5
261
2
4
C1
366
4
4
-
258
2
5(1)
B1(1)
363
4
5
D7
255
2
6(1)
C2(1)
360
4
6
A6
252
2
7
-
357
4
7
-
249
2
8(1)
D4(1)
354
4
8
B6
246
2
9(1)
D3(1)
351
4
9
C6
243
2
10
D2
348
4
10
C5
240
2
11
E4
345
4
11
D6
237
2
12
E3
342
4
12
B5
234
2
13
E1
339
4
13
A4
231
2
14
E2
336
4
14
D5
228
2
15
F4
333
4
15
B4
225
2
16
F3
330
4
16
C4
222
2
17
F2
327
4
17
A3
219
2
18
-
324
4
18
-
216
Notes:
1. Global control pin.
6
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DS600 (v1.1) April 3, 2007
Product Specification
XA95144XL Automotive CPLD
R
XA95144XL (Continued)
Function
Block
Macrocell
CS144
BScan
Order
Function
Block
Macrocell
CS144
BScan
Order
5
1
-
213
7
1
-
105
5
2
N6
210
7
2
N12
102
5
3
L8
207
7
3
L12
99
5
4
-
204
7
4
-
96
5
5
M7
201
7
5
M13
93
5
6
N7
198
7
6
L13
90
5
7
M10
195
7
7
K10
87
5
8
K7
192
7
8
K11
84
5
9
N8
189
7
9
K13
81
5
10
N11
186
7
10
K12
78
5
11
M8
183
7
11
J11
75
5
12
K8
180
7
12
H10
72
5
13
L11
177
7
13
J10
69
5
14
N9
174
7
14
H11
66
5
15
K9
171
7
15
H12
63
5
16
-
168
7
16
J12
60
5
17
M11
165
7
17
H13
57
5
18
-
162
7
18
-
54
6
1
-
159
8
1
-
51
6
2
C11
156
8
2
G11
48
6
3
-
153
8
3
F11
45
6
4
B11
150
8
4
E13
42
6
5
A12
147
8
5
G10
39
6
6
A11
144
8
6
F13
36
6
7
-
141
8
7
-
33
6
8
D10
138
8
8
F12
30
6
9
A10
135
8
9
F10
27
6
10
B10
132
8
10
D13
24
6
11
B9
129
8
11
E12
21
6
12
A9
126
8
12
E10
18
6
13
-
123
8
13
D11
15
6
14
D8
120
8
14
D12
12
6
15
A8
117
8
15
C13
9
6
16
D9
114
8
16
B13
6
6
17
B7
111
8
17
C12
3
6
18
-
108
8
18
-
0
DS600 (v1.1) April 3, 2007
Product Specification
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7
XA95144XL Automotive CPLD
R
XA95144XL Global, JTAG and Power Pins
8
Pin Type
CSG144
I/O/GCK1
K2
I/O/GCK2
L1
I/O/GCK3
N2
I/O/GTS1
D4
I/O/GTS2
D3
I/O/GTS3
B1
I/O/GTS4
C2
I/O/GSR
A2
TCK
L10
TDI
L9
TDO
C8
TMS
N10
VCCINT 3.3V
B3, D1, J13, L4
VCCIO 2.5V/3.3V
A1, A13, C7, L7, N1, N13
GND
B2, B8, B12, C10, E11, G1, G12, G13, K1, M2, M5, M9, M12
No Connects
–
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DS600 (v1.1) April 3, 2007
Product Specification
XA95144XL Automotive CPLD
R
Device Part Marking and Ordering Combination Information.
R
XA95144XL
CSG144
Device Type
Package
This line not
related to device
part number
15I
Speed
Operating Range
1
Sample package with part marking.
Device Ordering and
Part Marking Number
Speed
(pin-to-pin
delay)
XA95144XL-15CSG144I
15.5 ns
Pkg.
Symbol
No. of
Pins
CSG144 144-ball
Package Type
Operating
Range(1)
Chip Scale Package (CSP); Pb-free
I
Notes:
1. I-Grade: TA = –40° to +85°C
Example:
XA95144XL -15 CS
G
144
I
Device
Speed Grade
Package Type
Pb-Free
Number of Pins
Temperature Range
XA9500XL Automotive Requirements and Recommendations
Requirements
The following requirements are for all automotive applications:
1. All automotive customers are required to keep the
Macrocell Power selection set to low, and the Logic
Optimization set to density when designing with ISE
software. These are the default settings when
XA9500XL devices are selected for design. These
settings are found on the Process Properties page for
Implement Design. See the ISE Online Help for details
on these properties.
2. Use a monotonic, fast ramp power supply to power up
XA9500XL . A VCC ramp time of less than 1 ms is
required.
3. Do not float I/O pins during device operation. Floating
I/O pins can increase ICC as input buffers will draw
1-2 mA per floating input. In addition, when I/O pins are
floated, noise can propagate to the center of the CPLD.
DS600 (v1.1) April 3, 2007
Product Specification
I/O pins should be appropriately terminated with
keeper/bus-hold. Unused I/Os can also be configured
as CGND (programmable GND).
4. Do not drive I/O pins without VCC/VCCIO powered.
5. Sink current when driving LEDs. Because all Xilinx
CPLDs have N-channel pull-down transistors on
outputs, it is required that an LED anode is sourced
through a resistor externally to VCC. Consequently, this
will give the brightest solution.
6. Avoid external pull-down resistors. Always use external
pull-up resistors if external termination is required. This
is because the XA9500XL Automotive CPLD, which
includes some I/O driving circuits beyond the input and
output buffers, may have contention with external
pull-down resistors, and, consequently, the I/O will not
switch as expected.
7. Do not drive I/Os pins above the VCCIO assigned to its
I/O bank.
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9
XA95144XL Automotive CPLD
R
a. The current flow can go into VCCIO and affect a user
voltage regulator.
b. It can also increase undesired leakage current
associated with the device.
c.
If done for too long, it can reduce the life of the
device.
8. Do not rely on the I/O states before the CPLD
configures.
9. Use a voltage regulator which can provide sufficient
current during device power up. As a rule of thumb, the
regulator needs to provide at least three times the peak
current while powering up a CPLD in order to guarantee
the CPLD can configure successfully.
10. Ensure external JTAG terminations for TMS, TCK, TDI,
TDO comply with IEEE 1149.1. All Xilinx CPLDs have
internal weak pull-ups of ~50 kΩ on TDI, TMS, and
TCK.
11. Attach all CPLD VCC and GND pins in order to have
necessary power and ground supplies around the
CPLD.
12. Decouple all VCC and VCCIO pins with capacitors of
0.01 μF and 0.1 μF closest to the pins for each
VCC/VCCIO-GND pair.
Recommendations
The following recommendations are for all automotive applications.
1. Use strict synchronous design (only one clocking event)
if possible. A synchronous system is more robust than
an asynchronous one.
2. Include JTAG stakes on the PCB. JTAG stakes can be
used to test the part on the PCB. They add benefit in
reprogramming part on the PCB, inspecting chip
10
internals with INTEST, identifying stuck pins, and
inspecting programming patterns (if not secured).
3. XA9500XL Automotive CPLDs work with any power
sequence, but it is preferable to power the VCCI
(internal VCC) before the VCCIO for the applications in
which any glitches from device I/Os are unwanted.
4. Do not disregard report file warnings. Software
identifies potential problems when compiling, so the
report file is worth inspecting to see exactly how your
design is mapped onto the logic.
5. Understand the Timing Report. This report file provides
a speed summary along with warnings. Read the timing
file (*.tim) carefully. Analyze key signal chains to
determine limits to given clock(s) based on logic
analysis.
6. Review Fitter Report equations. Equations can be
shown in ABEL-like format, or can also be displayed in
Verilog or VHDL formats. The Fitter Report also
includes switch settings that are very informative of
other device behaviors.
7. Let design software define pinouts if possible. Xilinx
CPLD software works best when it selects the I/O pins
and manages resources for users. It can spread signals
around and improve pin-locking. If users must define
pins, plan resources in advance.
8. Perform a post-fit simulation for all speeds to identify
any possible problems (such as race conditions) that
might occur when fast-speed silicon is used instead of
slow-speed silicon.
9. Distribute SSOs (Simultaneously Switching Outputs)
evenly around the CPLD to reduce switching noise.
10. Terminate high speed outputs to eliminate noise caused
by very fast rising/falling edges.
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Product Specification
XA95144XL Automotive CPLD
R
Warranty Disclaimer
THIS WARRANTY DOES NOT EXTEND TO ANY IMPLEMENTATION IN AN APPLICATION OR ENVIRONMENT THAT IS
NOT CONTAINED WITHIN XILINX SPECIFICATIONS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE
NOT WARRANTED FOR USE IN THE DEPLOYMENT OF AIRBAGS. FURTHER, PRODUCTS ARE NOT WARRANTED
FOR USE IN APPLICATIONS THAT AFFECT CONTROL OF THE VEHICLE UNLESS THERE IS A FAIL-SAFE OR
REDUNDANCY FEATURE AND ALSO A WARNING SIGNAL TO THE OPERATOR OF THE VEHICLE UPON FAILURE.
USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE
LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY.
Further Reading
The following Xilinx links go to relevant XC9500XL CPLD documentation, including XAPP111, Using the XC9500XL Timing
Model, and XAPP784, Bulletproof CPLD Design Practices. Simply click on the link and scroll down.
Data Sheets, Application Notes, and White Papers.
Packaging
Revision History
The following table shows the revision history for this document.
Date
Version
01/12/07
1.0
Initial Release.
04/03/07
1.1
Add programming temperature range warning on page 1.
DS600 (v1.1) April 3, 2007
Product Specification
Revision
www.BDTIC.com/XILINX
www.xilinx.com
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