Download FDMS86252 Shielded Gate N-Channel

FDMS86252
N-Channel Shielded Gate PowerTrench® MOSFET
150 V, 16 A, 51 mΩ
Features
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized for the on-state resistance and yet maintain superior
switching performance.
„ Shielded Gate MOSFET Technology
„ Max rDS(on) = 51 mΩ at VGS = 10 V, ID = 4.6 A
„ Max rDS(on) = 70 mΩ at VGS = 6 V, ID = 3.9 A
„ Advanced package and silicon combination for low rDS(on) and
high efficiency
„ MSL1 robust package design
Application
„ 100% UIL tested
„ DC-DC Conversion
„ RoHS Compliant
Bottom
Top
Pin 1
S
D
D
D
S
S
G
D
S
D
S
D
S
D
G
D
Power 56
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current -Continuous
TC = 25 °C
-Continuous
TA = 25 °C
ID
TJ, TSTG
±20
V
(Note 1a)
4.6
A
20
Single Pulse Avalanche Energy
PD
Units
V
16
-Pulsed
EAS
Ratings
150
(Note 3)
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
50
69
(Note 1a)
Operating and Storage Junction Temperature Range
2.5
-55 to +150
mJ
W
°C
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case
RθJA
Thermal Resistance, Junction to Ambient
1.8
(Note 1a)
50
°C/W
Package Marking and Ordering Information
Device Marking
FDMS86252
Device
FDMS86252
©2010 Fairchild Semiconductor Corporation
FDMS86252 Rev.C2
Package
Power 56
1
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
FDMS86252 N-Channel Shielded Gate PowerTrench® MOSFET
May 2014
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 120 V, VGS = 0 V
1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
±100
nA
4.0
V
150
V
106
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
2.0
2.8
-9
mV/°C
VGS = 10 V, ID = 4.6 A
43.9
51
VGS = 6 V, ID = 3.9 A
50.5
70
VGS = 10 V, ID = 4.6 A,
TJ = 125 °C
83
96
VDS = 10 V, ID = 4.6 A
15
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
VDS = 75 V, VGS = 0 V,
f = 1 MHz
0.1
678
905
pF
74
115
pF
4.3
10
pF
0.4
1.8
Ω
ns
Switching Characteristics
td(on)
Turn-On Delay Time
7.7
16
tr
Rise Time
2.3
10
ns
td(off)
Turn-Off Delay Time
15
27
ns
VDD = 75 V, ID = 4.6 A,
VGS = 10 V, RGEN = 6 Ω
tf
Fall Time
Qg
Total Gate Charge
VGS = 0 V to 10 V
Qg
Total Gate Charge
VGS = 0 V to 5 V
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
VDD = 75 V,
ID = 4.6 A
3.2
10
ns
11
15
nC
6.1
8.6
nC
2.8
nC
2.4
nC
Drain-Source Diode Characteristics
VSD
Source-Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 2 A
(Note 2)
0.75
1.2
VGS = 0 V, IS = 4.6 A
(Note 2)
0.80
1.3
IF = 4.6 A, di/dt = 100 A/μs
V
56
90
ns
61
98
nC
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
a. 50 °C/W when mounted on a
1 in2 pad of 2 oz copper.
b. 125 °C/W when mounted on a
minimum pad of 2 oz copper.
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Starting TJ = 25 °C, L = 1 mH, IAS = 10 A, VDD = 135 V, VGS = 10 V.
©2010 Fairchild Semiconductor Corporation
FDMS86252 Rev.C2
2
www.fairchildsemi.com
FDMS86252 N-Channel Shielded Gate PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted
5
VGS = 10 V
VGS = 6 V
VGS = 5.5 V
15
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
20
VGS = 5 V
10
VGS = 4.5 V
5
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0
1
2
3
4
4
VGS = 5 V
3
2
VGS = 5.5 V
1
0
5
0
5
10
15
20
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
2.4
200
ID = 4.6 A
VGS = 10 V
2.2
2.0
SOURCE ON-RESISTANCE (mΩ)
ID = 4.6 A
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
150
1.8
rDS(on), DRAIN TO
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
VGS = 10 V
VGS = 6 V
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.6
1.4
1.2
1.0
0.8
0.6
0.4
-75
-50
100
IS, REVERSE DRAIN CURRENT (A)
VDS = 5 V
TJ = 150 oC
10
TJ = 25 oC
5
TJ = -55 oC
0
5
6
7
8
9
20
10
1
TJ = 150 oC
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.001
0.0
6
VGS = 0 V
0.2
0.4
0.6
0.8
1.0
VGS, GATE TO SOURCE VOLTAGE (V)
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
©2010 Fairchild Semiconductor Corporation
FDMS86252 Rev.C2
10
Figure 4. On-Resistance vs Gate to
Source Voltage
15
4
5
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
3
TJ = 25 oC
4
20
2
TJ = 125 oC
50
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs Junction Temperature
ID, DRAIN CURRENT (A)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 4.5 V
3
1.2
www.fairchildsemi.com
FDMS86252 N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
1000
ID = 4.6 A
Ciss
8
VDD = 75 V
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
6
VDD = 50 V
VDD = 100 V
4
100
Coss
Crss
10
2
f = 1 MHz
VGS = 0 V
0
0
3
6
9
3
0.1
12
Figure 7. Gate Charge Characteristics
10
100
Figure 8. Capacitance vs Drain
to Source Voltage
25
ID, DRAIN CURRENT (A)
20
IAS, AVALANCHE CURRENT (A)
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
TJ = 25 oC
10
TJ = 100 oC
TJ = 125 oC
20
15
VGS = 10 V
10
Limited by Package
VGS = 6 V
5
o
RθJC = 1.8 C/W
1
0.001
0.01
0.1
1
0
25
10
P(PK), PEAK TRANSIENT POWER (W)
ID, DRAIN CURRENT (A)
10
100 μs
1 ms
1
10 ms
THIS AREA IS
LIMITED BY rDS(on)
100 ms
1s
SINGLE PULSE
TJ = MAX RATED
10 s
RθJA = 125 oC/W
DC
TA = 25 oC
0.001
0.01
0.1
1
10
100
800
125
150
2000
1000
VGS = 10 V
100
10
SINGLE PULSE
RθJA = 125 oC/W
1 TA = 25 oC
0.5
-4
-3
-2
10
10
10
-1
10
1
100
10
1000
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
©2010 Fairchild Semiconductor Corporation
FDMS86252 Rev.C2
100
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
50
0.01
75
o
Figure 9. Unclamped Inductive
Switching Capability
0.1
50
TC, CASE TEMPERATURE ( C)
tAV, TIME IN AVALANCHE (ms)
Figure 12. Single Pulse Maximum
Power Dissipation
4
www.fairchildsemi.com
FDMS86252 N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
0.1
0.01
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
ZθJA(t) = r(t) x RθJA
SINGLE PULSE
0.001
0.0001
-4
10
RθJA = 125 °C/W
Peak TJ = PDM x ZθJA(t) + TA
Duty Cycle, D = t1 / t2
-3
10
-2
10
-1
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2010 Fairchild Semiconductor Corporation
FDMS86252 Rev.C2
5
www.fairchildsemi.com
FDMS86252 N-Channel Shielded Gate PowerTrench® MOSFET
Typical Characteristics TJ = 25 °C unless otherwise noted
FDMS86252 N-Channel Shielded Gate PowerTrench® MOSFET
Dimensional Outline and Pad Layout
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/package/packageDetails.html?id=PN_PQOAM-C08
©2010 Fairchild Semiconductor Corporation
FDMS86252 Rev.C2
6
www.fairchildsemi.com
tm
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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THEREIN, WHICH COVERS THESE PRODUCTS.
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Product Status
Definition
Advance Information
Formative / In Design
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Preliminary
First Production
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
No Identification Needed
Full Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Obsolete
Not In Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I68
©2010 Fairchild Semiconductor Corporation
FDMS86252 Rev.C2
7
www.fairchildsemi.com
FDMS86252 N-Channel Shielded Gate PowerTrench® MOSFET
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