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Virtex-II Pro and
VxWorks for
Embedded Solutions
Systems Engineering Group
Embedded System
Development
Embedded Solutions
• Key components of Embedded systems development
–
–
–
–
–
–
–
Integrated development environment (IDE: example TornadoII)
Real Time Operating System (RTOS: example VxWorks)
Board Support Package (BSP)
System Image (example VxWorks image)
Bootloader (bringing up the OS)
Dynamic Linking of software modules
Critical files and structure for embedded development
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Embedded Solutions
CF: local NV Storage
Embedded System Bus
Target
JTAG
Network
Serial
PPC Single Board Computer (SBC)
System Nodes
&
Applications / Plug in Modules
Host
Development Platform & IDE
4
Integrated Development
Environment (IDE)
• An IDE provides and enables the following:
– An Integrated Cross Development and Debug Environment for
Embedded Systems (for example Tornado II / VxWorks)
– Rapid Prototyping
•
•
•
•
Scalable Real Time OS
Application Development (Post Board Bring-Up)
Host Based Tools (Host Shell, Info Browser)
Dynamic Download
– Produces
• VxWorks System Images
• Dynamically loadable software object modules
• Bootloader
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RTOS & BSP
• Real Time Operating System - Scalability
– RTOS provides a deterministic task manager and inter-task
communication facilities for embedded application development
– Core OS functionality is abstracted from the particular target
architecture used. Thus providing a scalable system solution
across multiple platforms
• Board Support Package (BSP)- Platform independence
– The BSP is the glue logic that is used to tie the hardware to the
OS. Providing platform independence to the OS
– The platform abstraction of the BSP provides the OS with the
necessary details of the underlying hardware through standard
interface functions
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VxWorks
Real Time Kernel
• Fast and Deterministic
– Across Microprocessor families
– API consistent across
architectures
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Cl
oc
k
Sy
st
em
Intertask
Communications
rt
po
up
• Portable
t
sk en
Ta em
g
na
Ma
– You only ship what you need
y t
or en
em m
M age
Semaphores
an
M
tS
up
• Scalable
rr
te
In
– Lightweight tasking model
– Minimal time in Kernel mode
Tornado-II IDE
Workspace
Editor
Projects
Source
*.c, *.cpp
Header
*.h
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System Image
• The system image is a bootable set of core OS
functionality customized from a base BSP.
• Tornado-II Integrated Development Environment (IDE)
produces VxWorks system images.
– At compile time, the system image is defined by components
“included” or “excluded” during the system build process
• Application code may be built into the system image at
compile time
– Applications may later be upgraded using a loader that
dynamically loads and unloads software modules on top of a
running VxWorks system.
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Sy
st
em
Cl
o
SW_MOD
• A system image, based on the included set
OS functionality and built-in application
code is produced at compile time.
DYNAMICALLY
LOAD
ck
Intertask Communications
DYNAMICALLY
UNLOAD
• A running VxWorks system can be
upgraded via a dynamic linker loader
System Image
Cl
o
ck
sk nt
Ta eme
g
na
Ma
sk nt
Ta eme
g
na
Ma
Intertask Communications
y t
or en
em m
M age
an
Semaphores
M
Sy
st
em
Dynamic Linking
t
or
pp
Su
pt
rr u
te
In
rt
po
up
tS
up
rr
te
In
y t
or en
em m
M age
an
Semaphores
M
– Loads and unloads your compiled
source code, while your target is running
– This allows you test out your application
code one module at a time on top of an
existing vxWorks image.
10
SW_MOD
System Image
VxWorks Configuration
Driver selection, Tunable parameters
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Application selection
Methods of Bringing Up an
Embedded System
• Board Bring-Up
– Cable:
• Development & Debug w/ JTAG cable to deliver ELF software image
and a Debug path into Processor (WRS VisionProbe-II)
– Boot ROM
• Delivery of system image from onboard
non-volatile storage and booting VxWorks
Network
– Bootloader
NTWK
• Retrieve system image over the network
• Retrieve system image from local non-volatile
storage (eg. CF)
• Launch system image from RAM
CPU
RAM
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ROM
JTAG
Embedded System Upgrade
• Loading and Running an Application
– Local access of application in non-volatile storage
– Remote access of application over Network
– Run RAM resident application
Network
NTWK
CPU
RAM
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ROM
JTAG
Embedded Development Files
• Expected files for embedded development
– VxWorks System Image ( ELF)
– Dynamically Linkable Software Modules ( ELF )
– Bootloader ( ELF )
(ELF - Executable and Linkable Format)
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Directory Structure
• In summary there are three
main file types we have
discussed that will be needed
for our embedded solution
development
– System image
– Software module
– Bootloader
File System
VXWORKS
(Software)
IMAGES
MODULES
(ELF Format)
(ELF Format)
vxworks3
vxworks2
vxworks1
bootloader
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sw_mod2.out
sw_mod1.out
VxWorks
Virtex-II Pro &
System ACE-CF
Evolution of
Embedded Solutions
CF: local NV Storage
Embedded System Bus
Target
JTAG
Network
Serial
PPC Single Board Computer (SBC)
System Nodes
&
Applications / Plug in Modules
Host
Development Platform & IDE
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Evolution to Virtex-II Pro
(Scalable System Solution)
PPC405GP SBC
Host
Development
Platform
PPC Single Board Computers (SBCs)
Backplane
and
Embedded System Bus
PPC750 SBC
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Embedded Development Platform
(Rapid Prototyping)
ML3
ML2
PPC405 SBCs
ML1
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ML300 & Virtex-II Pro
Virtex-II Pro & System ACE-CF
(Evolution of Embedded Solutions)
Host
JTAG
Development
and Debug
Network
JTAG
TST
Serial
CF
JTAG
CFG
Embedded
Microprocessor
Serial
MPU
Reset
VT100
7
0
1
6
2
5
4
3
CFG
ADDR
GPIO
System ACE-CF Solution
• Board Bring-Up
– Cable via ACE-CF JTAG TST port:
• Development & Debug w/ JTAG cable to deliver ELF software image
and a Debug path into Processor (WRS VisionProbe-II)
– Boot ROM
• ACE-CF JTAG delivery of system image from CF
and booting VxWorks (eg JTAG cable like)
Network
– Bootloader:
NTWK
• Retrieve system image over the network
• Retrieve system image from CF via ACE MPU port
• Launch system image from RAM
CPU
RAM
System ACE
& CF
JTAG TST
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JTAG
System ACE-CF Solution
• Loading and Running an Application
– Local access of application in CF
– Remote access of application over Network
– Run RAM resident application
Network
NTWK
CPU
RAM
System ACE
& CF
JTAG TST
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JTAG
ML300
Embedded Development Platform
RJ45
• Management of
System Upgrade
PHY
IPIF
IPIF
IPIF
External
RAM
MAC
Serial
Port
PPC
ML300 & Virtex-II Pro
BRAM
IPIF
MPU
GPIO
CF
CF
JTAG
0
CFG_JTAG
CFG ADDR,
Reset
7
TST_JTAG
MPU
1
6
2
5
4
3
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Embedded Solution Comparison
Network
Network
NTWK
NTWK
CPU
RAM
JTAG
CPU
System ACE
& CF
RAM
JTAG TST
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ROM
JTAG
Virtex-II Pro and System ACE
RJ45
PHY
Network
Serial
Port
IPIF
IPIF
IPIF
External
RAM
MAC
PPC
NTWK
BRAM
IPIF
CPU
MPU
JTAG
GPIO
CF
CF
CFG ADDR,
Reset
JTAG TST
7
0
1
6
5
25
2
4
3
TST_JTAG
CFG_JTAG
RAM
System ACE
& CF
JTAG
MPU
Initial System Bring up
• System bring up from power on or system reset
– Multiple switch selectable configurations
– Hardware and SW boot
• FPGA configuration
• System ACE-CF loading system image and booting
VxWorks
– ACE via JTAG loads system image from CF and boot VxWorks
• System ACE-CF bootloader
– Retrieve system image from CF via ACE MPU port & boot
VxWorks
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PPC Controlled Self Upgrade
• Virtex-II Pro self upgrade using System ACE-CF
– MPU port control of System ACE-CF by the PPC
– Hardware and SW upgrade
• FPGA configuration
• System ACE-CF loading system image and booting
VxWorks
– ACE via JTAG loads system image from CF and boot VxWorks
• System ACE-CF bootloader
– Retrieve system image from CF via ACE MPU port & boot
VxWorks
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PPC Controlled Self Upgrade
• Virtex-II Pro self upgrade using System ACE-CF (contd)
– Load a new software module
• Dynamically link a new software module with VxWorks
– The OS stays up during this process
– Partial Reconfiguration of Virtex-II Pro
• ACE controlled update from CF via JTAG
• ACE file moved from CF via MPU port to RAM
– .ACE file played over MPU to JTAG under PPC control
– OS stays up during partial reconfiguration
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System ACE-CF
for
Embedded Solutions
Directory Structure
• System ACE-CF can support
the bring up capability and file
structure expected in
embedded systems
XILINX.SYS
– System image
– Software module
– Bootloader
System ACE Supported
Local File System
XILINX
VXWORKS
(Software)
vxboot
IMAGES
MODULES
(ELF Format) (ELF Format)
.ace
.out
.out
.out
.out
.
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System ACE-CF and
Embedded Solutions
• System ACE can boot a software system image as
expected in embedded systems
• …And More
– Configure Virtex-II Pro or any Xilinx FPGA
– Load hardware IP as well as software IP from single ACE file
– Offers an MPU interface for application software configuration
of FPGAs using ACE files
– Provides a Microdrive or Compact Flash based Local File
System for non-volatile storage
– Provides a JTAG test port for test, debug an integration with
embedded system development tools
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Xilinx.sys Controlled Tree
• System ACE automatic
configuration controller
uses the .ACE files
located in the Xilinx.sys
tree
System ACE Supported
Local File System
XILINX.SYS
XILINX
VXWORKS
(Software)
vxboot
IMAGES
MODULES
(ELF Format) (ELF Format)
.ace
.out
.out
.out
.out
.
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What’s an .ACE File and what
does System ACE -CF do?
• .ACE files are a Xilinx Proprietary binary SVF file
format (Serial Vector Format)
• System ACE -CF contains an .ACE file player that
is used to play out JTAG commands/data
• .ACE files can contain any combination of H/W
and or S/W
– FPGA configuration data by converting a .bit to .ACE
– PPC code/data by converting a .elf file (Executable
and Linkable Format) to .ACE
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Xilinx.sys Controlled
File Structure
System ACE Supported
Local File System
XILINX.SYS
dir = XILINX;
cfgaddr0 = bootload;
cfgaddr1 = xrom;
cfgaddr2 = linux;
cfgaddr3 = vxboot;
cfgaddr4 = quake;
cfgaddr5 = v2pdraw;
cfgaddr6 = tictac;
cfgaddr7 = vxworks;
XILINX
bootload
xrom
.ace
linux
.ace
vxboot
.ace
quake
.ace
v2pdraw
.ace
tictac
.ace
vxworks
.ace
.ace
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Options for .ACE File
Content
• HW (.bit) only .ACE file
– Only the FPGA is configured
– A .bit file may contain SW targeted for BRAM via
DATA2BRAM utility
• SW (.elf) only .ACE file
– PPC is single stepped to load the SW into memory
– Assumes FPGA is configured and PPC is connected
• Combined HW (.bit) and SW (.elf) .ACE file
– Loads your HW and SW in a single .ACE file
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System ACE-CF File System
Requirements
• ACE-CF can only access a DOS FAT12/16 file system
• ACE-CF requires a file named xilinx.sys at the root
directory
• The xilinx.sys file describes one collection directory with
up to 8 sub-dirs with each containing one or no .ACE file
• All directories accessed by ACE -CF must be valid
FAT 8.3 format
• 8.3 format does not apply to .ACE file names
• Other directories and files may coexist on the CF Disk
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Combined Local File System
System ACE Supported
Local File System
It’s Just a Disk!
XILINX.SYS
VXWORKS
(Software)
XILINX
bootload
PR_ACE
(Bitstreams)
.ace .bit
.ace .bit
xrom
.ace
SCRIPTS
(Utils)
IMAGES
MODULES
(ELF Format) (ELF Format)
linux
.ace
vxboot
.ace
.out
.out
.out
.out
quake
.ace
v2pdraw
.ace
tictac
.ace
vxworks
.ace
.ace
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Directory Structure
It’s Just a Disk!
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Virtex-II Pro and
JTAG
V2P Combined JTAG Chains
• Using the JTAGPPC Block
User Defined
JTAG Pins on
FPGA
– Integrates the PPC405 with the
FPGA Fabric JTAG chain
(dedicated JTAG pins)
– The combined chain supports
development and debug tools
•
•
•
•
TDO
TDI
CPU JTAG
Debug Port
ChipScope Pro (PC4)
iMPACT (PC4)
GDB (PC4)
SingleStep XE (visionPROBEII)
PPC
405
JTAGPPC
Fixed JTAG
Pins on FPGA
JTAG Config Port
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V2P Split JTAG Chains
• User defined JTAG Pins
User Defined
JTAG Pins on
FPGA
– Provides a direct and
TDO
isolated connection to
TDI
PPC
the PPC405 JTAG I/F
405
– JTAGPPC block is not CPU JTAG
Debug Port
used in this configuration
– The isolated chain supports
Fixed JTAG
embedded development
Pins on FPGA
and debug tools
JTAG Config Port
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ML300
Reference Design
How to hook up
System ACE-CF
System ACE-CF & Virtex-II Pro
JTAG
Config & Debug
3.3V Port
CPU JTAG
Debug
Port
CF
2.5V
2.5V
2.5V
405
VCCL
CLK
MPU
GPIO
43
2.5V
G_CLK
TDO
JTAG
RESET
CFGADDR[2:0]
2.5V
33 MHz
CFG_JTAG
CFGMODE
STAT& ERR LEDs
CFPROG
CFINIT
Compact
Flash
VCCH
.[
3.3V
TST_JTAG
POR_RESET
POR_BYPASS
POR_TEST
CPU_TDI
CPU_VCC
TCK
2.5V
System ACE and Virtex-II Pro
ML300
The JTAG Bus to program
JTAG
the FPGA Fabric
Config & Debug
Port
3.3V
TCK
3.3V
TST_JTAG
POR_RESET
POR_BYPASS
POR_TEST
CF
Compact
Flash
VCCH
2.5V
2.5V
CLK
RESET
CFGADDR[2:0]
MPU
ML300 Schematic
Rev B. pg. 3 of 55
Mode Switches for SysACE
File selection
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CFG_JTAG
CFGMODE
33 MHz
STAT& ERR LEDs
CFPROG
CFINIT
VCCL
TDO
System ACE and Virtex-II Pro
ML300
Access the JTAG Config port
from one of three connectors
JTAG
Config & Debug
3.3V Port
TCK
3.3V
TST_JTAG
POR_RESET
POR_BYPASS
POR_TEST
CF
Compact
Flash
VCCH
2.5V
2.5V
CLK
RESET
CFGADDR[2:0]
MPU
ML300 Schematic
Rev B. pg. 3 of 55
45
CFG_JTAG
CFGMODE
33 MHz
STAT& ERR LEDs
CFPROG
CFINIT
VCCL
TDO
JTAG Connectors
ML300
Three JTAG Connectors:
P115 - Fixed JTAG pins only
P114 and P109 - Fixed or User JTAG
With the jumper connected,
connect PC4 Cable to P115
to access Fixed JTAG Pins
ML300 Schematic Rev B. pg. 3 of 55
46
With the Jumper off, WRS
VisionProbe can access the
Fixed JTAG pins on P114
P109 is a Mictor
connector for use
with the WRS Vision
Probe
JTAG CPU Debug Port
ML300 CPU Debug Port allows direct
CPU JTAG
Debug
Port
access to User JTAG pins
2.5V
.[
CPU_TDI
CPU_VCC
2.5V
405
2.5V
G_CLK
JTAG
2.5V
ML300 Schematic
Rev B. pg. 3 of 55
47
System ACE MPU Port
ML300
JTAG
Config & Debug
Port
3.3V
CPU JTAG
Debug
Port
3.3V
TST_JTAG
POR_RESET
POR_BYPASS
POR_TEST
.
[
CPU_TDI
CPU_VCC
TCK
2.5V
VCCH
CF
2.5V
2.5V
405
CLK
2.5V
2.5V
G_CLK
TDO
JTAG
RESET
CFGADDR[2:0]
CFG_JTAG
CFGMODE
STAT& ERR LEDs
CFPROG
CFINIT
VCCL
MPU
ML300 Schematic
Rev B. pg. 17 of 55
48
System ACE & Compact Flash
ML300
JTAG
Config & Debug
3.3V Port
TCK
TST_JTAG
POR_RESET
POR_BYPASS
POR_TEST
CF
Compact
Flash
VCCH
2.5V
CFGMODE
33 MHz
CLK
RESET
CFGADDR[2:0]
MPU
ML300 Schematic
Rev B. pg. 27 of 55
49
STAT& ERR LEDs
CFPROG
CFINIT
VCCL