Download FDMS3669S PowerTrench Power Stage

PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFETs in a
„ Max rDS(on) = 10 mΩ at VGS = 10 V, ID = 13 A
dual PQFN package. The switch node has been internally
„ Max rDS(on) = 14.5 mΩ at VGS = 4.5 V, ID = 10 A
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
Q2: N-Channel
SyncFETTM (Q2) have been designed to provide optimal power
„ Max rDS(on) = 5 mΩ at VGS = 10 V, ID = 18 A
efficiency.
„ Max rDS(on) = 5.2 mΩ at VGS = 4.5 V, ID = 17 A
Applications
„ Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
„ Computing
„ MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
„ Communications
„ RoHS Compliant
„ Notebook VCORE
„ General Purpose Point of Load
G1
Pin 1
D1
Pin 1
D1
D1
D1
PHASE
(S1/D2)
G2
S2
S2
Top
S2
5
S2
6
S2
7
G2
8
S2
Bottom
Power 56
Q2
4 D1
PHASE
3 D1
2 D1
1 G1
Q1
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current
ID
TJ, TSTG
Units
V
V
(Note 3)
±20
±12
TC = 25 °C
24
60
-Continuous (Silicon limited)
TC = 25 °C
43
75
-Continuous
TA = 25 °C
131a
181b
-Pulsed
PD
Q2
30
-Continuous (Package limited)
(Note 6)
Single Pulse Avalanche Energy
EAS
Q1
30
50
60
614
485
mJ
Power Dissipation for Single Operation
TA = 25 °C
2.21a
2.51b
Power Dissipation for Single Operation
TA = 25 °C
1.01c
1.01d
Operating and Storage Junction Temperature Range
A
W
-55 to +150
°C
Thermal Characteristics
Thermal Resistance, Junction to Ambient
571a
501b
RθJA
Thermal Resistance, Junction to Ambient
1251c
1201d
RθJC
Thermal Resistance, Junction to Case
5.0
2.8
RθJA
°C/W
Package Marking and Ordering Information
Device Marking
9ACF
21CD
Device
Package
Reel Size
Tape Width
Quantity
FDMS3669S
Power 56
13 ”
12 mm
3000 units
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
1
www.fairchildsemi.com
FDMS3669S PowerTrench® Power Stage
January 2013
FDMS3669S
Symbol
Parameter
Test Conditions
Type
Min
30
30
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
Q1
Q2
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
Q1
Q2
1
500
μA
μA
IGSS
Gate to Source Leakage Current
VGS = 20 V, VDS= 0 V
VGS = 12 V, VDS= 0 V
Q1
Q2
100
100
nA
nA
2.7
2.5
V
V
16
20
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1
Q2
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-6
-3
VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 10 A
VGS = 10 V, ID = 13 A , TJ = 125 °C
Q1
8.1
12
11
10
14.5
14.5
VGS = 10 V, ID = 18 A
VGS = 4.5 V, ID = 17 A
VGS = 10 V, ID = 18 A , TJ = 125 °C
Q2
2.8
3.5
4.0
5.0
5.2
7.1
VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 18 A
Q1
Q2
53
113
Q1
Q2
1205
1469
1605
2060
pF
Q1
Q2
370
485
495
680
pF
Q1
Q2
35
59
55
90
pF
1.6
1.4
3.2
3.0
Ω
rDS(on)
gFS
Drain to Source On Resistance
Forward Transconductance
1.1
1.1
2.0
1.5
mV/°C
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
0.3
0.2
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg
Total Gate Charge
Qg
Total Gate Charge
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
Q1:
VDD = 15 V, ID = 13 A, RGEN = 6 Ω
Q2:
VDD = 15 V, ID = 18 A, RGEN = 6 Ω
VGS = 0 V to 10 V
Q1:
VDD = 15 V,
VGS = 0 V to 4.5 V ID = 13 A
Q2:
VDD = 15 V,
ID = 18 A
2
Q1
Q2
9
7
18
14
ns
Q1
Q2
3
3
10
10
ns
Q1
Q2
20
24
36
40
ns
Q1
Q2
3
3
10
10
ns
Q1
Q2
17
24
24
34
nC
Q1
Q2
7.5
12
12
17
nC
Q1
Q2
3.9
3.3
nC
Q1
Q2
2.0
3.6
nC
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FDMS3669S PowerTrench® Power Stage
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Q1
Q1
Q2
Q2
0.8
0.7
0.8
0.7
1.2
1.2
1.2
1.2
V
Q1
Q2
24
21
38
33
ns
Q1
Q2
8
16
15
31
nC
Drain-Source Diode Characteristics
VSD
VGS = 0 V, IS = 13 A
V = 0 V, IS = 2 A
Source to Drain Diode Forward Voltage GS
VGS = 0 V, IS = 18 A
VGS = 0 V, IS = 2 A
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
Q1:
IF = 13 A, di/dt = 100 A/μs
Q2:
IF = 18 A, di/dt = 300 A/μs
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Notes:
1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
b. 50 °C/W when mounted on
a 1 in2 pad of 2 oz copper
a. 57 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied with the negative Vgs rating.
4. EAS of 61 mJ is based on starting TJ = 25 oC; N-ch: L = 3 mH, IAS = 6.4 A, VDD = 30 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 20 A.
5. EAS of 48 mJ is based on starting TJ = 25 oC; N-ch: L = 3 mH, IAS = 5.7 A, VDD = 30 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 17 A.
6. Pulsed Id limited by junction temperature,td<=10uS. Please refer to SOA curve for more details.
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
3
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FDMS3669S PowerTrench® Power Stage
Electrical Characteristics TJ = 25 °C unless otherwise noted
5
VGS = 10 V
VGS = 6 V
40
VGS = 4.5 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
50
VGS = 4 V
30
20
10
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0
0.5
1.0
1.5
VGS = 3.5 V
2.0
2.5
VGS = 3.5 V
3
1
0
0
10
rDS(on), DRAIN TO
1.4
1.2
1.0
0.8
0.6
-75
-50
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
30
40
50
30
ID = 13 A
VGS = 10 V
TJ = 125 oC
15
10
TJ = 25 oC
4
6
8
10
50
IS, REVERSE DRAIN CURRENT (A)
VDS = 5 V
30
TJ = 150 oC
20
TJ = 25 oC
10
TJ = -55 oC
4
VGS = 0 V
10
TJ = 150 oC
TJ = 25 oC
1
TJ = -55 oC
0.1
0.0
5
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
20
Figure 4. On-Resistance vs Gate to
Source Voltage
40
3
25
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
2
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 13 A
5
2
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs Junction Temperature
ID, DRAIN CURRENT (A)
20
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.6
1
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
0
VGS = 4.5 V
VGS = 6 V
2
VDS, DRAIN TO SOURCE VOLTAGE (V)
50
VGS = 4 V
4
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
4
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FDMS3669S PowerTrench® Power Stage
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2000
ID = 13 A
1000
Ciss
8
VDD = 10 V
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
6
VDD =15 V
VDD = 20 V
4
Coss
100
2
0
0
3
6
9
12
15
10
0.1
18
Figure 7. Gate Charge Characteristics
10
30
Figure 8. Capacitance vs Drain
to Source Voltage
25
50
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
20
TJ = 25 oC
15
TJ = 125 oC
TJ = 100 oC
10
5
40
VGS = 10 V
30
VGS = 4.5 V
20
Limited by Package
10
o
RθJC = 5.0 C/W
1
0.01
0.1
1
10
0
25
40
50
150
1000
P(PK), PEAK TRANSIENT POWER (W)
100 μs
10
1 ms
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
SINGLE PULSE
TJ = MAX RATED
1s
10 s
DC
RθJA = 125 oC/W
TA = 25 oC
0.01
0.01
125
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
100
0.1
100
o
Figure 9. Unclamped Inductive
Switching Capability
1
75
TC, CASE TEMPERATURE ( C)
tAV, TIME IN AVALANCHE (ms)
ID, DRAIN CURRENT (A)
Crss
f = 1 MHz
VGS = 0 V
0.1
1
10
o
RθJA = 125 C/W
100
10
1
0.1 -4
10
100200
-3
10
-2
10
-1
10
1
100
10
1000
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
SINGLE PULSE
Figure 12. Single Pulse Maximum
Power Dissipation
5
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FDMS3669S PowerTrench® Power Stage
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
DUTY CYCLE-DESCENDING ORDER
NORMALIZED THERMAL
IMPEDANCE, ZθJA
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
0.01
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
o
RθJA = 125 C/W
(Note 1c)
0.001 -4
10
-3
10
-2
10
-1
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
6
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FDMS3669S PowerTrench® Power Stage
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
25 oC unlenss otherwise noted
60
8
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
VGS = 10 V
VGS = 4.5 V
45
VGS = 3.5 V
VGS = 3 V
30
VGS = 2.5 V
15
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0
0.3
0.6
0.9
1.2
6
4
VGS = 3.5 V
VGS = 3 V
2
VGS = 4.5 V
0
1.5
0
15
30
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 14. On-Region Characteristics
45
60
20
ID = 18 A
VGS = 10 V
rDS(on), DRAIN TO
1.4
1.2
1.0
0.8
0.6
-75
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
VGS = 10 V
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
15
ID = 18 A
10
TJ = 25 oC
0
-50
-25
0
25
50
75
TJ = 125 oC
5
100 125 150
2
4
TJ, JUNCTION TEMPERATURE (oC)
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 17. On-Resistance vs Gate to
Source Voltage
Figure 16. Normalized On-Resistance
vs Junction Temperature
100
60
IS, REVERSE DRAIN CURRENT (A)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID, DRAIN CURRENT (A)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 2.5 V
45
VDS = 5 V
TJ
= 125 oC
30
TJ = 25 oC
15
TJ = -55 oC
0
1.0
1.5
2.0
2.5
10
TJ = 125 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
1E-3
0.0
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
Figure 18. Transfer Characteristics
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
VGS = 0 V
7
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FDMS3669S PowerTrench® Power Stage
Typical Characteristics (Q2 N-Channel) TJ =
10000
ID = 17 A
Ciss
8
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
VDD = 10 V
6
VDD = 15 V
4
VDD = 20 V
1000
Coss
100
2
0
f = 1 MHz
VGS = 0 V
0
10
20
10
0.1
30
1
30
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
80
ID, DRAIN CURRENT (A)
100
IAS, AVALANCHE CURRENT (A)
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
TJ = 100 oC
10
TJ = 25 oC
TJ = 125
oC
60
0.01
0.1
1
10
100
VGS = 10 V
VGS = 4.5 V
40
Limited by Package
o
RθJC = 2.8 C/W
20
0
1
1E-3
25
50
P(PK), PEAK TRANSIENT POWER (W)
100 μs
10
0.1
RθJA = 120 oC/W
TA = 25 oC
0.01
0.01
1 ms
10 ms
100 ms
SINGLE PULSE
TJ = MAX RATED
0.1
1s
10s
CURVE BENT ON
MEASURED DATA
1
10
DC
100200
150
2000
1000
SINGLE PULSE
o
RθJA = 120 C/W
100
10
1
0.5 -4
10
-3
10
-2
10
-1
10
0
10
1
10
100
1000
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 25. Single Pulse Maximum
Power Dissipation
Figure 24. Forward Bias Safe
Operating Area
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
125
Figure 23. Maximun Continuous Drain
Current vs Case Temperature
100
THIS AREA IS
LIMITED BY rDS(on)
100
TC, CASE TEMPERATURE ( C)
Figure 22. Unclamped Inductive
Switching Capability
1
75
o
tAV, TIME IN AVALANCHE (ms)
ID, DRAIN CURRENT (A)
Crss
8
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FDMS3669S PowerTrench® Power Stage
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
NORMALIZED THERMAL
IMPEDANCE, ZθJA
2
1
0.1
0.01
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
SINGLE PULSE
t2
o
RθJA = 120 C/W
1E-3
1E-4 -4
10
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
(Note 1d)
-3
10
-2
10
-1
0
10
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
9
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FDMS3669S PowerTrench® Power Stage
TJ = 25 oC unless otherwise noted
Typical Characteristics (Q2 N-Channel)
SyncFETTM Schottky body diode
Characteristics
Fairchild’s SyncFETTM process embeds a Schottky diode in
parallel with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3669S.
Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power
in the device.
-2
IDSS, REVERSE LEAKAGE CURRENT (A)
20
15
CURRENT (A)
didt = 300 A/μs
10
5
0
-5
-40
0
40
80
120
160
TJ = 125 oC
-3
10
TJ = 100 oC
-4
10
-5
10
TJ = 25 oC
-6
10
0
5
10
15
20
25
30
VDS, REVERSE VOLTAGE (V)
TIME (ns)
Figure 28. SyncFETTM body diode reverse
leakage versus drain-source voltage
Figure 27. FDMS3669S SyncFETTM body
diode reverse recovery characteristic
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
10
10
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FDMS3669S PowerTrench® Power Stage
Typical Characteristics (continued)
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Competitors solution
Power Stage Device
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
11
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FDMS3669S PowerTrench® Power Stage
Application Information
FDMS3669S PowerTrench® Power Stage
Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part.
Figure 31. Recommended PCB Layout
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
12
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1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
13
www.fairchildsemi.com
FDMS3669S PowerTrench® Power Stage
Following is a guideline, not a requirement which the PCB designer should consider:
FDMS3669S PowerTrench® Power Stage
Dimensional Outline and Pad Layout
(2X )
CL
B
PKG
CL
8
A
0.00
0.10 C
4.00
2.00
5.10
4.90
8
5
7
6
1.27 TYP
0.65 TYP
5
0.63
2.52
1.60
KEEP OUT AREA
2.15
6.25
5.90
PKG CL
0.00 CL
4.16
1.21
2.13
1
PIN # 1
INDICATOR
4
0.10 C
(2 X)
0.63
1.18
TOP VIEW
2
1
SEE
DETAIL A
3
4
2.31
3.15
0.59
3.18
5.10
RECOMMENDED LAND PATTERN
FOR SAWN / PUNCHED TYPE
SIDE VIEW
0.1 0
0.0 5
0.65
0.38
0.35
0.30
3.16
2.80
1
2
3
(6X)
C A B
C
0.70
0.36
4
8X
0.08 C
1.34
1.12
1.10
0.90
0.65
0.38
8
0.44
0.24
7
6
1.27
5
0.35
0.15
0.05
0.00
C
SEATING
P LANE
DETAIL 'A'
0.66? 05
(SCALE: 2X)
2.25
2.05
4.08
3.70
0 .10 C
1.02
0.82
0.61 (8X)
0.31
3.81
BOTTOM VIEW
OPTION - A (SAWN TYPE)
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
14
www.fairchildsemi.com
FDMS3669S PowerTrench® Power Stage
Dimensional Outline and Pad Layout
5.10
4.90
0.10 C
(2X)
SEE
DETAIL B
PKG
C
L
8
0.35
0.15
5
0.28
0.08
PKG
6.25
5.90
CL
1
4
DETAIL 'B'
(SCALE: 2X)
0.10 C
(2X)
0.41 (8X)
0.21
TOP VIEW
10?
5.90
5.70
5.00
4.80
SEE
DETAIL C
0.10 C
0.35
0.15
8X
0.08 C
C
SIDE VIEW
1.10
0.90
0.35
0.30
(6X)
0.65
0.38
3.16
2.80
1
2
3
0.70
0.36
4
0.10
0.05
C A B
C
1.34
1.12
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC REGISTRATION, MO-240, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQN08EREV5.
0.66? 05
2.25
2.05
4.08
3.70
0.65
0.38
8
0.44
0.24
7
6
1.27
5
DETAIL 'C'
(SCALE: 2X)
SEATING
PLANE
1.02
0.82
0.61
0.31
(8X)
3.81
BOTTOM VIEW
OPTION - B (PUNCHED TYPE)
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
15
www.fairchildsemi.com
tm
tm
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE
RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY
PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY
THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE
EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used here in:
1. Life support devices or systems are devices or systems which, (a) are
intended for surgical implant into the body or (b) support or sustain life,
and (c) whose failure to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury of the user.
2.
A critical component in any component of a life support, device, or
system whose failure to perform can be reasonably expected to cause
the failure of the life support device or system, or to affect its safety or
effectiveness.
ANTI-COUNTERFEITING POLICY
Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website,
www.Fairchildsemi.com, under Sales Support.
Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their
parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed
application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the
proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild
Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild
Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of
up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and
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committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative / In Design
Datasheet contains the design specifications for product development. Specifications
may change in any manner without notice.
Definition
Preliminary
First Production
Datasheet contains preliminary data; supplementary data will be published at a later
date. Fairchild Semiconductor reserves the right to make changes at any time without
notice to improve design.
No Identification Needed
Full Production
Datasheet contains final specifications. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve the design.
Obsolete
Not In Production
Datasheet contains specifications on a product that is discontinued by Fairchild
Semiconductor. The datasheet is for reference information only.
Rev. I61
©2013 Fairchild Semiconductor Corporation
FDMS3669S Rev.C1
16
www.fairchildsemi.com
FDMS3669S PowerTrench® Power Stage
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
2Cool™
F-PFS™
PowerTrench®
The Power Franchise®
®
PowerXS™
AccuPower™
FRFET®
Global Power ResourceSM
Programmable Active Droop™
AX-CAP™*
Green Bridge™
QFET®
BitSiC®
TinyBoost™
Build it Now™
QS™
Green FPS™
TinyBuck™
CorePLUS™
Quiet Series™
Green FPS™ e-Series™
TinyCalc™
CorePOWER™
RapidConfigure™
Gmax™
TinyLogic®
CROSSVOLT™
GTO™
™
TINYOPTO™
CTL™
IntelliMAX™
TinyPower™
Saving our world, 1mW/W/kW at a time™
Current Transfer Logic™
ISOPLANAR™
TinyPWM™
DEUXPEED®
Marking Small Speakers Sound Louder SignalWise™
TinyWire™
Dual Cool™
SmartMax™
and Better™
TranSiC®
EcoSPARK®
SMART START™
MegaBuck™
TriFault Detect™
EfficentMax™
Solutions for Your Success™
MICROCOUPLER™
TRUECURRENT®*
ESBC™
SPM®
MicroFET™
μSerDes™
STEALTH™
MicroPak™
®
SuperFET®
MicroPak2™
SuperSOT™-3
MillerDrive™
Fairchild®
UHC®
SuperSOT™-6
MotionMax™
Fairchild Semiconductor®
Ultra FRFET™
SuperSOT™-8
Motion-SPM™
FACT Quiet Series™
UniFET™
SupreMOS®
mWSaver™
FACT®
VCX™
SyncFET™
OptoHiT™
FAST®
VisualMax™
Sync-Lock™
OPTOLOGIC®
FastvCore™
VoltagePlus™
OPTOPLANAR®
®*
FETBench™
XS™
FlashWriter® *
®
FPS™