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FDPC8012S PowerTrench® Power Clip 25V Asymmetric Dual N-Channel MOSFET Features General Description Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a Max rDS(on) = 7.0 mΩ at VGS = 4.5 V, ID = 12 A dual package. The switch node has been internally connected to Q2: N-Channel enable easy placement and routing of synchronous buck Max rDS(on) = 2.2 mΩ at VGS = 4.5 V, ID = 23 A converters. The control MOSFET (Q1) and synchronous SyncFETTM (Q2) have been designed to provide optimal power Low inductance packaging shortens rise/fall times, resulting in lower switching losses efficiency. MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing Applications RoHS Compliant Communications Computing General Purpose Point of Load Pin 1 V+ LSG GND V+ GND (HSD GND (LSS SW Pin 1 HSG SW SW HSG PAD9 V+(HSD) V+ LSG SW SW SW 3.3 mm x 3.3 mm LSG SW GND SW PAD10 GND(LSS) GND GND GND SW SW Top V+ HSG Bottom MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID Q1 25 TJ, TSTG V 12 12 TC = 25 °C 35 88 -Continuous TA = 25 °C 131a 261b 40 120 (Note 4) Single Pulse Avalanche Energy PD Units V -Continuous -Pulsed EAS Q2 25 50 181 Power Dissipation for Single Operation TA = 25 °C (Note 3) 1.61a 2.01b Power Dissipation for Single Operation TA = 25 °C 0.81c 0.91d Operating and Storage Junction Temperature Range A mJ -55 to +150 W °C Thermal Characteristics Thermal Resistance, Junction to Ambient 771a RθJA Thermal Resistance, Junction to Ambient 1c RθJC Thermal Resistance, Junction to Case RθJA 151 5.0 631b 1351d °C/W 3.5 Package Marking and Ordering Information Device Marking 01OD/03OD Device FDPC8012S ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C Package Power Clip 33 1 Reel Size 13 ” Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip December 2012 Symbol Parameter Test Conditions Type Min 25 25 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V VDS = 20 V, VGS = 0 V Q1 Q2 1 500 μA μA IGSS Gate to Source Leakage Current, Forward VGS = 12 V/-8 V, VDS= 0 V VGS = 12 V/-8 V, VDS= 0 V Q1 Q2 ±100 ±100 nA nA 2.2 2.2 V V 18 22 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA VGS = VDS, ID = 1 mA Q1 Q2 ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 -4 -4 VGS = 4.5 V, ID = 12 A VGS = 4.5 V, ID = 12 A,TJ =125 °C Q1 5.2 7.5 7.0 10.5 VGS = 4.5 V, ID = 23 A VGS = 4.5 V, ID = 23 A ,TJ =125 °C Q2 1.6 2.3 2.2 3.2 VDS = 5 V, ID = 13 A VDS = 5 V, ID = 26 A Q1 Q2 79 200 S Q1: VDS = 13 V, VGS = 0 V, f = 1 MHZ Q1 Q2 1075 3456 pF Q1 Q2 250 885 pF Q1 Q2 50 130 pF rDS(on) gFS Drain to Source On Resistance Forward Transconductance 0.8 1.1 1.3 1.6 mV/°C mΩ Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance Q2: VDS = 13 V, VGS = 0 V, f = 1 MHZ Q1 Q2 0.1 0.1 0.4 0.5 2.0 2.0 Ω Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg Total Gate Charge Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C Q1: VDD = 13 V, ID = 13 A, RGEN = 6 Ω Q2: VDD = 13 V, ID = 26 A, RGEN = 6 Ω VGS = 0 V to 4.5 V Q1 VDD = 13 V, ID = 13 A Q2 VDD = 13 V, ID = 26 A 2 Q1 Q2 6 12 ns Q1 Q2 2 3 ns Q1 Q2 19 34 ns Q1 Q2 2 3 ns Q1 Q2 8 25 nC Q1 Q2 2.3 7.8 nC Q1 Q2 2.0 6.4 nC www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Electrical Characteristics TJ = 25 °C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 0.8 1.2 1.2 V Q1 Q2 20 27 35 43 ns Q1 Q2 6 27 12 43 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 13 A VGS = 0 V, IS = 26 A (Note 2) (Note 2) Q1 IF = 13 A, di/dt = 100 A/μs Q2 IF = 26 A, di/dt = 300 A/μs Notes: 1.RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 63 °C/W when mounted on a 1 in2 pad of 2 oz copper a. 77 °C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G SS SF DS DF G d. 135 °C/W when mounted on a minimum pad of 2 oz copper c. 151 °C/W when mounted on a minimum pad of 2 oz copper SS SF DS DF G SS SF DS DF G 2 Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. Q1 :EAS of 50 mJ is based on starting TJ = 25 oC; N-ch: L = 3 mH, IAS = 5.8A, VDD = 25 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 14.5 A. Q2: EAS of 181 mJ is based on starting TJ = 25 oC; N-ch: L = 3 mH, IAS = 11 A, VDD = 25 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 32.9 A. 4. Pulsed Id limited by junction temperature,td<=10uS. Please refer to SOA curve for more details. ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 3 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Electrical Characteristics TJ = 25 °C unless otherwise noted VGS = 10 V VGS = 4.5 V 32 VGS = 3.5 V VGS = 3 V 24 16 VGS = 2.5 V 8 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.2 0.4 0.6 0.8 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 40 VGS = 2.5 V 4 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 3 VGS = 3 V 2 1 0 1.0 0 8 VDS, DRAIN TO SOURCE VOLTAGE (V) 32 40 30 ID = 13 A VGS = 10 V SOURCE ON-RESISTANCE (mΩ) 1.4 rDS(on), DRAIN TO NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 24 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 1.2 1.0 0.8 0.6 -75 -50 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 20 15 10 TJ = 125 oC 5 TJ = 25 oC 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) ID = 13 A 25 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 100 40 IS, REVERSE DRAIN CURRENT (A) VDS = 5 V ID, DRAIN CURRENT (A) 16 VGS = 10 V ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics 32 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 24 TJ = 150 oC 16 TJ = 25 oC 8 TJ = -55 0 VGS = 4.5 V VGS = 3.5 V 0 1 2 oC 3 10 1 TJ = 150 oC TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 4 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C VGS = 0 V Figure 6. Source to Drain Diode Forward Voltage vs Source Current 4 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted ID = 13 A VDD = 10 V Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 5000 10 VDD = 13 V 6 VDD = 15 V 4 1000 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 4 8 12 16 10 0.1 20 1 10 25 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 60 50 10 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o RθJC = 5.0 C/W TJ = 100 oC TJ = 25 oC TJ = 125 oC 1 0.001 0.01 0.1 1 10 48 VGS = 10 V 36 VGS = 4.5 V 24 Limited by Package 12 0 25 100 50 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 150 1000 100 μs 10 1 ms 10 ms 100 ms THIS AREA IS LIMITED BY rDS(on) SINGLE PULSE TJ = MAX RATED RθJA = 151 oC/W TA = 25 oC 0.01 0.01 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 100 0.1 100 o Figure 9. Unclamped Inductive Switching Capability 1 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) 1s 10 s DC DERIVED FROM TEST DATA 0.1 1 10 10 SINGLE PULSE RθJA = 151 oC/W 1 TA = 25 oC 0.1 -4 10 100 VDS, DRAIN to SOURCE VOLTAGE (V) -3 10 -2 10 -1 10 0 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 100 Figure 12. Single Pulse Maximum Power Dissipation 5 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 151 C/W (Note 1c) 0.001 -4 10 -3 10 -2 10 -1 0 10 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 6 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted VGS = 10 V VGS = 4.5 V 90 VGS = 4 V VGS = 3.5 V VGS = 3 V 60 30 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.2 0.4 0.6 VDS, DRAIN TO SOURCE VOLTAGE (V) 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 120 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 4 VGS = 3 V 3 2 1 0 30 60 90 120 ID, DRAIN CURRENT (A) Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage 8 1.6 ID = 26 A VGS = 10 V SOURCE ON-RESISTANCE (mΩ) 1.4 rDS(on), DRAIN TO NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 0 VGS = 10 V VGS = 4.5 V VGS = 4 V 0.8 Figure 14. On-Region Characteristics 1.2 1.0 0.8 0.6 -75 120 4 TJ = 125 oC 2 TJ = 25 oC IS, REVERSE DRAIN CURRENT (A) VDS = 5 V TJ = 125 oC 60 TJ = 25 oC 40 TJ = -55 oC 20 2.5 3.0 3 4 5 6 7 8 9 200 100 VGS = 0 V 10 TJ = 125 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 3.5 0.2 0.4 0.6 0.8 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode Forward Voltage vs Source Current ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 10 Figure 17. On-Resistance vs Gate to Source Voltage 80 2.0 2 VGS, GATE TO SOURCE VOLTAGE (V) 100 1.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 6 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 1.0 ID = 26 A 0 -50 Figure 16. Normalized On-Resistance vs Junction Temperature ID, DRAIN CURRENT (A) VGS = 3.5 V 7 1.0 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted ID = 26 A Ciss VDD = 10 V 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10000 10 VDD = 13 V 6 VDD = 15 V 4 Coss 1000 Crss 100 2 f = 1 MHz VGS = 0 V 0 0 12 24 36 48 10 0.1 60 1 120 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 300 100 TJ = 100 oC 10 TJ = 25 oC TJ = 125 oC 1 0.001 0.01 96 72 48 o VGS = 4.5 V RθJC = 3.5 C/W 24 0.1 1 10 0 25 100 50 75 100 125 150 o TC, CASE TEMPERATURE ( C) Figure 23. Maximum Continuous Drain Current vs Case Temperature Figure 22. Unclamped Inductive Switching Capability 10000 P(PK), PEAK TRANSIENT POWER (W) 200 100 100 μs ID, DRAIN CURRENT (A) VGS = 10 V Limited by Package tAV, TIME IN AVALANCHE (ms) 10 0.1 25 Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) 1 ms 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms SINGLE PULSE TJ = MAX RATED 1s RθJA = 135 oC/W 10 s DC TA = 25 oC 0.01 0.01 DERIVED FROM TEST DATA 0.1 1 10 100 VDS, DRAIN to SOURCE VOLTAGE (V) 100 10 1 SINGLE PULSE RθJA = 135 oC/W TA = 25 oC 0.1 -4 10 -3 10 -2 10 -1 10 0 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 24. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 1000 Figure 25. Single Pulse Maximum Power Dissipation 8 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Typical Characteristics (Q2 N-Channel) TJ = 25°C unless otherwise noted NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 0.01 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 135 C/W 1E-3 (Note 1d) 1E-4 -4 10 -3 10 -2 10 -1 10 0 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 9 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted SyncFETTM Schottky body diode Characteristics Fairchild’s SyncFETTM process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDPC8012S. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. -2 IDSS, REVERSE LEAKAGE CURRENT (A) 30 25 di/dt = 300 A/μs CURRENT (A) 20 15 10 5 0 -5 0 80 160 240 320 400 TIME (ns) TJ = 125 oC -3 10 TJ = 100 oC -4 10 -5 10 TJ = 25 oC -6 10 0 5 10 15 20 25 VDS, REVERSE VOLTAGE (V) Figure 28. SyncFETTM body diode reverse leakage versus drain-source voltage Figure 27. FDPC8012S SyncFETTM body diode reverse recovery characteristic ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 10 10 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Typical Characteristics (continued) Typical Application Diagram (Synchronous Rectifier Buck Converter) Figure 1.Power Clip in Buck Converter Topology As shown in Figure 1, in the Power Clip package Q1 is the High Side MOSFET (Control MOSFET) and Q2 is the Low Side MOSFET (Synchronous MOSFET). Figure 2 below shows the package pin out. The blue overlay on the drawing indicates a typical PCB land pattern for the part. Figure 2.Top View of Power Clip Table 1 Pin Information shows the name and description of each pin. PIN Number Description Name 1 HSG 2,3,4 SW Switch or Phase node, Source of Q1 and Drain of Q2 5,6,PAD 10 GND,GND(LSS) PAD Ground, Source of Q2 7 LSG Gate signal input of Q2 Gate 8,PAD 9 V+, V+(HSD) PAD Table 1. Pin Information ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C Gate signal input of Q1 Gate Input voltage of SR Buck converter, Drain of Q1 11 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Application Information As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Clip is a high power density solution and all high current flow paths, such as V+(HSD), SW and GND(LSS) should be short and wide for minimal resistance and inductance. V+(HSD) and GND(LSS) are the primary heat flow paths for the Power Clip. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part. Figure 3.Top/Component (green) View and Bottom (red) PCB View Following is a guideline, not a requirement which the PCB designer should consider. Figure 3 shows an example of a well designed layout. The discussion that follows summarizes the key features of this layout. "The input ceramic bypass capacitor between VIN and GND should be placed as close as possible to the pins V+ / V+(HSD) PAD and GND / GND(LSS) PAD to help reduce parasitic inductance and high frequency ringing. Several capacitors may be placed in parallel, and capacitors may be placed on both the top and bottom side of the board. The capacitor located immediately adjacent to the Power Clip will be the most effective at reducing HF parasitic. Caps located farther away, or on the opposite side of the board will also assist, but will be less effective due to increased trace inductance. "The Power Clip package design, with very short distance between pins V+ and GND, allows for a short connect distance to the input cap. This is a factor that enables the Power Clip switch loop to have very low parasitic inductance. "Use large copper areas on the component side to connect the V+ pin and V+ (HSD) pad, and the GND and GND(LSS) PAD. "The SW to inductor copper trace is a high current path. It will also be a high noise region due to switching voltage transients. The trace should be short and wide to enable a low resistance path and to minimize the size of the noise region. Care should be taken to minimize coupling of this trace to adjacent traces. The layout in Figure 3 shows a good example of this short, wide path. "The Power Trench® Technology MOSFETs used in the Power Clip are effective at minimizing SW node ringing. They incorporate a proprietary design1 that minimizes the peak overshoot ring voltage on the switch node (SW). They allow the part to operate well within the breakdown voltage limits. For most layouts, this eliminates the need to add an external snubber circuit. If the designer chooses to use an RC snubber, it should be placed close to the part between the SW pins and GND / GND (LSS) PAD to dampen the high frequency ringing. "The Driver IC should be placed relatively closed to HSG pin and LSG pin to minimize G drive trace inductance. Excessive G trace length may slow the switching speed of the HS drive. And it may lead to excessive ringing on the LS G. If the designer must place the driver a significant distance away from the Power Clip, it would be a good practice to include a 0 Ohm resistor in the LS G path as a place holder. In the final design, if the LS G exhibits excessive LF ringing, efficiency can often be improved by changing this resistor to a few Ohms to dampen the LS G LF ringing. "The Power Clip has very good Junction-PCB heat transfer from all power pins. It has much better heat transfer Junction-GND (LSS) than traditional dual FET packages. In most cases, board ground will be the most effective heat transfer path on the PCB. Use a large copper area between GND / GND(LSS)PAD pins and board ground. To ensure the best thermal and electrical connection to ground, we recommend using multiple vias to interconnect ground plane layers as shown in Figure 3. 1.Patent Pending ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 12 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip Recommended PCB Layout Guidelines "Avoid using narrow thermal relief traces on the V+ / V+(HSD) PAD and GND / GND(LSS)PAD pins. These will increase HF switch loop inductance. And these will increase ringing of the HF power loop and the SW node. ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 13 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip "Use multiple vias in parallel on each copper region to interconnect top, inner and bottom layers. This will reduce resistance and inductance of the vias and will improve thermal conductivity. Vias should be relatively large, around 8 mils to 10 mils. FDPC8012S PowerTrench® Power Clip Dimensional Outline and Pad Layout ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 14 www.fairchildsemi.com tm *Trademarks of System General Corporation, used under license by Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used here in: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ANTI-COUNTERFEITING POLICY Fairchild Semiconductor Corporation’s Anti-Counterfeiting Policy. Fairchild’s Anti-Counterfeiting Policy is also stated on our external website, www.Fairchildsemi.com, under Sales Support. Counterfeiting of semiconductor parts is a growing problem in the industry. All manufactures of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed application, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild’s quality standards for handing and storage and provide access to Fairchild’s full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address and warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I61 ©2012 Fairchild Semiconductor Corporation FDPC8012S Rev.C 15 www.fairchildsemi.com FDPC8012S PowerTrench® Power Clip TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 2Cool™ F-PFS™ PowerTrench® The Power Franchise® ® AccuPower™ FRFET® PowerXS™ AX-CAP™* Global Power ResourceSM Programmable Active Droop™ BitSiC® Green Bridge™ QFET® TinyBoost™ Green FPS™ Build it Now™ QS™ TinyBuck™ Green FPS™ e-Series™ CorePLUS™ Quiet Series™ TinyCalc™ Gmax™ CorePOWER™ RapidConfigure™ TinyLogic® GTO™ CROSSVOLT™ ™ TINYOPTO™ CTL™ IntelliMAX™ TinyPower™ Current Transfer Logic™ Saving our world, 1mW/W/kW at a time™ ISOPLANAR™ TinyPWM™ DEUXPEED® Marking Small Speakers Sound Louder SignalWise™ TinyWire™ Dual Cool™ SmartMax™ and Better™ TranSiC® SMART START™ EcoSPARK® MegaBuck™ TriFault Detect™ Solutions for Your Success™ EfficentMax™ MICROCOUPLER™ TRUECURRENT®* SPM® ESBC™ MicroFET™ μSerDes™ STEALTH™ MicroPak™ ® SuperFET® MicroPak2™ SuperSOT™-3 MillerDrive™ Fairchild® UHC® SuperSOT™-6 MotionMax™ Fairchild Semiconductor® Ultra FRFET™ SuperSOT™-8 Motion-SPM™ FACT Quiet Series™ UniFET™ SupreMOS® mWSaver™ FACT® VCX™ SyncFET™ OptoHiT™ FAST® VisualMax™ Sync-Lock™ OPTOLOGIC® FastvCore™ VoltagePlus™ OPTOPLANAR® ®* FETBench™ XS™ FlashWriter® * ® FPS™