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Advances in Natural and Applied Sciences, 7(2): 117-125, 2013
ISSN 1995-0772
This is a refereed journal and all articles are professionally screened and reviewed
ORIGINAL ARTICLE
Investigation on Cascaded H-Bridge Multilevel DSTATCOM for Mitigation of Load
Current Harmonics in Distribution Utilities
1
S.Suresh, 2Dr.N.Devarajan
1
2
Department of EEE, Kalaignar Karunanidhi Institute of Technology, Coimbatore, Tamilnadu, India,
Department of EEE, Government College of Technology, Coimbatore, Tamilnadu, India,
S.Suresh, Dr. N. Devarajan: Investigation on Cascaded H-Bridge Multilevel DSTATCOM for
Mitigation of Load Current Harmonics in Distribution Utilities
ABSTRACT
The most efficient solution for mitigating load current harmonics in electric power systems have been
recognized as STATCOM. The power quality improvement in the distribution sides are extensively investigated
by DSTATCOMs. The principle of the carrier phase-shifted pulse-width modulation (CPS-PWM) and the
mathematical model of the CHB-DSTATCOM are presented in this paper. The simulation results obtained from the
MATLAB are presented and evaluated, which verifies the validity and effectiveness of the devised control
scheme.
Key words: DSTATCOM, Cascaded H-Bridge, THD, Carrier Phase Shifted PWM.
Introduction
The harmonics due to the nonlinear loads causes indicative voltage fluctuations; sag/swell and temporary
interruptions The STATCOM are the most suitable solution for mitigating the load current harmonics. Cascaded
H-bridge (CHB) inverter is used for high-power medium-voltage power quality conditioner applications
because of its modularity and flexibility in manufacturing. The dc-link voltage control scheme is split into two
parts, i.e., the average voltage controller and voltage balancing controller (Han, Y., et al., 2009; Malinowski,
M., et al., 2010). Simulation results obtained from the MATLAB are provided, which verifies
effectiveness of the devised control scheme (Kouro, S., et al., 2010).
2. Carrier Phase-Shifted PWM Principles:
Fig.1 shows the circuit diagram of the five-level cascaded multilevel DSTATCOM. In Fig.1, Lg and
Rg indicate the line impedance. Each H-bridge includes four IGBT switches with anti-parallel diodes and a dclink capacitor.
Thus the output voltages of the CHB-DSTATCOM can be derived as VaN=Va1+Va2. Assuming
Vdc1=Vdc2=Vdc in steady state and the unipolar modulation scheme is adopted in the PWM process, thus
each H-bridge would produce three voltage levels -Vdc, 0, Vdc. With reference to the upper bridge, it is
possible to set Va1= +Vdc by turning on switches S11 and S14 and Va1=-Vdc by turning on switches S12 and
S13. Moreover, it is possible to set Va1=0 by turning on either S11 and S12 or S13 and S14, the lower bridge
operates in a similar manner. Thus five distinct voltage levels can be synthesized at the ac terminals. It is
worth noticing that, the switching states of Sx1, Sx2 (x=1, 2) must be complementary to those of Sx3, Sx4
(x=1,2) in order to avoid short circuit of the H-bridges (Han, Y., et al., 2009).
To obtain five level output voltage at the ac terminal, the carrier signals utilized in each cell must be
phase shifted by 90 degree in case of two H-bridge module configuration. Fig.2 shows the waveforms of
the modulation signal, phase-shifted carriers and the output multilevel voltage of the CHB-DSTATCOM.
3. The Model Derivation of CHB DSTATCOM:
With the reference to the fig.1, the switching functions of the multilevel CHB-STATCOM can be derived
as,
Corresponding Author: S.Suresh, Department of EEE, Kalaignar Karunanidhi Institute of Technology, Coimbatore,
Tamilnadu, India,
Mobile: +91-9500680004; E-mail: [email protected]. 118
Adv. in Nat. Appl. Sci., 7(2): 117-125, 2013
f1 =S11.S14 -S12 .S13 


f 2 =S21.S24 -S22 .S23 
(1)
The value of fx (x=1, 2) indicates the dynamic process of charging and discharging between the dc-link
capacitors C1 and C2. Supposing the DSTATCOM current ic is positive, then the capacitor Cx (x=1, 2) is charging
if fx=1, discharging if fx =-1, and not undergoing any of these processes if fx=0 (Han, Y., et al., 2010).
Complementary phenomenon appears if the inverter current is negative. The following assumptions are
made for deriving the model of the cascaded H-bridge inverters:
a) The grid is assumed to be AC voltage source;
b) The losses of the multilevel DSTATCOM are categorized as effective series loss and parallel loss.
The series loss and interfacing inductor loss are represented as equivalent series resistance (ESR). Parallel
losses are represented as shunt connected resistances across the dc-link capacitors, corresponding to the active
power loss of the H-bridge, including blocking loss, capacitor loss and absorbing circuit loss, etc.
The differential equation describing the dynamics of the coupling inductor between the cascaded H-bridge
inverter and the grid is derived as
vsa =Ri c +L
dic
+f1vdc1 +f 2 vdc2
dt
(2)
where the variable Vsa represents grid voltage at the point of common coupling (PCC) [see Figure 1], L
represents the inductance of the coupling inductor and R represents the equivalent series resistance. The
variables Vdc1 andVdc2 are the actual voltages across the dc-link capacitors of the cascaded H-bridge inverter,
which may not equal to the reference voltage during dynamic process. According to the Kirchhoff’s law, the
currents flowing into the dc-link capacitors C1 and C2 can be expressed as:
Fig. 1: Block diagram of the cascaded H-bridge multilevel DSTATCOM
Fig. 2: Simulation result of CHB-DSTATCOM.(a)The waveform of modulated signal,phase shifted carrier 119
Adv. in Nat. Appl. Sci., 7(2): 117-125, 2013
dv dc1
v dc1 

i c1 =C1 dt =i o1 -i R1 =f1i1 - R 

1 


dv
v
dc1
dc2 
i =C
=i
-i
=f
i
o2 R2
2 1
 c2 2 dt
R 2 
(3)
Where R1 and R2 are the equivalent resistance of each H bridges, representing the parallel losses. The
variables io1 and io2 represent the total dc-link current and iR1 and iR2 represent the currents in the dc-link
resistance of the individual H-bridge module. Let the vector of state variables as X2=[ ic, vdc1, vdc2]T and U2= [vsa,
0, 0]T, as input vector, rearranging Equations.(1)-(3), the state equations can be rewritten in the compact matrix
form as
X 2 =A 2 X 2 +B2 U 2
(4)
Where,
 R
 L
 f
A2 =  1
 C1
 f2

 C2
f1
L
1
R1C1
-
0
f2 

L 

0  &

1 

R 2 C2 
-
Fig. 3:The equivalent circuit diagram of CHB-STATCOM
1
L

B2 =  0
0



0 0

0 0
0 0


4. The Analysis of Power Balancing Mechanism:
The equivalent circuit of the multilevel CHB-STATCOM for the steady-state power balance analysis is
shown in the Fig.3 (Suresh, S., et al., 2012)
 va1 =f1vdc1 ,p R1 =vdci R1 


 va2 =f 2 vdc2 ,p R2 =vdci R2 
(5)
The above equation represents the individual H-bridge inverters by AC voltage sources va1 and va2.where
pR1 and pR2 represents the active power consumed by the effective resistance across the dc-link capacitors. For
the sake of brevity, the equivalent resistance of the coupling inductor is neglected; hence Eq. (2) can be
rewritten as
vsa =L
dic
+va1+ va2
dt
(6)
From Fig.1 and Fig.3, the power balancing equations of the CHB-DSTATCOM can be
2
d v dc1
(
)+p R1
dt 2
d v 2 dc 2
derived as va 2 ic  C 2
(
)  pR 2
dt 2
v a1i c =C1
(7)
(8)
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Adv. in Nat. Appl. Sci., 7(2): 117-125, 2013
The behavior of the CHB-DSTATCOM is characterized by the inductor current dynamics and the dc-link
capacitor voltage dynamics. The power balance between the two H-bridge inverters depends on the dc link
voltages and the individual modulation signals. To better illustrate the mechanism of power exchange between
the two modules, the phasor diagram of the output voltages and current of the CHB-DSTATCOM is given in
Fig.4. In the analysis, it is assumed that vaN is calculated in such a way that ic is 90 degree phase shifted with
respect to vsa. The angles θ1 and θ2 represent the phase shifts of the output voltages va1 and va2 with respect to vsa,
leading to a reactive power exchange between the individual H-bridge inverter with the grid.
Fig. 4: Phasor diagram of voltage and current In the phasorial diagram (Fig.4), the maximum output voltages in root-mean square (rms) values of each H
bridge can be calculated as:
4
4
(9)
va1m 
vdc1, va 2 m 
vdc 2
 2
 2
The reactive power injected by each H-bridge inverter to the grid depends on the value of the capacitor
voltage in the cell and the control signal modulated by each module. To ensure stable operation of the CHBDSTATCOM, both cells must be utilized to synthesize the output voltage vaN.Fig.5 shows the red marked area
the possible points to achieve the desired output voltage. Any point outside of this region makes the system
unstable since the output voltage of the CHB-DSTATCOM cannot be modulated with those values of the dclink capacitor voltages. Furthermore, as shown in Fig.5, the projections of va1 and va2 over vsa are always
positive. Hence, the reactive powers in both converters are positive, indicating that both inverters of
CHBDSTATCOM inject reactive power to the grid simultaneously. Moreover, it is not possible to find a point
where one of the cells injects reactive power and, at the same time, the other cell absorbs reactive power from
the grid. Fig.6 shows that, for a given total amount of reactive power to be supplied or absorbed by the H-bridge
inverter, the reactive power sharing by each cell has to be between a minimum and maximum value to achieve a
stable operation of the CHB-inverter.
Fig. 5: The stable control area of the CHB-DSTATCOM
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Adv. in Nat. Appl. Sci., 7(2): 117-125, 2013
Fig. 6: The diagram of maximum and minimum reactive power limits.
Fig.6(a) shows the minimum reactive power supplied by the first inverter, which corresponds to the
minimum reachable length of the projection of va1 over vsa represented by va1q,min. As the amount of reactive
power supplied by the CHB-DSTATCOM is fixed, this value is related with the maximum reactive power that
is supplied to the second cell, shown in Fig6(a) as va2q,max, which is the maximum reachable length of the
projection of va2 over vsa. In the same way, the values for the maximum reactive power supplied by the first
inverter va1q,max and the minimum reactive power supplied by the second inverter va2q,min can also be illustrated,
as shown in Fig.6(b).
5. Controller Strategy:
The control block diagram can be synthesized from the analysis of power balancing mechanism. Fig.7
shows the control algorithm which consists of the reference current generation (RCG) unit, the phase-locked
loop (PLL), the current loop controller (CC), the average dc-link voltage controller (AVC) and the dc voltage
balancing controller (VBC). Equal reactive power sharing of the two cells by dynamically exchanging active
power within the two inverters is achieved by voltage balancing scheme. The outputs of the AVC controller (p1
and p2) are applied to the VBC controller to regulate the difference of dc voltages. The phase angle of the grid
voltage is utilized to achieve the active and reactive power balancing for the individual H-bridge modules.
Hence synchronization of the multilevel CHB-DSTATCOM to the grid is essential to ensure its stable
operation.
Fig. 7: The block diagram of the control algorithm
An arbitrary grid voltage can be represented as:
N
vsa (t )  V1 sin(0 t  1 )   Vn sin(n0 t  1 )
(10)
n2
The dc offset is neglected for the sake of brevity. The phase angle of the fundamental component voltage
can be expressed as φ1=Δθ1+θ1, where θ1 and Δθ1 represent the estimated phase angle of the fundamental
grid voltage and the estimation error, respectively obtained from the Adaline based PLL(APLL). Therefore,
the phase angle of the nth order harmonic component can be expressed as
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Adv. in Nat. Appl. Sci., 7(2): 117-125, 2013
n0t  n  n(0t  1 )  n  n1
n(0t  1 )  n1  (n  n1 )
(11)
Where φn is the initial phase angle of the nth order harmonic component. Substituting Eq.(11) back
into (10), rearranging terms, we get (Han, Y., et al., 2009)
vsa (t ) = V1 cos(Dq1 ) sin(w0t + q1 )
+V1 sin(Dq1 ) cos(w0t + q1 )
N
+å {Vn cos( nDq1 + (jn - nj1 )) sin[ n(w0t + q1 )]}
(12)
n= 2
N
+å {Vn sin( nDq1 + (jn - nj1 )) cos[ n(w0t + q1 )]}
n= 2
From (12), it can be deduced that the original signal denoted by Eq.(10) can be regenerated by adjusting
the coefficients Vncos(nΔθ1+(φn-nφ1)), Vnsin(nΔθ1+(φn-nφ1)) (n=1, …, N), even though the phase angle of
the original signal is unknown.
The weight vector w denotes the coefficients of the Corresponding trigonometric functions. From the
above definition, the fundamental grid voltage can be expressed as,
Y = W T X
where Y is the estimated output of the fundamental grid voltage by using the lms-based weights
estimation scheme. The vector W and X corresponding to the weight vector and the input vector, respectively,
are represented as
W





X


 [V1 cos(1 ), V1 sin(1 ),...,


Vn cos(n1  (n  n1 )),


Vn sin(n1  (n  n1 ))]

[11 , 12 ,..., n1,n 2, ]


 [sin(0t  1 ), cos(0t  1 )

sin[n(0t  1 )], cos[n(0t  1 )]]T 
(13)
From eq.(13), the weights of the fundamental frequency component are denoted as ω11 and ω12, hence the
phase estimation error is denoted by δθ1. By using a properly designed closed-loop control system, ∆ θ1 can
be regulated to zero. The per unit representation of the weight ω12 is utilized as the input signal for the loop
filter (LF) of the APLL is derived as:
12pu 

12
112  122
V1 sin( 1 )
V12 sin 2 ( 1 )  V12 cos 2 (1 )
(14)
 sin(1 )
In APLL, the frequency and phase angle of the fundamental grid voltage is recursively updated by the
loop filter (LF) and voltage controlled oscillator (VCO) this is the main difference between the ADALINE
algorithm and the proposed APLL ,the frequency and phase angle signals utilized in the ADALINE weights
updating process are assumed to be constant. The weights updating process of APLL is similar to the adaptive
linear neural network (ADALINE), which is based on the recursively searching the optimal point of the
quadratic cost function, i.e., the least square (LS) error.
5.2 Current Loop Controller:
Current loop controller for the CHB-DSTATCOM, Proportional-Integral (PI) regulator is represented by
transfer function C(Z),
(15)
Where Kp and Ki denote the proportional and integral gains. The plant of the current controller is the
coupling inductor, and gp(s)=1/(L0s+R0), where L0 and R0 denote the nominal parameters. Eq.(6) can be
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Adv. in Nat. Appl. Sci., 7(2): 117-125, 2013
discretized using the zero-order hold (ZOH) method, as
(16)
Where ‘m’ denotes the equivalent sample of control Delay. Neglecting the effect of the grid voltage
and consider m=1, the open loop transfer function of the current loop controller can be derived as
cc
Gopen
( z) 
k pTs
L0
.
z  (1  (kiTs ) / k p ))
z ( z  1)[ z  (1  R0Ts / L0 ))]
(17)
Hence, the closed-loop transfer function can be easily derived from eq.(17)
5.3 Voltage Balancing Controller:
Fig. 8: The MATLAB block diagram of the system
The active power exchange between the two H-bridge inverters and equal reactive power sharing between
two cells is achieved by voltage balancing controller (VBC) and average voltage controller (AVC), is designed
to regulate the total active power balance between the CHB-DSTATCOM with the grid.
6. Simulation Results and Discussions:
A simulation using MATLAB is done to evaluate the effectiveness of the devised control scheme.
Figure 8 shows the MATLAB model of the proposed system. The parameters of this system are: Lg=50µh,
Rg=20mΩ, L=1.5mh, R=50mΩ, and the nominal dc-link parameters are C1=C2=2000µf, R1=R2=39000Ω,
the grid voltage Vsa=220 V(rms), the target inverter dc-link voltage is 200v. The initial dc-link voltages are
set to 180v and 220v, respectively.
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Adv. in Nat. Appl. Sci., 7(2): 117-125, 2013
Fig. 9: Waveform of load voltage and load current
Figure 9 and figure 10 shows the load voltage & load current without STATCOM operation
and FFT analysis of the load current. The harmonics measured in the load current is 24.62%. The
grid current tracks its reference within two fundamental cycles, which demonstrates the validity of the
control scheme.
Fig.10: Load current FFT analysis
Fig.11:Waveform of source voltage and source current
Fig. 12: FFT analysis of source current
Figure 11 and figure 12 shows the source voltage & source current with STATCOM operation
and FFT analysis of the load current. When the STATCOM is connected to the grid, harmonics
content in the load current was mitigated with a total harmonic distortion of 4.18% which is less than the
current harmonic limitation of 5% as per the IEEE standard 519-1992. The power-stage parameters deviation
is quite small hence a sufficient stability margin can also be achieved.
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Adv. in Nat. Appl. Sci., 7(2): 117-125, 2013
7. Conclusion:
The optimized control scheme for the cascaded H-bridge (CHB) DSTATCOM which is based on
multilevel carrier-shifted pulse-width modulation (CSPWM) and the mechanism of power balancing among
individual h-bridges inverters is presented in this paper the validity of the devised control scheme is validated by
the simulation results from MATLAB.
References
Han, Y., L. Xu, G. Yao, L. Zhou, M.M. Khan, C. Chen, 2009. Flicker mitigation of arc furnace load using
modified p-q-rmethod, Przeglad Elektrot., 85(1): 225-229.
Malinowski, M., K. Gopakumar, J. Rodriguez, M.A. Pérez, 2010. A survey on cascaded multilevel inverters,
IEEE Trans. Ind. Electron., 57(7): 2197-2206.
Kouro, S., M. Malinowski, K. Gopakumar, J. Pou, L. G. Franquelo, B. Wu, J. Rodriguez, M.A. Perez, J. I.
Leon, 2010. Recent advances and industrial applications of multilevel converters, IEEE Trans. Ind.
Electron., 57(8): 2553-2580.
Han, Y., L. Xu, M.M. Khan, G. Yao, L. Zhou, C. Chen, 2009. A novel synchronization scheme for gridconnected converters by using adaptive linear optimal filter based PLL (ALOF-PLL), Simulation
Modeling Practice and Theory, 17(7): 1299-1345.
Han, Y., L. Xu, G. Yao, L. Zhou, M.M. Khan, C. Chen, 2010. State-Space Averaging (SSA) Technique for
Modeling of the Cascaded H-Bridge Multilevel DSTATCOMs and Active Filters, International Review
of Electrical Engineering-IREE, 4(5): 744-760.
Suresh, S., Dr. N. Devarajan, V. Rajasekaran, 2012. Modeling and Analysis of Shunt Hybrid Filter to Enhance
Power Quality for Mitigation of Load Current Harmonics, Advances in Natural and Applied Sciences,
6(8): 1276-1282.