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UM0858
User manual
Getting started with STEVAL-PCC011V1,
ST802RT1 FX mode Ethernet PHY demonstration kit
1
Introduction
The STEVAL-PCC011V1 demonstration kit was designed to evaluate the ST802RT1 FX
mode. This device is a Fast Ethernet physical layer (PHY) interface which supports 100
Base-FX applications. The PHY provides a Media Independent Interface (MII) and Reduced
Media Independent Interface (RMII) for easy attachment to a 10/100 Media Access
Controllers (MAC). The demonstration board features jumpers, test points and connectors to
test the features provided by the ST802RT1 FX mode Ethernet PHY.
To quickly evaluate the microcontroller and physical layer, the device can be connected to
the STM32F107 controller demonstration board through an additional header connector.
The controller board is preprogrammed with a web server demonstration. The STM32F107
controller demonstration board is not part of the STEVAL-PCC011V1 package but has to be
purchased separately. The only way to get it is to purchase additionally STEVALPCC010V1.
The board can be equipped with a dedicated digital connector compatible to the Spirent®
Communications SmartBits 200/2000 (SMB-200/ SMB-2000) analysis system.
Figure 1.
ST802RT1 FX mode Ethernet PHY demonstration board - top view
This document refers to STEVAL-PCC010V1 user manual UM0819 which provides
a complete description of the ST802RT1 Fast Ethernet physical layer interface in TX mode.
For a complete description of the ST802RT1 transceiver, please refer to the datasheet.
November 2009
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Contents
UM0858
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2
Board key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
General system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4
Package content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Board layout - ST802RT1 FX mode Ethernet PHY demonstration
board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6
Configuration and functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1
7
8
6.1.1
Bootstrap options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1.2
Solder bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1.3
RESET button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1.4
LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1.5
Test point MCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6.1.6
Power supply and power consumption measurement . . . . . . . . . . . . . . 13
FX mode functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.1
LVPECL - low voltage pseudo emitter coupled logic . . . . . . . . . . . . . . . . 14
7.2
Utilization of ST802RT1 FX mode Ethernet PHY with AFBR-5803 optical
transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1
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Configuration and functionality of ST802RT1 FX mode Ethernet PHY
demonstration board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Connectors of the ST802RT1 FX mode Ethernet PHY demonstration
board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1.1
MII/RMII debugging connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8.1.2
MII/RMII connector P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8.1.3
Optical transceiver U2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
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UM0858
Contents
Appendix A ST802RT1 FX mode Ethernet PHY demonstration board
- BOM and schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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List of tables
UM0858
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
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Auto-negotiation jumper settings for evaluation purpose only . . . . . . . . . . . . . . . . . . . . . . 11
PHY MII address jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power-down jumper setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Loopback jumper setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MII/RMII jumper settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
MII/RMII interface selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LEDs functionality - alternative 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
LEDs functionality - alternative 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Power supply jumpers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
MII/RMII debugging connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MII/RMII connector P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Optical transceiver connector U2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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UM0858
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
ST802RT1 FX mode Ethernet PHY demonstration board - top view . . . . . . . . . . . . . . . . . . 1
ST802RT1 FX mode Ethernet PHY demonstration kit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Board layout - ST802RT1 FX mode Ethernet PHY demonstration board. . . . . . . . . . . . . . . 9
Jumper configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
ST802RT1- single ended measurement on the TXP line in 100 Base-FX mode . . . . . . . . 14
Recommended schematic for connection of ST802RT1 FX mode with AFBR-5803
optical transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MII/RMII debugging connector J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
MII/RMII connector P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Optical transceiver connector U2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
ST802RT1 FX mode Ethernet PHY demonstration board - schematic - part 1 . . . . . . . . . 20
ST802RT1 FX mode Ethernet PHY demonstration board - schematic - part 2 . . . . . . . . . 21
ST802RT1 FX mode Ethernet PHY demonstration board - schematic - part 3 . . . . . . . . . 22
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Board key features
2
UM0858
Board key features
ST802RT1 FX mode Ethernet PHY demonstration board has the following features:
6/24
●
ST802RT1 FX mode Fast Ethernet physical layer transceiver
●
On-board 3.3 V LDO regulator
●
On-board 25 MHz crystal
●
12 jumpers for bootstrap configuration (MII address, auto-negotiation, loopback, powerdown, MII/RMII configuration)
●
Several GND test points and jumpers for power consumption measurement
●
Connectors
–
20-pin full pitch header connector for debug purposes (compatible to the
STM32F107 controller board)
–
40-pin connector compatible to the Spirent Communications SmartBits 200/2000
(SMB-200/ SMB-2000) analysis system (not assembled)
–
Optical transceiver connector.
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UM0858
3
General system description
General system description
The ST802RT1 FX mode STEVAL-PCC011V1 demonstration board was designed to
evaluate the PHY chip in fiber optics mode. It therefore allows to easily select the PHY boot
options, to evaluate the power consumption of the chip and to attach the device to the
professional test equipment.
The board also allows simple connection to the customer microcontroller or FPGA platforms
by means of the on-board connectors. The board was designed to allow evaluation of MII
and RMII digital communication interfaces.
In addition, the STM32F107 controller demonstration board can extend the ST802RT1 FX
mode demonstration board with STM32™ microcontroller and its embedded MAC. This
allows to evaluate application based on the embedded microcontroller and the Ethernet
PHY in FX mode.
Figure 2.
ST802RT1 FX mode Ethernet PHY demonstration kit
ST802RT1 FX mode
demonstration board
ST802RT1 FX mode
MII / RMII
—
Optical
transceiver
100 Base-FX
AM00647
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Package content
4
UM0858
Package content
The ST802RT1 FX mode Ethernet PHY ST802RT1 demonstration kit includes the following
items:
Hardware content
●
One ST802RT1 FX mode Ethernet PHY demonstration board
Documentation
8/24
●
ST802RT1 product documentation
●
This user manual.
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UM0858
5
Board layout - ST802RT1 FX mode Ethernet PHY demonstration board
Board layout - ST802RT1 FX mode Ethernet PHY
demonstration board
Figure 3.
Board layout - ST802RT1 FX mode Ethernet PHY demonstration board
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Configuration and functionality
6
UM0858
Configuration and functionality
This section describes the functions and configuration of the STM802RT1 FX mode
Ethernet PHY demonstration board.
6.1
Configuration and functionality of ST802RT1 FX mode
Ethernet PHY demonstration board
In this chapter jumper “high” means that the jumper is placed in the position closer to the top
edge of the board and position “low” means that the jumper is placed in the position closer
to the bottom edge of the board as shown by Figure 4.
Figure 4.
6.1.1
Jumper configuration
Bootstrap options
The ST802RT1 FX mode PHY uses many of the functional pins as strap options. The values
of these pins are sampled during hardware reset and power-up. They are used to strap
signals on the device into specific modes of operation. The ST802RT1 FX mode provides
a simple strap options to automatically configure the device to operate in the modes
requiring no device register configuration. All strap pins have a weak internal pull-ups or
pull-downs. To change the default strap value, the strap pins should be connected directly to
VCC or GND with an external 2.2 kΩ resistor. The software reset and power-down through
the power-down pin cannot be used to change the strap configuration.
Auto-negotiation
Auto-negotiation functions are not supported in 100 Base-FX mode. It is possible to change
the HW configuration of the involved pins - see Table 1 for the default settings and check the
board schematic for further possible connections.
10/24
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UM0858
Configuration and functionality
Table 1.
Auto-negotiation jumper settings for evaluation purpose only(1)
Jumper
Description
Default configuration
JP16
AN_1
High
JP17
AN_0
High
JP18
AN_EN
High
1. See functionality of AN_xxx pins in the ST802RT1 documentation.
PHY MII address
The MDIO/MDC serial management interface is used to access the internal registers of the
PHY. The Ethernet MAC must know the PHY address to establish successful
communications with it. Special case is PHY address 0x00. If this address is used as the
bootstrap address during the reset, the 00000 value is latched into the internal receive mode
control register RN14 (0x14h) and the PHY goes also to the isolation mode. It is possible to
change the PHY address by writing the RN14 register when the application is already
running.
Table 2.
PHY MII address jumper settings
Jumper
Description
Default configuration
JP11
MII address 0
High
JP12
MII address 1
Low
JP13
MII address 2
Low
JP14
MII address 3
Low
JP15
MII address 4
Low
Power-down
This pin is an active low input of the PHY and should be asserted low to put the device in
power-down mode. During the power-down mode, TXP/TXN outputs and all LED outputs
are 3-state, and the MII interface is isolated. The power-down functionality is also achievable
by software by asserting bit 11 of register RN00.
Table 3.
Power-down jumper setting
Jumper
Description
Default configuration
JP1
Power-down, if fitted - PHY works normally; if not fitted - PHY is
in power-down mode
Fitted
Loopback
Local loopback passes data internally from the transmitting to the receiving serial analog
logic. There are two ways to enter the internal loopback mode, either writing RN00 register,
bit 14 (MDIO/MDC) or by using bootstrap LPBK pin (VDD - enabled, GND - disabled, through
2.2 kΩ resistor).
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Configuration and functionality
Table 4.
UM0858
Loopback jumper setting
Jumper
Description
Default configuration
JP8
LPBK - loopback; “high” - internal loopback selected (mainly for
debug purposes); “low” - normal operation
Low
MII/RMII mode selection
A strapping option allows setting the operating mode of the MAC data interface. Default
operation (no pull-ups) enables normal MII operating mode. Strapping CF0 “high” will cause
the device to be in RMII.
Table 5.
Jumper
Description
Default configuration
JP9
CF0 - MAC data interface selection
Low
JP10
CF1 - MAC data interface selection
Low
Table 6.
6.1.2
MII/RMII jumper settings
MII/RMII interface selection
CF0 (JP9)
CF1 (JP10)
MII
Low
X
RMII
High
Low
Solder bridges
The SB1 and SB2 solder bridges are used to connect 25 MHz crystal X1 to the ST802RT1
FX mode PHY. They can be removed to disconnect the crystal when external clock signal on
test point MCO is used as the input clock.
6.1.3
RESET button
The RESET button resets the ST802RT1 FX mode PHY to its initial state.
6.1.4
LEDs
By default the LEDs have the following functionality:
Table 7.
12/24
LEDs functionality - alternative 1
LED
Description
Details
LED1
BLINK for activity
JP16 is low
LED2
BLINK for activity
JP16 is high
LED3
ON for 100 Mb
JP17 is low
LED4
ON for 100 Mb
JP17 is high
LED5
ON for link up / OFF for link down
JP18 is low
LED6
ON for link up / OFF for link down
JP18 is high
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UM0858
Configuration and functionality
Alternatively it is possible to change the meaning of LED1 - LED6 by writing the PHY
register RN1B [0d27, 0x1B]:
Table 8.
6.1.5
LEDs functionality - alternative 2
LED
Description
Details
LED1
ON for full duplex, BLINK for collision
JP16 is low
LED2
ON for full duplex, BLINK for collision
JP16 is high
LED3
ON for 100 Mb
JP17 is low
LED4
ON for 100 Mb
JP17 is high
LED5
ON for link up and BLINK for activity / OFF for link down
JP18 is low
LED6
ON for link up and BLINK for activity / OFF for link down
JP18 is high
LED8
Is used for indicating that the board is powered
—
Test point MCO
The test point MCO can be used to connect external clock signal to the clock input of the
STM802RT1A PHY in MII mode. Note that the 25 MHz crystal X1 has to be disconnected
from the ST802RT1 FX mode PHY by removing solder bridges SB1 and SB2 before
connecting any external signal to the test point.
6.1.6
Power supply and power consumption measurement
The board was designed to be powered from the +5 V DC supply voltage coming from the
P1 header connector or by means of JP20. On-board jumpers allow to measure the actual
current power consumption of the Ethernet PHY chip and the power consumption of the
peripheral components connected to the PHY. The typical total power dissipation of the
board is 500 mW.
Table 9.
Power supply jumpers
Jumper
Description
Details
JP3
Disconnects/connects the supply voltage from/to the optical transceiver (allows to
measure power consumption of the optical transceiver)
Fitted
JP4
Disconnects/connects the digital domain supply voltage from the peripheral
components around the PHY from/to the power supply
Fitted
JP5
Disconnects/connects the digital domain supply voltage of the PHY from/to the
power supply
Fitted
JP6
Disconnects/connects the analog domain supply voltage from the peripheral
components around the PHY from/to the power supply
Fitted
JP7
Disconnects/connects the analog domain supply voltage of the PHY from/to the
power supply
Fitted
JP19
Connects the output of the on-board voltage regulator (U2) to the rest of the
application board
Fitted
JP20
Connects the external power supply input (from pin 2 of connector P1) to the
input of the on-board voltage regulator (U3)
Fitted
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FX mode functionality
7
UM0858
FX mode functionality
In this section you can find a short description of the functionality of the ST802RT1 Ethernet
PHY in 100 Base-FX mode. ST802RT1 provides a low voltage pseudo ECL interface
suitable for driving a fiber optic transceiver - communication between the PHY and the
transceiver. The AFBR5803 optical transceiver allows to connect to the multimode fiber
backbones.
7.1
LVPECL - low voltage pseudo emitter coupled logic
The ST802RT1 provides a low voltage pseudo ECL (LVPECL) interface suitable for driving
a fiber optic transceiver. LVPECL is a differential signaling system mainly used in high speed
systems. It requires a positive 3.3 V supply voltage. The LVPECL logical low level
(LVPECLLOW) is approximately VCC–1.7 V, the LVPECL logical middle level (LVPECLMID)
is approximately VCC–1.3 V and the LVPECL logical high level (LVPECLHIGH) is
approximately VCC–0.9 V.
Figure 5 shows a typical waveform of the low voltage PECL signal measured on the TXP pin
of ST802RT1 in FX mode. The TXN signal would be inverted exactly with the reference to
LVPECLMID voltage level.
Figure 5.
14/24
ST802RT1- single ended measurement on the TXP line
in 100 Base-FX mode
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UM0858
7.2
FX mode functionality
Utilization of ST802RT1 FX mode Ethernet PHY with
AFBR-5803 optical transceiver
The following ST802RT1 PHY pins must be connected with the optical transceiver with
respect to the LVPECL voltage levels.
●
SDP - positive signal detect - indicates the optical link status and is usually bonded out
from the optical receiver.
●
SDN - negative signal detect - pin SDN can be permanently connected to LVPECLMID
because it is not usually bonded out from the optical transceiver
●
TXP, TXN - differential transmit outputs
●
RXP, TXN - differential receive inputs
Figure 6 shows the recommended connections of the Ethernet PHY ST802RT1 and the
optical transceiver AFBR-5803. The SDN pin is connected to the voltage divider
represented by resistors R6 and R7 and is not directly connected to the optical transceiver.
Its voltage level is equal to LVPECLMID, that is 2.03 V.
Place a 100 Ω termination resistor directly across the TDP to TDN inputs of the optical
transmitter. Connect a 100 Ω resistor between TXN and VCCA and between TXP and VCCA
to achieve the pseudo emitter coupled logic (PECL) levels for the optical transmitter.
The RDN, RDP and SDP lines are connected to a resistor net with respect to the LVPECL
logic, impedance characteristic of the optical transceiver and PHY and the recommended
schematic for the used optical transceiver.
Figure 6.
Recommended schematic for connection of ST802RT1 FX mode
with AFBR-5803 optical transceiver
VCCA
VCCA
R6
750 Ω
VCCA
R8
910 Ω
VCCA
R10
130 Ω
VCCA
R12
130 Ω
SDN
VCCA
R15
100 Ω
R14
100 Ω
R16
100 Ω
R7
1.2 KΩ
GND
AFBR_VCC_1
AFBR_VCC_2
U2
AFBR-5803Z 5
6
RDP
2
RDN
3
SDP
4
R9
100 Ω
GND
R11
82 Ω
GND
TDN
7
TDP
8
R13
82 Ω
GND
VCC
VCC
TD V
EE
VEE
RD
RD
SD
TD
1
9
GND GND
AM00648
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Connectors
UM0858
8
Connectors
8.1
Connectors of the ST802RT1 FX mode Ethernet PHY
demonstration board
8.1.1
MII/RMII debugging connector J1
Figure 7.
MII/RMII debugging connector J1
1 2 3 4
5 6
8 9 10 11 12 13 14 15 16 17 18 19 20
42
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
AM00639
Table 10.
MII/RMII debugging connector J1(1)
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
+5 V
12
FXCLK
23
GND
34
GND
2
MDIO
13
FXEN
24
GND
35
GND
3
MDC
14
FXD_0
25
GND
36
GND
4
RXD_3
15
FXD_1
26
GND
37
GND
5
RXD_2
16
FXD_2
27
GND
38
GND
6
RXD_1
17
FXD_3
28
GND
39
GND
7
RXD_0
18
COL
29
GND
40
Not connected
8
RXDV
19
CRS
30
GND
41
GND
9
RXCLK
20
Not connected
31
GND
42
GND
10
RXER
21
+5 V
32
GND
11
FXER
22
GND
33
GND
1. This connector is not assembled by manufacturing.
16/24
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UM0858
8.1.2
Connectors
MII/RMII connector P1
Figure 8.
MII/RMII connector P1
2
4
6
8 10 12 14 16 18 20
1
3
5
7
9 11 13 15 17 19
AM00640
Table 11.
8.1.3
MII/RMII connector P1
Pin
Signal
Pin
Signal
Pin
Signal
Pin
Signal
1
GND
6
RXD3
11
FXER
16
FXD0
2
+5 V
7
RXD0
12
RXER
17
FXD3
3
MDC
8
RXD1
13
FXEN
18
FXD2
4
MDIO
9
RXCLK
14
FXCLK
19
CRS
5
RXD2
10
RXDV
15
FXD1
20
COL
Optical transceiver U2
Figure 9.
Optical transceiver connector U2
5
2
3
4
7
8
6
V
VCC
RD CC
RD
SD
TD
TD V
EE
VEE
1
9
AM00649
Table 12.
Optical transceiver connector U2
Pin
Description
Pin
Description
1
GND
2
Receive data positive
3
Receive data negative
4
Signal detect
5
VCC (+3.3 V)
6
VCC (+3.3 V)
7
Transmit data negative
8
Transmit data positive
9
GND
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ST802RT1 FX mode Ethernet PHY demonstration board - BOM and schematic
Appendix A
Table 13.
ST802RT1 FX mode Ethernet PHY
demonstration board - BOM and schematic
Bill of material
Designator
Quantity
Description
Value
Order
RESET
GM Electronic®:
630-121
Farnell: 9471898
B1
1
Push button
(DT2112C)
C1, C2
2
Capacitor
10 nF
Farnell: 1709948
C3, C4
2
Capacitor
12 pF
Farnell: 1462447
C5, C6, C7, C9, C11,
C14, C15, C18, C20
9
Capacitor
100 nF
Farnell: 4532004
C8, C12
2
Capacitor
Murata:
1 µF / X5R Murata
GRM188R60J105KA01
GRM188R60J105KA01
Farnell: 1710296
C13, C16, C19, C21
4
Polarized
capacitor
10 µF / tantalum
Farnell: 1213794
D1
1
Schottky diode
STPS160A /
STPS2L40U
STMicroelectronics™:
STPS2L40UF
J1
1
Plug assembly,
40-pin connector
Connector 40
Tyco Electronics:
174218-2;
Fujitsu:
FCN-238P040-G/F
J2, J8
2
1-pin header,
2 mm banana
receptacle
2MM_REC
J3, J4, J5, J6, J7
5
1-pin header
GND
JP3, JP6, JP7, JP1,
JP4, JP5, JP19,
JP20
8
2-pin jumper wire Jumper
Farnell: 1593411
JP8, JP9, JP10,
JP11, JP12, JP13,
JP14, JP15, JP16,
JP17, JP18
11
3-pin jumper wire Jumper3
Farnell: 1593412
L1, L2, L3, L4
4
Ferrite bead
NFE31PT222Z1E9L
Murata
Farnell: 9528172
LED1, LED2
2
LED
Yellow
Farnell: 1226420
LED3, LED4, LED8
3
LED
Red
Farnell: 1226392
LED5, LED6
2
LED
Green
Farnell: 1226373
P1
1
Header, 20-pin,
dual row
Header 10 x 2
Farnell: 1593446
R1
1
Resistor
5.6 KΩ
Farnell: 1514773
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UM0858
Not
assemble
J1
J2, J8
Farnell: 1593411
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UM0858
Table 13.
ST802RT1 FX mode Ethernet PHY demonstration board - BOM and schematic
Bill of material (continued)
Designator
Quantity
Description
Value
Order
R2
1
Resistor
91 KΩ
Farnell: 1646361
R3, R4
2
Resistor
10 KΩ
Farnell: 1601277
R5
1
Resistor
1M NA
Farnell: 1631320
R6
1
Resistor
750 Ω
Farnell: 1399909
R7
1
Resistor
1.2 KΩ
Farnell: 1632396
R8
1
Resistor
910 Ω
R9, R14, R15, R16
4
Resistor
100 Ω
R10, R12
2
Resistor
130 Ω
R11, R13
2
Resistor
82 Ω
R17, R18, R19, R20,
R21, R22, R23, R24
8
Resistor
2.2 KΩ
Farnell: 1632417
R25
1
Resistor
330 Ω
Farnell: 1646224
R26, R28, R30
3
Resistor
2 KΩ
Farnell: 1632414
R27, R32
2
Resistor
470 Ω
Farnell: 9367659
R29
1
Resistor
220 Ω
Farnell: 1646159
SB1, SB2, SB3
3
Soldering bridge
Soldbridge
U1
1
10 / 100 Fast
Ethernet 3.3 V
transceiver
ST802RT1 FX mode
ST:
ST802RT1 FX mode
U2
1
Fiber optic
transceiver
Avago Technologies:
AFBR-5803Z
Farnell: 9450025
U3
1
Linear regulator
LD1117S33
ST: LD1117S33
X1
1
Epson® Crystal:
FA-238
25 MHz
Farnell: 1712818
Jumper
19
JUMP-SW OPEN JUMP-SW OPEN
BLACK
BLACK
Not
assemble
R5
GME: 832-140;
Farnell: 4218152
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GND
2
TXEN
6
7
8
9
TXD_ 1
TXD_ 2
TXD_ 3
PWRDWN
GND
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RDN RDP
IREF
GND GND
TDP TDN
GND
SDP
RESET
MDIO
LED_ACT/AN1
LED_SPEED/AN0
LED_LINK/AN_EN
IREF GNDA
RXN GNDA
GNDA
VCCA
VCCA
RXP TXP TXN GNDA
ST802RT1 FX mode
VCCA_CORE
GND
34
33
26
27
28
25
29
30
OVDD 32
MDC 31
GND
X2
DVDD 36
X1 35
RX_CLK
RXDV/MII_CFG0
CRS/TXD4
RXERR/RXD4
SDN
RXD3/PHYADDR4
DVDD
41 48 40 39 38 37
13 14 15 16 17 18 19 20 21 22 23 24
VCCA
RESERVED
RESERVED
PWRDWN/MDINT
TXD3/MII
_CFG1
TXD2/SCLK
TXD1
TXD0
VCCA
GNDA
TX_EN
VCCA_CORE
12
11
10
5
VCCA_CORE
TXD_ 0
4
3
1
TXCL K
47 46 45 44 43 42
GND
COL/PHYADDR0
RXD0/PHYADDR1
RXD1/PHYADDR2
RXD2/PHYADDR3
TX_CLK/LPBK_EN
U1
ST802RT1
FX mode
SDN RXER
CRS
RXDV
RXCLK
DVDD_CORE
RXD_2 RXD_3
RXD_1
RXD_0
COL
GND
GND
RESET
GND
C1
10 nF
R3
10 KΩ
DVDD
GND
1
2
B1
RESET
LED_LINK/AN_EN LE D_LI NK
LED_SPEED/AN0
LED_SPEED
LED_ACT/AN1
LE D_AC T
SDP
RESET
MDIO
DVDD_CORE
MDC
GND
X2
C2
10 nF
GND
R4
10 KΩ
DVDD_CORE
X1
PWRDWN
JP1
DVDD
AM00650
ST802RT1 FX mode Ethernet PHY demonstration board - BOM and schematic
UM0858
Figure 10. ST802RT1 FX mode Ethernet PHY demonstration board - schematic - part 1
+5 V
42
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
+5V
MDIO
MDC
RXD_3
RXD_2
RXD_1
RXD_0
RXDV
RXCLK
RXER
TXER
TXCLK
TXEN
TXD_0
TXD_1
TXD_2
TXD_3
COL
CRS
R2
91 KΩ
Doc ID 16756 Rev 1
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2
4
6
8
10
12
14
16
18
20
Header 10 x 2
1
3
5
7
9
11
13
15
17
19
P1
100 nF
C9
GND
GND
TXD_3
COL
AFBR_VCC_1
SB3
TXCLK
RXD_3
RXD_2
RXD_1
RXD_0
RXDV
C6
C7
GND
SDP
GND
1
X2
3.3 V
GND
R13
82 Ω
3.3 V
3
2
1 MΩ
25 MHz
TSX-3225
/ FA-238
R5
4
X1
5
C4
12 pF
SDN
AM00651
GND
R7
1.2 KΩ
R6
750 Ω
VCCA
GND
9
1
GND
VEE
VCC
6
VEE
VCC
SB2
TD
TD
SD
RD
RD
GND
GND
X1
8
7
4
3
2
AFBR-5803Z
U2
AFBR_VCC_1 AFBR_VCC_2
R14
100 Ω
VCCA
100 Ω
R16
R15
100 Ω
VCCA
1
TDP
TDN
R12
130 Ω
GND
R11
82 Ω
R10
130 Ω
VCCA VCCA
JP3
R9
100 Ω
RDN
RDP
R8
910 Ω
GND
C19
1 µF/X5R
C8
GND
NFE31PT222Z1E9L
L3
GND
C18
100 nF
GND
C12
VCCA
100 nF 1 µF / X5R
C11
100 nF 100 nF 100 nF
C5
GND
VCCA_CORE
DVDD_CORE
2 10 µF / tantalum
SB1
+5V
GND
GND
GND
MDI O
NFE31PT222Z1E9L
RXD_3
GND
L4
RXD_1
RXDV AFBR_VCC_2
RXER
C3
1
12 pF
TXCLK
TXD_0
C21
C20
TXD_2
100 nF
10 µF / tantalum
2
GND
COL
GND
GND
GND
J1
Connector 40 MII
GND
MDC
RXD_ 2
RXD_ 0
RXCL K
TXER
TXEN
TXD_ 1
TXD_ 3
CRS
+5 V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
41
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
R1
5.6 KΩ
IREF
UM0858
ST802RT1 FX mode Ethernet PHY demonstration board - BOM and schematic
Figure 11. ST802RT1 FX mode Ethernet PHY demonstration board - schematic - part 2
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TXD_3
RXDV
TXCLK
3.3 V
+5 V
L2
L1
TXD_3
RXDV
TXCLK
GND
2
2.2 KΩ
R19
2.2 KΩ
R18
2
2
2.2 KΩ
R17
NFE31PT222Z1E9L
GND
NFE31PT222Z1E9L
VCCA
JP10
GND
1
DVDD
3
JP9
GND
1
DVDD
3
JP8
GND
1
DVDD
3
JP6
JP4
DVDD
RXD_1
RXD_0
COL
JP7
JP5
GND
2
1
RXD_1
RXD_0
2
2.2 KΩ
R22
2.2 KΩ
R21
2
2
LED8
GND
1
JP13
DVDD
3
GND
1
JP12
DVDD
3
GND
1
JP11
DVDD
3
R32
470 Ω
GND
2
1
3.3 V
2.2 KΩ
R20
VCCA_CORE
DVDD_CORE
COL
3.3 V
J8
RXD_3
RXD_2
GND
3.3 V
J2
LE D_LINK
LED_SPEED
JP19 3.3 V
C16
LED_ACT
10 µF / 6.3 V
/ Tantalum
3.3 V LDO
GND GND
U3 LD1117S33
3 V
2
IN VOUT 4
VOUT
GND
C14
C15
1
100 nF
100 nF
JP20
STPS2L40UF 1
C13
10 µF / 6.3 V / 2
Tantalum
GND GND
D1
RXD_3
RXD_2
1
LED2
2
1
LED4
2
1
2.2 KΩ
R24
2
2
2
2
DVDD
3
1
LED6
LED5
R30 2 KΩ
2
1
LED3
R28 2 KΩ
2
1
GND
1
JP15
GND
DVDD
3
1
2.2 KΩ
JP14
R23
Green
LED_LINK/AN_EN
Red
LED_SPEED/AN0
Yellow
LED_ACT/AN1
LED1
R26 2 KΩ
GND
GND
GND
GND
GND
220 Ω
R29
470 Ω
R27
330 Ω
R25
2
2
2
AM00646
J7
J6
J5
J4
J3
GND
1
JP18
DVDD
3
GND
1
JP17
DVDD
3
JP16
GND
1
DVDD
3
ST802RT1 FX mode Ethernet PHY demonstration board - BOM and schematic
UM0858
Figure 12. ST802RT1 FX mode Ethernet PHY demonstration board - schematic - part 3
UM0858
Revision history
Revision history
Table 14.
Document revision history
Date
Revision
30-Nov-2009
1
Changes
Initial release.
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UM0858
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