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Download LT1886 - Dual 700MHz, 200mA Operational Amplifier
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LT1886 Dual 700MHz, 200mA Operational Amplifier U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 700MHz Gain Bandwidth ±200mA Minimum IOUT Low Distortion: –72dBc at 1MHz, 4VP-P, 25Ω, AV = 2 Stable in AV ≥ 10, Simple Compensation for AV < 10 ±4.3V Minimum Output Swing, VS = ±6V, RL = 25Ω 7mA Supply Current per Amplifier 200V/µs Slew Rate Stable with 1000pF Load 6nV/√Hz Input Noise Voltage 2pA/√Hz Input Noise Current 4mV Maximum Input Offset Voltage 4µA Maximum Input Bias Current 400nA Maximum Input Offset Current ±4.5V Minimum Input CMR, VS = ±6V Specified at ±6V, ±2.5V U APPLICATIO S ■ ■ ■ ■ DSL Modems xDSL PCI Cards USB Modems Line Drivers The LT®1886 is a 200mA minimum output current dual op amp with outstanding distortion performance. The amplifiers are gain-of-ten stable, but can be easily compensated for lower gains. The LT1886 features balanced, high impedance inputs with 4µA maximum input bias current, and 4mV maximum input offset voltage. Single supply applications are easy to implement and have lower total noise than current feedback amplifier implementations. The output drives a 25Ω load to ±4.3V with ±6V supplies. On ±2.5V supplies the output swings ±1.5V with a 100Ω load. The amplifier is stable with a 1000pF capacitive load which makes it useful in buffer and cable driver applications. The LT1886 is manufactured on Linear Technology’s advanced low voltage complementary bipolar process and is available in a thermally enhanced SO-8 package. , LTC and LT are registered trademarks of Linear Technology Corporation. U TYPICAL APPLICATIO Single 12V Supply ADSL Modem Line Driver 12V ADSL Modem Line Driver Distortion 0.1µF IN + + –60 12.4Ω VS = 12V AV = 10 f = 200kHz 100Ω LINE 1:2 TRANSFORMER – 909Ω 10k 20k 1:2* 100Ω 100Ω 1µF 10k 20k 1µF 100Ω 909Ω – IN – 1/2 LT1886 + –70 HD2 –80 –90 HD3 *COILCRAFT X8390-A OR EQUIVALENT 12.4Ω 0.1µF HARMONIC DISTORTION (dBc) 1/2 LT1886 1886 TA01 –100 0 2 4 6 8 10 12 LINE VOLTAGE (VP-P) 14 16 1886 TA01a www.BDTIC.com/Linear 1 LT1886 W W W AXI U U ABSOLUTE RATI GS U U W PACKAGE/ORDER I FOR ATIO (Note 1) Total Supply Voltage (V + to V –) ........................... 13.2V Input Current (Note 2) ....................................... ±10mA Input Voltage (Note 2) ............................................ ±VS Maximum Continuous Output Current (Note 3) DC ............................................................... ±100mA AC ............................................................... ±300mA Operating Temperature Range (Note 10) – 40°C to 85°C Specified Temperature Range (Note 9) .. – 40°C to 85°C Maximum Junction Temperature ......................... 150°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C ORDER PART NUMBER TOP VIEW OUT A 1 –IN A 2 A +IN A 3 V– 4 8 V+ 7 OUT B 6 –IN B 5 +IN B LT1886CS8 B S8 PART MARKING S8 PACKAGE 8-LEAD PLASTIC SO 1886 TJMAX = 150°C, θJA = 80°C/W (Note 4) Consult factory for parts specified with wider operating temperature ranges. ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±6V, VCM = 0V, pulse power tested unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 5) MIN TYP MAX 1 4 5 mV mV ● Input Offset Voltage Drift IOS (Note 8) ● Input Offset Current 3 17 µV/°C 150 400 600 nA nA 1.5 4 6 µA µA ● IB Input Bias Current UNITS ● en Input Noise Voltage f = 10kHz 6 nV/√Hz in Input Noise Current f = 10kHz 2 pA/√Hz RIN Input Resistance VCM = ±4.5V Differential 10 35 MΩ kΩ CIN Input Capacitance 2 pF Input Voltage Range (Positive) Input Voltage Range (Negative) CMRR PSRR AVOL 5 ● ● 4.5 VCM = ±4.5V ● 77 98 Minimum Supply Voltage Guaranteed by PSRR ● Power Supply Rejection Ratio VS = ±2V to ±6.5V 86 ● 80 78 dB dB 5.0 4.5 12 ● V/mV V/mV 4.5 4.0 12 ● V/mV V/mV 4.85 4.70 5 ● ±V ±V 4.30 4.10 4.6 ● ±V ±V 4.30 4.10 4.5 ● ±V ±V 800 500 mA mA Common Mode Rejection Ratio Large-Signal Voltage Gain VOUT = ±4V, RL = 100Ω VOUT = ±4V, RL = 25Ω VOUT Output Swing RL = 100Ω, 10mV Overdrive RL = 25Ω, 10mV Overdrive IOUT = 200mA, 10mV Overdrive ISC 2 Short-Circuit Current (Sourcing) Short-Circuit Current (Sinking) 5.9 –5.2 –4.5 dB ±2 (Note 3) www.BDTIC.com/Linear V V V LT1886 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±6V, VCM = 0V, pulse power tested unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS SR Slew Rate AV = –10 (Note 6) ● Full Power Bandwidth MIN TYP 133 110 200 V/µs V/µs 8 MHz 700 MHz 4V Peak (Note 7) MAX UNITS GBW Gain Bandwidth f = 1MHz tr, tf Rise Time, Fall Time AV = 10, 10% to 90% of 0.1V, RL = 100Ω 4 ns Overshoot AV = 10, 0.1V, RL = 100Ω 1 % Propagation Delay AV = 10, 50% VIN to 50% VOUT, 0.1V, RL = 100Ω 2.5 ns Settling Time 6V Step, 0.1% 50 ns Harmonic Distortion HD2, AV = 10, 2VP-P, f = 1MHz, RL = 100Ω/25Ω HD3, AV = 10, 2VP-P, f = 1MHz, RL = 100Ω/25Ω – 75/– 63 – 85/– 71 dBc dBc IMD Intermodulation Distortion AV = 10, f = 0.9MHz, 1MHz, 14dBm, RL = 100Ω/25Ω – 81/– 80 dBc ROUT Output Resistance AV = 10, f = 1MHz Channel Separation VOUT = ±4V, RL = 25Ω tS ● IS Supply Current 82 80 Per Amplifier 0.1 Ω 92 dB dB 7 ● 8.25 8.50 mA mA The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±2.5V, VCM = 0V, pulse power tested unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS VOS Input Offset Voltage (Note 5) MIN TYP MAX 1.5 5 6 mV mV ● Input Offset Voltage Drift IOS (Note 8) ● Input Offset Current 5 17 µV/°C 100 350 550 nA nA 1.2 3.5 5.5 µA µA ● IB Input Bias Current UNITS ● en Input Noise Voltage f = 10kHz 6 nV/√Hz in Input Noise Current f = 10kHz 2 pA/√Hz RIN Input Resistance VCM = ±1V Differential 20 50 MΩ kΩ CIN Input Capacitance 2 pF Input Voltage Range (Positive) Input Voltage Range (Negative) CMRR Common Mode Rejection Ratio VCM = ±1V AVOL Large-Signal Voltage Gain VOUT = ±1V, RL = 100Ω 10 ● ● 1 ● 75 91 dB 5.0 4.5 10 ● V/mV V/mV 4.5 4.0 10 ● V/mV V/mV 1.50 1.40 1.65 ● ±V ±V 1.35 1.25 1.50 ● ±V ±V 0.87 0.80 1 ● ±V ±V VOUT = ±1V, RL = 25Ω VOUT Output Swing RL = 100Ω, 10mV Overdrive RL = 25Ω, 10mV Overdrive IOUT = 200mA, 10mV Overdrive www.BDTIC.com/Linear 2.4 –1.7 –1 V V 3 LT1886 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VS = ±2.5V, VCM = 0V, pulse power tested unless otherwise noted. (Note 9) SYMBOL PARAMETER CONDITIONS ISC Short-Circuit Current (Sourcing) Short-Circuit Current (Sinking) (Note 3) MIN SR Slew Rate AV = –10 (Note 6) MAX UNITS 600 400 mA mA 100 V/µs V/µs 1V Peak (Note 7) 16 MHz 530 MHz 66 60 ● Full Power Bandwidth TYP GBW Gain Bandwidth f = 1MHz tr, tf Rise Time, Fall Time AV = 10, 10% to 90% of 0.1V, RL = 100Ω Overshoot AV = 10, 0.1V, RL = 100Ω 5 % Propagation Delay AV = 10, 50% VIN to 50% VOUT, 0.1V, RL = 100Ω 5 ns Harmonic Distortion HD2, AV = 10, 2VP-P, f = 1MHz, RL = 100Ω/25Ω HD3, AV = 10, 2VP-P, f = 1MHz, RL = 100Ω/25Ω – 75/– 64 – 80/– 66 dBc dBc – 77/– 85 dBc 7 IMD Intermodulation Distortion AV = 10, f = 0.9MHz, 1MHz, 5dBm, RL = 100Ω/25Ω ROUT Output Resistance AV = 10, f = 1MHz Channel Separation VOUT = ±1V, RL = 25Ω 82 80 ● IS Supply Current Per Amplifier ns 0.2 Ω 92 dB dB 5 5.75 6.25 ● Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: The inputs are protected by back-to-back diodes. If the differential input voltage exceeds 0.7V, the input current should be limited to less than 10mA. Note 3: A heat sink may be required to keep the junction temperature below absolute maximum. Note 4: Thermal resistance varies depending upon the amount of PC board metal attached to the device. θJA is specified for a 2500mm2 test board covered with 2 oz copper on both sides. Note 5: Input offset voltage is exclusive of warm-up drift. mA mA Note 6: Slew rate is measured between ±2V on a ±4V output with ±6V supplies, and between ±1V on a ±1.5V output with ±2.5V supplies. Note 7: Full power bandwidth is calculated from the slew rate: FPBW = SR/2πVP. Note 8: This parameter is not 100% tested. Note 9: The LT1886C is guaranteed to meet specified performance from 0°C to 70°C. The LT1886C is designed, characterized and expected to meet specified performance from –40°C to 85°C but is not tested or QA sampled at these temperatures. For guaranteed I-grade parts, consult the factory. Note 10: The LT1886C is guaranteed functional over the operating temperature range of –40°C to 85°C. U W TYPICAL PERFOR A CE CHARACTERISTICS COMMON MODE RANGE (V) VS = ±6V 10 VS = ±2.5V 5 V+ 3.0 –0.1 2.5 INPUT BIAS CURRENT (µA) 15 SUPPLY CURRENT (mA) Input Bias Current vs Input Common Mode Voltage Input Common Mode Range vs Supply Voltage Supply Current vs Temperature –0.2 –0.3 TA = 25°C ∆VOS > 1mV 1.5 1.0 V– –25 0 25 50 75 TEMPERATURE (°C) 100 125 1886 G01 4 2.0 VS = ±6V 1.5 VS = ±2.5V 1.0 0.5 0.5 0 –50 TA = 25°C IB = (IB + + IB –)/2 0 0 2 4 6 8 10 12 TOTAL SUPPLY VOLTAGE (V) 14 –6 1886 G02 www.BDTIC.com/Linear –4 –2 0 2 4 INPUT COMMON MODE VOLTAGE (V) 6 1886 G03 LT1886 U W TYPICAL PERFOR A CE CHARACTERISTICS Input Bias Current vs Temperature 100 IB = (IB + + IB –)/2 INPUT VOLTAGE NOISE (nV/√Hz) 3.0 2.5 2.0 VS = ±6V 1.5 1.0 VS = ±2.5V 0.5 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 10 10 en in 1 10 125 100 1000 INPUT CURRENT NOISE (pA/√Hz) TA = 25°C AV = 101 OUTPUT SHORT-CIRCUIT CURRENT (mA) 100 3.5 INPUT BIAS CURRENT (µA) Output Short-Circuit Current vs Temperature Input Noise Spectral Density 1 100k 1k 10k FREQUENCY (Hz) 900 SOURCE, VS = ±6V 800 700 SOURCE, VS = ±2.5V 600 500 SINK, VS = ±6V 400 SINK, VS = ±2.5V 300 200 ∆VIN = 0.2V 100 0 –50 –25 0 25 50 75 TEMPERATURE (°C) 100 125 1886 G05 1886 G04 1886 G06 Output Saturation Voltage vs Temperature, VS = ±6V + V –1.5 1.5 IL = 150mA IL = 200mA IL = 150mA IL = 200mA 1.0 RL = 100Ω 0.5 V– –50 –25 0 25 50 75 TEMPERATURE (°C) 100 6 VS = ±6V –0.5 RL = 100Ω 4 –1.0 –1.5 1.5 IL = 150mA IL = 200mA IL = 150mA IL = 200mA OUTPUT STEP (V) RL = 100Ω –1.0 1.0 RL = 100Ω 0.5 V– –50 125 –25 0 25 50 75 TEMPERATURE (°C) 40 VS = ±6V 40 20 30 0 20 VS = ±2.5V –20 GAIN –40 10 TA = 25°C AV = –10 RL = 100Ω 0 –10 –20 1M 10M 100M FREQUENCY (Hz) PHASE (DEG) GAIN (dB) 60 VS = ±2.5V 50 –2 100 0 125 10 20 30 40 SETTLING TIME (ns) –60 50 60 1886 G09 Output Impedance vs Frequency 100 TA = 25°C AV = –10 GAIN BANDWIDTH (MHz) 60 1mV 0 –6 800 80 VS = ±6V 10mV 2 Gain Bandwidth vs Supply Voltage 100 PHASE 1mV 1886 G08 Gain and Phase vs Frequency 80 10mV –4 1886 G07 70 Settling Time vs Output Step + 700 RL = 1k 600 RL = 100Ω 500 RL = 25Ω OUTPUT IMPEDANCE (Ω) –0.5 OUTPUT SATURATION VOLTAGE (V) OUTPUT SATURATION VOLTAGE (V) V Output Saturation Voltage vs Temperature, VS = ±2.5V 400 10 AV = 100 1 0.1 AV = 10 –80 –100 1G 1886 G10 300 0 2 4 6 8 10 12 TOTAL SUPPLY VOLTAGE (V) 14 0.01 100k 1886 G11 www.BDTIC.com/Linear 1M 10M FREQUENCY (Hz) 100M 1886 G12 5 LT1886 U W TYPICAL PERFOR A CE CHARACTERISTICS Frequency Response vs Supply Voltage, AV = 10 Frequency Response vs Supply Voltage, AV = –10 23 23 TA = 25°C AV = 10 RL = 100Ω 22 9 TA = 25°C AV = –10 RL = 100Ω 22 21 8 6 19 5 VS = ±6V 17 VS = ±2.5V 16 VS = ±6V 18 17 VS = ±2.5V 16 2 1 14 14 0 13 1M 1G 10M 100M FREQUENCY (Hz) 38 2 35 VS = ±2.5V 29 GAIN (dB) TA = 25°C AV = –1 RL = 100Ω RF = RG = 1k RC = 124Ω CC = 100pF SEE FIGURE 2 –4 –5 –6 –7 1M 1000pF 500pF 200pF 26 100pF 23 50pF 20 17 8 1M 1G 10M 100M FREQUENCY (Hz) (–) SUPPLY 40 (+) SUPPLY 20 10 100M 1886 G19 COMMON MODE REJECTION RATIO (dB) VS = ±6V AV = 10 1M 10M FREQUENCY (Hz) VS = ±2.5V 0 –50 1G –SR –25 0 25 50 75 TEMPERATURE (°C) 125 Amplifier Crosstalk vs Frequency 0 VS = ±6V TA = 25°C 90 80 70 60 50 40 30 20 10 0 100k 100 1886 G18 100 50 6 +SR 100 Common Mode Rejection Ratio vs Frequency 60 0 100k –SR 150 1886 G17 100 30 +SR 200 11 Power Supply Rejection vs Frequency 80 VS = ±6V 50 1886 G16 70 250 14 10M 100M FREQUENCY (Hz) 90 AV = –10 RL = 100Ω 300 1M 10M FREQUENCY (Hz) 100M OUTPUT TO INPUT CROSSTALK (dB) –3 350 VS = ±6V TA = 25°C AV = 10 NO RL 32 VS = ±6V Slew Rate vs Temperature SLEW RATE (V/µs) 3 –2 1G 1886 G15 Frequency Response vs Capacitive Load –1 10M 100M FREQUENCY (Hz) 1886 G14 Frequency Response vs Supply Voltage, AV = –1 0 –1 1M 1G 1886 G13 1 TA = 25°C AV = 2 RL = 100Ω RF = RG = 1k RC = 124Ω CC = 100pF SEE FIGURE 3 3 15 10M 100M FREQUENCY (Hz) VS = ±6V 4 15 13 1M GAIN (dB) GAIN (dB) 20 19 18 VS = ±2.5V 7 20 GAIN (dB) GAIN (dB) 21 POWER SUPPLY REJECTION (dB) Frequency Response vs Supply Voltage, AV = 2 –10 –20 –30 VS = ±6V AV = 10 RL = 100Ω INPUT = –20dBm –40 –50 –60 B→A –70 –80 –90 –100 1M 1886 G20 www.BDTIC.com/Linear A→B 10M 100M FREQUENCY (Hz) 1G 1886 G21 LT1886 U W TYPICAL PERFOR A CE CHARACTERISTICS Harmonic Distortion vs Frequency, AV = 10, VS = ±6V Harmonic Distortion vs Frequency, AV = 10, VS = ±2.5V –20 –20 –30 –40 2nd –50 3rd RL = 25Ω –60 –70 –90 3rd –90 2nd 3rd 3rd 10M –20 –30 –40 RL = 25Ω –50 3rd –80 2nd –90 –90 3rd –100 –100 3rd 1 10 100 LOAD RESISTANCE (Ω) 1k 2 4 6 8 10 OUTPUT VOLTAGE (VP-P) 0 2nd –80 2nd 0 2 –40 –50 –60 RL = 25Ω –70 2nd 3rd 2nd –90 3rd –100 –30 –80 3rd –90 12 1886 G28 RL = 100Ω 3rd –100 4 6 8 10 OUTPUT VOLTAGE (VP-P) RL = 100Ω 1 2 3 4 OUTPUT VOLTAGE (VP-P) 5 1886 G27 HIGHEST HARMONIC DISTORTION (dBc) –70 RL = 100Ω 3rd –30 –20 RL = 25Ω 2nd Harmonic Distortion vs Output Current, VS = ±6V TA = 25°C RF = RG = 1k RC = 124Ω CC = 100pF f = 1MHz SEE FIGURE 3 –10 –50 –60 3rd –80 Harmonic Distortion vs Output Swing, AV = 2, VS = ±2.5V DISTORTION (dBc) –40 2nd –70 12 0 –30 –60 1886 G26 0 –20 RL = 25Ω –50 –100 0 Harmonic Distortion vs Output Swing, AV = 2, VS = ±6V –10 –40 –90 RL = 100Ω 1886 G25 TA = 25°C RF = RG = 1k RC = 124Ω CC = 100pF f = 1MHz SEE FIGURE 3 TA = 25°C f = 1MHz –10 –30 2nd DISTORTION (dBc) Harmonic Distortion vs Output Swing, AV = 10, VS = ±2.5V –20 –70 –80 1k 0 –60 2nd –70 10 100 LOAD RESISTANCE (Ω) 1886 G24 DISTORTION (dBc) DISTORTION (dBc) DISTORTION (dBc) –50 3rd 1 TA = 25°C f = 1MHz –10 –40 2nd –70 –100 1M FREQUENCY (Hz) 0 TA = 25°C VS = ±2.5V AV = 10 2VP-P OUT f = 1MHz –60 –60 Harmonic Distortion vs Output Swing, AV = 10, VS = ±6V 0 –30 –50 1886 G23 Harmonic Distortion vs Resistive Load –20 –40 –90 1886 G22 –10 –30 –80 RL = 100Ω –100 100k 10M 2nd –70 –80 1M FREQUENCY (Hz) RL = 25Ω –60 2nd RL = 100Ω –20 –40 –50 TA = 25°C VS = ±6V AV = 10 2VP-P OUT f = 1MHz –10 –30 –80 –100 100k TA = 25°C AV = 10 2VP-P OUT –10 DISTORTION (dBc) DISTORTION (dBc) 0 0 TA = 25°C AV = 10 2VP-P OUT –10 DISTORTION (dBc) 0 Harmonic Distortion vs Resistive Load 0 TA = 25°C AV = 10 f = 1MHz –40 RL = 5Ω –50 RL = 10Ω –60 RL = 25Ω –70 –80 1 2 3 4 OUTPUT VOLTAGE (VP-P) 5 0 1886 G29 www.BDTIC.com/Linear 100 200 300 400 PEAK OUTPUT CURRENT (mA) 500 1886 G30 7 LT1886 U W TYPICAL PERFOR A CE CHARACTERISTICS Harmonic Distortion vs Output Current, VS = ±2.5V Undistorted Output Swing vs Frequency 12 TA = 25°C AV = 10 f = 1MHz –40 OUTPUT VOLTAGE SWING (VP-P) HIGHEST HARMONIC DISTORTION (dBc) –30 RL = 5Ω –50 RL = 10Ω –60 RL = 25Ω –70 –80 0 50 100 150 200 PEAK OUTPUT CURRENT (mA) VS = ±6V 10 8 6 VS = ±2.5V 4 2 0 100k 250 TA = 25°C AV = 10 RL = 100Ω 1% DISTORTION 1M FREQUENCY (Hz) 1886 G32 1886 G30 Small-Signal Transient, AV = 10 1886 G33 Large-Signal Transient, AV = 10 1886 G36 8 10M Small-Signal Transient, AV = –10 Small-Signal Transient, AV = 10, CL = 1000pF 1886 G34 Large-Signal Transient, AV = –10 1886 G35 Large-Signal Transient, AV = 10, CL = 1000pF 1886 G37 www.BDTIC.com/Linear 1886 G38 LT1886 U U W U APPLICATIO S I FOR ATIO Input Considerations The inputs of the LT1886 are an NPN differential pair protected by back-to-back diodes (see the Simplified Schematic). There are no series protection resistors onboard which would degrade the input voltage noise. If the inputs can have a voltage difference of more than 0.7V, the input current should be limited to less than 10mA with external resistance (usually the feedback resistor or source resistor). Each input also has two ESD clamp diodes—one to each supply. If an input drive exceeds the supply, limit the current with an external resistor to less than 10mA. The LT1886 design is a true operational amplifier with high impedance inputs and low input bias currents. The input offset current is a factor of ten lower than the input bias current. To minimize offsets due to input bias currents, match the equivalent DC resistance seen by both inputs. The low input noise current can significantly reduce total noise compared to a current feedback amplifier, especially for higher source resistances. Layout and Passive Components With a gain bandwidth product of 700MHz the LT1886 requires attention to detail in order to extract maximum performance. Use a ground plane, short lead lengths and a combination of RF-quality supply bypass capacitors (i.e., 470pF and 0.1µF). As the primary applications have high drive current, use low ESR supply bypass capacitors (1µF to 10µF). For best distortion performance with high drive current a capacitor with the shortest possible trace lengths should be placed between Pins 4 and 8. The optimum location for this capacitor is on the back side of the PC board. The DSL driver demo board (DC304) for this part uses a Taiyo Yuden 10µF ceramic (TMK432BJ106MM). The parallel combination of the feedback resistor and gain setting resistor on the inverting input can combine with the input capacitance to form a pole which can cause frequency peaking. In general, use feedback resistors of 1kΩ or less. Thermal Issues The LT1886 enhanced θJA SO-8 package has the V– pin fused to the lead frame. This thermal connection increases the efficiency of the PC board as a heat sink. The PCB material can be very effective at transmitting heat between the pad area attached to the V– pin and a ground or power plane layer. Copper board stiffeners and plated throughholes can also be used to spread the heat generated by the device. Table 1 lists the thermal resistance for several different board sizes and copper areas. All measurements were taken in still air on 3/32" FR-4 board with 2oz copper. This data can be used as a rough guideline in estimating thermal resistance. The thermal resistance for each application will be affected by thermal interactions with other components as well as board size and shape. Table 1. Fused 8-Lead SO Package COPPER AREA (2oz) TOPSIDE BACKSIDE TOTAL COPPER AREA θJA 2500 sq. mm 2500 sq. mm 5000 sq. mm 80°C/W 1000 sq. mm 2500 sq. mm 3500 sq. mm 92°C/W 600 sq. mm 2500 sq. mm 3100 sq. mm 96°C/W 180 sq. mm 2500 sq. mm 2680 sq. mm 98°C/W 180 sq. mm 1000 sq. mm 1180 sq. mm 112°C/W 180 sq. mm 600 sq. mm 780 sq. mm 116°C/W 180 sq. mm 300 sq. mm 480 sq. mm 118°C/W 180 sq. mm 100 sq. mm 280 sq. mm 120°C/W 180 sq. mm 0 sq. mm 180 sq. mm 122°C/W Calculating Junction Temperature The junction temperature can be calculated from the equation: TJ = (PD)(θJA) + TA TJ = Junction Temperature TA = Ambient Temperature PD = Device Dissipation θJA = Thermal Resistance (Junction-to-Ambient) As an example, calculate the junction temperature for the circuit in Figure 1 assuming an 85°C ambient temperature. The device dissipation can be found by measuring the supply currents, calculating the total dissipation and then subtracting the dissipation in the load. www.BDTIC.com/Linear 9 LT1886 U U W U APPLICATIO S I FOR ATIO Typical Performance Curve of Frequency Response vs Capacitive Load shows the peaking for various capacitive loads. 6V + – 909Ω 4V 100Ω 50Ω –4V 1K 100Ω f = 1MHz – + Compensation –6V 1886 F01 Figure 1. Thermal Calculation Example The dissipation for the amplifiers is: PD = (63.5mA)(12V) – (4V/√2)2/(50) = 0.6W The total package power dissipation is 0.6W. When a 2500 sq. mm PC board with 2oz copper on top and bottom is used, the thermal resistance is 80°C/W. The junction temperature TJ is: TJ = (0.6W)(80°C/W) + 85°C = 133°C The maximum junction temperature for the LT1886 is 150°C so the heat sinking capability of the board is adequate for the application. If the copper area on the PC board is reduced to 180 sq. mm the thermal resistance increases to 122°C/W and the junction temperature becomes: TJ = (0.6W)(122°C/W) + 85°C = 158°C which is above the maximum junction temperature indicating that the heat sinking capability of the board is inadequate and should be increased. Capacitive Loading The LT1886 is stable with a 1000pF capacitive load. The photo of the small-signal response with 1000pF load in a gain of 10 shows 50% overshoot. The photo of the largesignal response with a 1000pF load shows that the output slew rate is not limited by the short-circuit current. The 10 This stability is useful in the case of directly driving a coaxial cable or twisted pair that is inadvertently unterminated. For best pulse fidelity, however, a termination resistor of value equal to the characteristic impedance of the cable or twisted pair (i.e., 50Ω/75Ω/100Ω/135Ω) should be placed in series with the output. The other end of the cable or twisted pair should be terminated with the same value resistor to ground. The LT1886 is stable in a gain 10 or higher for any supply and resistive load. It is easily compensated for lower gains with a single resistor or a resistor plus a capacitor. Figure␣ 2 shows that for inverting gains, a resistor from the inverting node to AC ground guarantees stability if the parallel combination of RC and RG is less than or equal to RF/9. For lowest distortion and DC output offset, a series capacitor, CC, can be used to reduce the noise gain at lower frequencies. The break frequency produced by RC and CC should be less than 15MHz to minimize peaking. The Typical Curve of Frequency Response vs Supply Voltage, AV = –1 shows less than 1dB of peaking for a break frequency of 12.8MHz. RF RG Vi RC CC (OPTIONAL) Vo – + = Vi Vo –RF RG (RC || RG) ≤ RF/9 1 < 15MHz 2πRCCC 1886 F02 Figure 2. Compensation for Inverting Gains Figure 3 shows compensation in the noninverting configuration. The RC, CC network acts similarly to the inverting case. The input impedance is not reduced because the network is bootstrapped. This network can also be placed between the inverting input and an AC ground. Another compensation scheme for noninverting circuits is shown in Figure 4. The circuit is unity gain at low frequency and a gain of 1 + RF/RG at high frequency. The DC output offset is reduced by a factor of ten. The techniques of www.BDTIC.com/Linear LT1886 U U W U APPLICATIO S I FOR ATIO Figures 3 and 4 can be combined as shown in Figure 5. The gain is unity at low frequencies, 1 + RF/RG at mid-band and for stability, a gain of 10 or greater at high frequencies. termination resistor is used, a capacitor to ground at the load can eliminate ringing. Line Driving Back-Termination Vo + Vi RC Vi RF RG (RC || RG) ≤ RF/9 Vo – CC (OPTIONAL) =1+ 1 RF < 15MHz 2πRCCC RG 1886 F03 Figure 3. Compensation for Noninverting Gains Vi Vo + = 1 (LOW FREQUENCIES) Vi – RF =1+ VO (HIGH FREQUENCIES) RG RG ≤ RF/9 RF 1 < 15MHz 2πRGCC RG CC 1886 F04 The standard method of cable or line back-termination is shown in Figure 6. The cable/line is terminated in its characteristic impedance (50Ω, 75Ω, 100Ω, 135Ω, etc.). A back-termination resistor also equal to to the chararacteristic impedance should be used for maximum pulse fidelity of outgoing signals, and to terminate the line for incoming signals in a full-duplex application. There are three main drawbacks to this approach. First, the power dissipated in the load and back-termination resistors is equal so half of the power delivered by the amplifier is wasted in the termination resistor. Second, the signal is halved so the gain of the amplifer must be doubled to have the same overall gain to the load. The increase in gain increases noise and decreases bandwidth (which can also increase distortion). Third, the output swing of the amplifier is doubled which can limit the power it can deliver to the load for a given power supply voltage. Figure 4. Alternate Noninverting Compensation Vi + Vi RC Vo VO RL RF RBT = RL CC RF Vo RF Vi = 1 2 (1 + RF/RG) 1886 F06 AT MEDIUM FREQUENCIES RG =1+ Vo RG = 1 AT LOW FREQUENCIES Vi =1+ CBIG RBT – – RG CABLE OR LINE WITH CHARACTERISTIC IMPEDANCE RL + RF Figure 6. Standard Cable/Line Back-Termination AT HIGH FREQUENCIES (RC || RG) 1886 F05 Figure 5. Combination Compensation Output Loading The LT1886 output stage is very wide bandwidth and able to source and sink large currents. Reactive loading, even isolated with a back-termination resistor, can cause ringing at frequencies of hundreds of MHz. For this reason, any design should be evaluated over a wide range of output conditions. To reduce the effects of reactive loading, an optional snubber network consisting of a series RC across the load can provide a resistive load at high frequency. Another option is to filter the drive to the load. If a back- An alternate method of back-termination is shown in Figure 7. Positive feedback increases the effective backtermination resistance so RBT can be reduced by a factor of n. To analyze this circuit, first ground the input. As RBT␣ = RL/n, and assuming RP2>>RL we require that: Va = Vo (1 – 1/n) to increase the effective value of RBT by n. Vp = Vo (1 – 1/n)/(1 + RF/RG) Vo = Vp (1 + RP2/RP1) Eliminating Vp, we get the following: (1 + RP2/RP1) = (1 + RF/RG)/(1 – 1/n) www.BDTIC.com/Linear 11 LT1886 U U W U APPLICATIO S I FOR ATIO For example, reducing RBT by a factor of n = 4, and with an amplifer gain of (1 + RF/RG) = 10 requires that RP2/RP1 =␣ 12.3. Note that the overall gain is increased: RP2 / (RP2 + RP1) Vo = Vi (1+ 1/ n) / (1+ RF / RG ) − RP1 / (RP2 + RP1) [ ] [ ] A simpler method of using positive feedback to reduce the back-termination is shown in Figure 8. In this case, the drivers are driven differentially and provide complementary outputs. Grounding the inputs, we see there is inverting gain of –RF/RP from –Vo to Va Va = Vo (RF/RP) and assuming RP >> RL, we require Va = Vo (1 – 1/n) solving RF/RP = 1 – 1/n So to reduce the back-termination by a factor of 3 choose RF/RP = 2/3. Note that the overall gain is increased to: Vo/Vi = (1 + RF/RG + RF/RP)/[2(1 – RF/RP)] ADSL Driver Requirements The LT1886 is an ideal choice for ADSL upstream (CPE) modems. The key advantages are: ±200mA output drive with only 1.7V worst-case total supply voltage headroom, high bandwidth, which helps achieve low distortion, low quiescent supply current of 7mA per amplifier and a space-saving, thermally enhanced SO-8 package. An ADSL remote terminal driver must deliver an average power of 13dBm (20mW) into a 100Ω line. This corresponds to 1.41VRMS into the line. The DMT-ADSL peak-toaverage ratio of 5.33 implies voltage peaks of 7.53V into the line. Using a differential drive configuration and transformer coupling with standard back-termination, a transformer ratio of 1:2 is well suited. This is shown on the front page of this data sheet along with the distortion performance vs line voltage at 200kHz, which is beyond ADSL requirements. Note that the distortion is better than –73dBc for all swings up to 16VP-P into the line. The gain of this circuit from the differential inputs to the line voltage is 10. Lower gains are easy to implement using the compensation techniques of Figure 5. Table 2 shows the drive requirements for this standard circuit. The above design is an excellent choice for desktop applications and draws typically 550mW of power. For portable applications, power savings can be achieved by reducing the back-termination resistor using positive feedback as shown in Figure 9. The overall gain of this circuit is also 10, but the power consumption has been reduced to 350mW, a savings of 36% over the previous design. Note that the reduction of the back-termination resistor has allowed use of a 1:1 transformer ratio. RP2 RP1 Vi + Va RBT VP – RL FOR RBT = RF RF 1886 F07 FOR RBT = RG RL ( )( 1+ n RF RP1 RG RP1 + RP2 ) Vo Vi = 1 + 1/n ( ) 1+ RF 1– RG – RL RF n Vi RG Figure 7. Back-Termination Using Positive Feedback + –Va = RF + RG RF RP ( ) 2 1– RF RP RBT RP1 –Vi RF 1+ Vo – RP2 + RP1 n RP RP 1 =1– RL 1 n= RL RP RP2/(RP2 + RP1) 12 Va RBT Vo – RG + Vi Vo –Vo 1886 F08 Figure 8. Back-Termination Using Differential Positive Feedback www.BDTIC.com/Linear LT1886 U U W U APPLICATIO S I FOR ATIO Table 2. ADSL Upstream Driver Designs STANDARD LOW POWER Line Impedance 100Ω 100Ω Line Power 13dBm 13dBm 5.33 5.33 Peak-to-Average Ratio Transformer Turns Ratio 2 1 25Ω 100Ω Back-Termination Resistors 12.5Ω 8.35Ω Transformer Insertion Loss 1dB 0.5dB Average Amplifier Swing 0.79VRMS 0.87VRMS Average Amplifier Current 31.7mARMS 15mARMS Reflected Impedance Peak Amplifier Swing 4.21V Peak 4.65V Peak Peak Amplifier Current 169mA Peak 80mA Peak 550mW 350mW Single 12V Single 12V Total Average Power Consumption Supply Voltage Table 2 compares the two approaches. It may seem that the low power design is a clear choice, but there are further system issues to consider. In addition to driving the line, the amplifiers provide back-termination for signals that are received simultaneously from the line. In order to reject the drive signal, a receiver circuit is used such as shown in Figure 10. Taking advantage of the differential nature of the signals, the receiver can subtract out the drive signal and amplify the received signal. This method works well for standard back-termination. If the backtermination resistors are reduced by positive feedback, a portion of the received signal also appears at the amplifier outputs. The result is that the received signal is attenuated by the same amount as the reduction in the back-termination resistor. Taking into account the different transformer turns ratios, the received signal of the low power design will be one third of the standard design received signal. The reduced signal has system implications for the sensitivity of the receiver. The power reduction may, or may not, be an acceptable system tradeoff for a given design. Demo Board Demo board DC304 has been created to provide a versatile platform for a line driver/receiver design. (Figure 11 shows a complete schematic.) The board is set up for either single or dual supply designs with Jumpers 1–4. The LT1886 is set up for differential, noninverting gain of 3. Each amp is configured as in Figure 5 for maximum flexibility. The amplifiers drive a 1:2 transformer through back-termination resistors that can be reduced with optional positive feedback. The secondary of the transformer can be isolated from the primary with Jumper 5. A differential receiver is included using the LT1813, a dual 100MHz, 750V/µs operational amplifier. The receiver gain from the transformer secondary is 2, and the drive signals are rejected by approximately a factor of 14dB. Other optional components include filter capacitors and an RC snubber network at the transformer primary. RBT Va VL 1:n RL RBT –Va Vi –VL + 8.45Ω RF RD – 1k 1.21k 523Ω – 1:1 + 1k 1.21k – RL + VRX AV = 10 – 8.45Ω 2n2 VBIAS LT1813 – –Vi = REFLECTED IMPEDANCE n2 RL 2n2 = ATTENUATION OF Va + RBT + 523Ω RL LT1813 100Ω 1µF RG + RF RL RD SET RG = RD RG 2n2 RL 2n2 + RBT 1886 F10 1886 F09 Figure 9. Power Saving ADSL Modem Driver Figure 10. Receiver Configuration www.BDTIC.com/Linear 13 LT1886 U U W U APPLICATIO S I FOR ATIO V+ C1 0.1µF C8 0.1µF C9 470pF JP1 TP1 3 +DRV V R1 10k C3 1µF R3 20k + R20 130Ω C19 100pF 8 + 1 LT1886 2 – R2 10k C21 470pF TP5 R5 1k 9 LINE OUT 7 10 C5 1µF V– R8 499Ω R4 20k –DRV R7 12.4Ω R19 C20 100pF R4 130Ω 6 – 5 + R7 1k TP3 7 LT1886 JP2 C10 470pF C12 0.1µF 8 – –RCV 1 V+ + C15 1µF C18 10µF +RCV GND 7 C16 10µF + V– C17 1µF 2 COILCRAFT X8390-A OR EQUIVALENT R12 2k R13 1k LT1813 V+ C14 10µF + 3 + 5 LT1813 – 6 R15 2k 4 JP4 C13 0.1µF V– R14 4.02k R16 1k C7 10pF Figure 11. LT1886, LT1813 DSL Demo Board (DC304) 14 SEPARATE SECONDARY GROUND C22 470pF R11 4.02k V+ JP5 TP4 C6 10pF C11 0.1µF 2 C23 470pF R10 12.4Ω 4 C2 0.1µF TP6 4 6 R18 R6 499Ω C4 1µF JP3 TP2 R9 12.4Ω www.BDTIC.com/Linear 1886 F11 LT1886 W W SI PLIFIED SCHE ATIC V+ I4 Q8 Q4 Q3 Q5 OUT Q6 D1 –IN Q7 C1 Q2 Q1 Q9 +IN D2 I1 I2 I3 V– 1886 SS U PACKAGE DESCRIPTIO Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.189 – 0.197* (4.801 – 5.004) 8 7 6 5 0.150 – 0.157** (3.810 – 3.988) 0.228 – 0.244 (5.791 – 6.197) 1 0.010 – 0.020 × 45° (0.254 – 0.508) 0.008 – 0.010 (0.203 – 0.254) 0.053 – 0.069 (1.346 – 1.752) 0°– 8° TYP 0.016 – 0.050 (0.406 – 1.270) 0.014 – 0.019 (0.355 – 0.483) TYP *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 2 3 4 0.004 – 0.010 (0.101 – 0.254) 0.050 (1.270) BSC www.BDTIC.com/Linear Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. SO8 1298 15 LT1886 U TYPICAL APPLICATIO Considerations for Fault Protection The basic line driver design presents a direct DC path between the outputs of the two amplifiers. An imbalance in the DC biasing potentials at the noninverting inputs through either a fault condition or during turn-on of the system can create a DC voltage differential between the two amplifier outputs. This condition can force a considerable amount of current, 500mA or more, to flow as it is limited only by the small valued back-termination resistors and the DC resistance of the transformer primary. This high current can possibly cause the power supply voltage source to drop significantly impacting overall system performance. If left unchecked, the high DC current can heat the LT1886 to destruction. Using DC blocking capacitors to AC couple the signal to the transformer eliminates the possibility for DC current to flow under any conditions. These capacitors should be sized large enough to not impair the frequency response characteristics required for the data transmission. Another important fault related concern has to do with very fast high voltage transients appearing on the telephone line (lightning strikes for example). TransZorbsTM, varistors and other transient protection devices are often used to absorb the transient energy, but in doing so also create fast voltage transitions themselves that can be coupled through the transformer to the outputs of the line driver. Several hundred volt transient signals can appear at the primary windings of the transformer with current into the driver outputs limited only by the back termination resistors. While the LT1886 has clamps to the supply rails at the output pins, they may not be large enough to handle the significant transient energy. External clamping diodes, such as BAV99s, at each end of the transformer primary help to shunt this destructive transient energy away from the amplifier outputs. TransZorb is a registered trademark of General Instruments, GSI Split Supply ±5V ADSL CPE Line Driver 5V 3 130Ω 5V 8 + 2 6.19Ω BAV99** –5V – 1k 100pF + 1 1/2 LT1886 0.47µF** VL 1:2* 2k 866Ω + =5 (ASSUME 0.5dB TRANSFORMER POWER LOSS) VIN REFLECTED LINE IMPEDANCE = 100Ω / 22 = 25Ω VIN 100Ω VL – EFFECTIVE TERMINATION = 2 • 6.19 • 866Ω 1k 100pF 6 – 5 + = 24.8Ω EACH AMPLIFIER: 0.56VRMS, 29.9mARMS ±3V PEAK, ±160mA PEAK 1/2 LT1886 130Ω 2kΩ 1kΩ – 2k 7 6.19Ω 4 *COILCRAFT X8390-A OR EQUIVALENT **SEE TEXT REGARDING FAULT PROTECTION 5V BAV99** 0.47µF** –5V 1886 TA02 –5V RELATED PARTS PART NUMBER DESCRIPTION LT1207 Dual 250mA, 60MHz Current Feedback Amplifier Shutdown/Current Set Function LT1361 Dual 50MHz, 800V/µs Op Amp ±15V Operation, 1mV VOS, 1µA IB LT1396 Dual 400MHz, 800V/µs Current Feedback Amplifier 4.6mA Supply Current Set, 80mA IOUT LT1497 Dual 125mA, 50MHz Current Feedback Amplifier 900V/µs Slew Rate LT1795 Dual 500mA, 50MHz Current Feedback Amplifier Shutdown/Current Set Function, ADSL CO Driver LT1813 Dual 100MHz, 750V/µs, 8nV/√Hz Op Amp Low Noise, Low Power Differential Receiver 16 COMMENTS www.BDTIC.com/Linear Linear Technology Corporation 1886fa LT/LCG 0301 2K REV A • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com LINEAR TECHNOLOGY CORPORATION 1999